MVSAS: Update chip initialization
PATCH 1/7 MVSAS: Update chip initialization
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60ba00f2f2263c52e4b2f5a614b1800a36f4cb9eMon Sep 17 00:00:00 2001
From: andy <[email protected]>
Date: Fri, 6 Nov 2009 16:54:50 +0800
Subject: [PATCH 1/6] Update chip initialization
Update chip init code to enhance performance,correct some settings for 6G phy negotiation.
Signed-off-by Andy <[email protected]>
Signed-off-by Jacky <[email protected]>
Signed-off-by Ke <[email protected]>
--- drivers/scsi/mvsas/mv_64xx.c | 18 +++++++++++++----- drivers/scsi/mvsas/mv_94xx.c | 41 ++++++++++++++++++++++++++++------------- drivers/scsi/mvsas/mv_94xx.h | 5 +++-- drivers/scsi/mvsas/mv_chips.h | 5 ----- 4 files changed, 44 insertions(+), 25 deletions(-)
drivers/scsi/mvsas/mv_64xx.c +13 -5
@@ -373,15 +373,23 @@ static int __devinit mvs_64xx_init(struct mvs_info *mvi)/* reset CMD queue */ tmp =mr32 (MVS_PCS ); tmp |=PCS_CMD_RST ; + tmp &= ~PCS_SELF_CLEAR ; + +/* enable cmd_cmpl bit self-clearing */ +if (mvi->flags &MVF_MSI ) + tmp |=PCS_SELF_CLEAR ; +mw32 (MVS_PCS , tmp);/* interrupt coalescing may cause missing HW interrput in some case, * and the max count is 0x1ff, while our max slot is 0x200, * it will make count 0. */ tmp =0 ; -mw32 (MVS_INT_COAL , tmp); - - tmp =0x100 ; +if (MVS_CHIP_SLOT_SZ >0x1ff ) +mw32 (MVS_INT_COAL ,0x1ff |COAL_EN ); +else +mw32 (MVS_INT_COAL ,MVS_CHIP_SLOT_SZ |COAL_EN ); + tmp =0x10400 ;mw32 (MVS_INT_COAL_TMOUT , tmp);/* ladies and gentlemen, start your engines */
@@ -393,8 +401,8 @@ static int __devinit mvs_64xx_init(struct mvs_info *mvi) PCS_CMD_EN | PCS_CMD_STOP_ERR);/* enable completion queue interrupt */ - tmp = (CINT_PORT_MASK |CINT_DONE |CINT_MEM |CINT_SRS |CINT_CI_STOP | -CINT_DMA_PCIE ); + tmp = (CINT_PORT_MASK |CINT_DONE |CINT_MEM | +CINT_SRS |CINT_CI_STOP |CINT_DMA_PCIE );mw32 (MVS_INT_MASK , tmp);
drivers/scsi/mvsas/mv_94xx.c +28 -13
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drivers/scsi/mvsas/mv_94xx.h +3 -2
@@ -100,6 +100,7 @@ enum hw_registers {MVS_P4_VSR_DATA =0x254 ,/* phy4 VSR data */ MVS_PA_VSR_ADDR =0x290 ,/* All port VSR addr */ MVS_PA_VSR_PORT =0x294 ,/* All port VSR data */ + MVS_COMMAND_ACTIVE = 0x300, /* ACTIVE COMMAND */ }; enum pci_cfg_registers {
@@ -129,8 +130,8 @@ enum sas_sata_vsp_regs {enum chip_register_bits {PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 <<8 ), -PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 <<8 ), -PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (12 ), +PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 <<12 ), +PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16 ),PHY_NEG_SPP_PHYS_LINK_RATE_MASK = (0x3 <<PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET ), };
drivers/scsi/mvsas/mv_chips.h +0 -5
@@ -190,11 +190,6 @@ static inline void __devinit mvs_phy_hacks(struct mvs_info *mvi) tmp &=0x0000ffff ; tmp |=0x00fa0000 ;mvs_cw32 (mvi,CMD_PHY_MODE_21 , tmp); - - tmp =mvs_cr32 (mvi,CMD_PHY_TIMER ); - tmp &=0x1fffffff ; - tmp |= (2U <<29 );/* 8 ms retry */ -mvs_cw32 (mvi,CMD_PHY_TIMER , tmp); }static inline void mvs_int_sata (struct mvs_info *mvi)
Signature · 1 line
1.6.2.2