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e1000e: MDIO slow mode should always be done for 82577

PATCH Applied Jeff Kirsher 2 participants 4 messages Jan 13, 2010 – Jan 14, 2010

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#0 lore raw

PATCH 1/2 e1000e: MDIO slow mode should always be done for 82577

From: Bruce Allan <[email protected]>

A previous 82577 workaround that set the MDIO access speed to slow mode for every PHY register read/write when the cable is unplugged should instead set the access mode to always be slow before any PHY register access. Since the mode bit gets cleared when the PHY is reset, set the mode after every PHY reset.

---

 drivers/net/e1000e/e1000.h   |    1 
 drivers/net/e1000e/ich8lan.c |   57 ++++++++++++++++++++++++++--
 drivers/net/e1000e/phy.c     |   85 ------------------------------------------
 3 files changed, 53 insertions(+), 90 deletions(-)
drivers/net/e1000e/e1000.h +0 -1
index cebbd90..d6ee28f 100644
@@ -582,7 +582,6 @@ extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
 extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
 extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
                                          u16 data);
-extern s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow);
 extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
 extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
 extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
drivers/net/e1000e/ich8lan.c +53 -4

111 lines not on this page · raw message

drivers/net/e1000e/phy.c +0 -85

136 lines not on this page · raw message

#1 lore raw

PATCH 2/2 e1000e: workaround link issues on busy hub in half duplex on 82577/82578

From: Bruce Allan <[email protected]>

This patch removes a delay in hardware after every received packet allowing more time for transmitted packets to go out in between received packets in half duplex.

---

 drivers/net/e1000e/ich8lan.c |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletions(-)
drivers/net/e1000e/ich8lan.c +18 -1
index c2ea861..8b6ecd1 100644
@@ -1122,6 +1122,7 @@ static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 {
 	s32 ret_val = 0;
+	u16 phy_data;
 
 	if (hw->mac.type != e1000_pchlan)
 		return ret_val;
@@ -1165,16 +1166,32 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 
 	hw->phy.addr = 1;
 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
+	hw->phy.ops.release(hw);
 	if (ret_val)
 		goto out;
-	hw->phy.ops.release(hw);
 
 	/*
 	 * Configure the K1 Si workaround during phy reset assuming there is
 	 * link so that it disables K1 if link is in 1Gbps.
 	 */
 	ret_val = e1000_k1_gig_workaround_hv(hw, true);
+	if (ret_val)
+		goto out;
 
+	/* Workaround for link disconnects on a busy hub in half duplex */
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val)
+		goto out;
+	ret_val = hw->phy.ops.read_reg_locked(hw,
+	                                      PHY_REG(BM_PORT_CTRL_PAGE, 17),
+	                                      &phy_data);
+	if (ret_val)
+		goto release;
+	ret_val = hw->phy.ops.write_reg_locked(hw,
+	                                       PHY_REG(BM_PORT_CTRL_PAGE, 17),
+	                                       phy_data & 0x00FF);
+release:
+	hw->phy.ops.release(hw);
 out:
 	return ret_val;
 }
maintainer Applied
#2 lore raw

Re: [net-2.6 PATCH 2/2] e1000e: workaround link issues on busy hub in half duplex on 82577/82578

From: Jeff Kirsher <[email protected]>
Date: Wed, 13 Jan 2010 03:53:08 -0800

Quoted 8 lines

From: Bruce Allan <[email protected]>

This patch removes a delay in hardware after every received packet allowing more time for transmitted packets to go out in between received packets in half duplex.

Applied.

maintainer Applied
#3 lore raw
In reply to Jeff Kirsher

From: Jeff Kirsher <[email protected]>
Date: Wed, 13 Jan 2010 03:52:49 -0800

Quoted 10 lines

From: Bruce Allan <[email protected]>

A previous 82577 workaround that set the MDIO access speed to slow mode for every PHY register read/write when the cable is unplugged should instead set the access mode to always be slow before any PHY register access. Since the mode bit gets cleared when the PHY is reset, set the mode after every PHY reset.

Applied.