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tcg-x86_64: Special-case all 32-bit AND operands.

PATCH In review Richard Henderson 2 participants 4 messages Jan 6, 2010 – Jan 14, 2010

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#0 lore raw

PATCH 1/2 tcg-x86_64: Special-case all 32-bit AND operands.

This avoids an unnecessary REX.W prefix when dealing with AND operands that fit into a 32-bit quantity. The most common change actually seen is movz[wb]q -> movz[wb]l.

Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes.

---
 tcg/x86_64/tcg-target.c |   26 ++++++++------------------
 1 files changed, 8 insertions(+), 18 deletions(-)
tcg/x86_64/tcg-target.c +8 -18
index 2339091..f584c94 100644
@@ -426,24 +426,18 @@ static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
     } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
         /* dec */
         tcg_out_modrm(s, 0xff | P_REXW, 1, r0);
-    } else if (val == (int8_t)val) {
-        tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
-        tcg_out8(s, val);
-    } else if (c == ARITH_AND && val == 0xffu) {
-        /* movzbl */
-        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
-    } else if (c == ARITH_AND && val == 0xffffu) {
-        /* movzwl */
-        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
     } else if (c == ARITH_AND && val == 0xffffffffu) {
         /* 32-bit mov zero extends */
         tcg_out_modrm(s, 0x8b, r0, r0);
+    } else if (c == ARITH_AND && (uint64_t)val <= 0xffffffffu) {
+        /* AND with no high bits set can use a 32-bit operation.  */
+        tgen_arithi32(s, c, r0, val);
+    } else if (val == (int8_t)val) {
+        tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
+        tcg_out8(s, val);
     } else if (val == (int32_t)val) {
         tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
         tcg_out32(s, val);
-    } else if (c == ARITH_AND && val == (uint32_t)val) {
-        tcg_out_modrm(s, 0x81, c, r0);
-        tcg_out32(s, val);
     } else {
         tcg_abort();
     }
@@ -1182,16 +1176,12 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
         break;
     case INDEX_op_ext8u_i32:
+    case INDEX_op_ext8u_i64:
         tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, args[0], args[1]);
         break;
     case INDEX_op_ext16u_i32:
-        tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);
-        break;
-    case INDEX_op_ext8u_i64:
-        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, args[0], args[1]);
-        break;
     case INDEX_op_ext16u_i64:
-        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, args[0], args[1]);
+        tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);
         break;
     case INDEX_op_ext32u_i64:
         tcg_out_modrm(s, 0x8b, args[0], args[1]);
Signature · 1 line
1.6.5.2
#1 lore raw
Quoted 24 lines · Richard Henderson

This avoids an unnecessary REX.W prefix when dealing with AND operands that fit into a 32-bit quantity. The most common change actually seen is movz[wb]q -> movz[wb]l.

Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes.

---
 tcg/x86_64/tcg-target.c |   26 ++++++++------------------
 1 files changed, 8 insertions(+), 18 deletions(-)
tcg/x86_64/tcg-target.c +0 -5
index 2339091..f584c94 100644
@@ -426,24 +426,18 @@ static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
     } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
         /* dec */
         tcg_out_modrm(s, 0xff | P_REXW, 1, r0);
-    } else if (val == (int8_t)val) {
-        tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
-        tcg_out8(s, val);
-    } else if (c == ARITH_AND && val == 0xffu) {
-        /* movzbl */

tcg/x86_64/tcg-target.c static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) · line 434

Quoted 10 lines
tcg/x86_64/tcg-target.c +3 -4
-        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
-    } else if (c == ARITH_AND && val == 0xffffu) {
-        /* movzwl */
-        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
     } else if (c == ARITH_AND && val == 0xffffffffu) {
         /* 32-bit mov zero extends */
         tcg_out_modrm(s, 0x8b, r0, r0);
+    } else if (c == ARITH_AND && (uint64_t)val <= 0xffffffffu) {
+        /* AND with no high bits set can use a 32-bit operation.  */
+        tgen_arithi32(s, c, r0, val);

Do we really want to call tgen_arithi32() here, that will redo part of the above tests again? It might be better to simply remove the REX.W prefix above instead.

Quoted 21 lines
tcg/x86_64/tcg-target.c +4 -4
+    } else if (val == (int8_t)val) {
+        tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
+        tcg_out8(s, val);
     } else if (val == (int32_t)val) {
         tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
         tcg_out32(s, val);
-    } else if (c == ARITH_AND && val == (uint32_t)val) {
-        tcg_out_modrm(s, 0x81, c, r0);
-        tcg_out32(s, val);
     } else {
         tcg_abort();
     }
@@ -1182,16 +1176,12 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
         break;
     case INDEX_op_ext8u_i32:
+    case INDEX_op_ext8u_i64:
         tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, args[0], args[1]);
         break;
     case INDEX_op_ext16u_i32:
-        tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);

tcg/x86_64/tcg-target.c static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, · line 1187

Quoted 10 lines
tcg/x86_64/tcg-target.c +1 -5
-        break;
-    case INDEX_op_ext8u_i64:
-        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, args[0], args[1]);
-        break;
     case INDEX_op_ext16u_i64:
-        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, args[0], args[1]);
+        tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);
         break;
     case INDEX_op_ext32u_i64:
         tcg_out_modrm(s, 0x8b, args[0], args[1]);

This part looks fine.

Signature · 2 lines
Aurelien Jarno                          GPG: 1024D/F1BCDB73
[email protected]                 http://www.aurel32.net
#2 lore raw
Quoted 31 lines · Aurelien Jarno
Quoted 30 lines · Richard Henderson

This avoids an unnecessary REX.W prefix when dealing with AND operands that fit into a 32-bit quantity. The most common change actually seen is movz[wb]q -> movz[wb]l.

Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes.

---
  tcg/x86_64/tcg-target.c |   26 ++++++++------------------
  1 files changed, 8 insertions(+), 18 deletions(-)
tcg/x86_64/tcg-target.c +0 -9
index 2339091..f584c94 100644
@@ -426,24 +426,18 @@ static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
      } else if ((c == ARITH_ADD&&  val == -1) || (c == ARITH_SUB&&  val == 1)) {
          /* dec */
          tcg_out_modrm(s, 0xff | P_REXW, 1, r0);
-    } else if (val == (int8_t)val) {
-        tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
-        tcg_out8(s, val);
-    } else if (c == ARITH_AND&&  val == 0xffu) {
-        /* movzbl */
-        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
-    } else if (c == ARITH_AND&&  val == 0xffffu) {
-        /* movzwl */
-        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
      } else if (c == ARITH_AND&&  val == 0xffffffffu) {
          /* 32-bit mov zero extends */
Quoted 8 lines

tcg/x86_64/tcg-target.c static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) · line 434

Quoted 4 lines
tcg/x86_64/tcg-target.c +3 -0
          tcg_out_modrm(s, 0x8b, r0, r0);
+    } else if (c == ARITH_AND&&  (uint64_t)val<= 0xffffffffu) {
+        /* AND with no high bits set can use a 32-bit operation.  */
+        tgen_arithi32(s, c, r0, val);

Do we really want to call tgen_arithi32() here, that will redo part of the above tests again? It might be better to simply remove the REX.W prefix above instead.

Pardon? Do you mean the inc/dec tests? Otherwise I don't see what "above tests again" you're talking about.

I am looking to handle more than 0xff, 0xffff with the new test in gen_arithi64 -- 0x1234 is an appropriate mask to shorten to 32-bit AND as well. I have no idea if that answers your question.

r~

#3 lore raw
Quoted 41 lines · Richard Henderson
Quoted 31 lines · Aurelien Jarno
Quoted 30 lines · Richard Henderson

This avoids an unnecessary REX.W prefix when dealing with AND operands that fit into a 32-bit quantity. The most common change actually seen is movz[wb]q -> movz[wb]l.

Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes.

---
 tcg/x86_64/tcg-target.c |   26 ++++++++------------------
 1 files changed, 8 insertions(+), 18 deletions(-)
tcg/x86_64/tcg-target.c +0 -9
index 2339091..f584c94 100644
@@ -426,24 +426,18 @@ static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
     } else if ((c == ARITH_ADD&&  val == -1) || (c == ARITH_SUB&&  val == 1)) {
         /* dec */
         tcg_out_modrm(s, 0xff | P_REXW, 1, r0);
-    } else if (val == (int8_t)val) {
-        tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
-        tcg_out8(s, val);
-    } else if (c == ARITH_AND&&  val == 0xffu) {
-        /* movzbl */
-        tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
-    } else if (c == ARITH_AND&&  val == 0xffffu) {
-        /* movzwl */
-        tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
     } else if (c == ARITH_AND&&  val == 0xffffffffu) {
         /* 32-bit mov zero extends */
Quoted 8 lines

tcg/x86_64/tcg-target.c static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) · line 434

Quoted 4 lines
tcg/x86_64/tcg-target.c +3 -0
         tcg_out_modrm(s, 0x8b, r0, r0);
+    } else if (c == ARITH_AND&&  (uint64_t)val<= 0xffffffffu) {
+        /* AND with no high bits set can use a 32-bit operation.  */
+        tgen_arithi32(s, c, r0, val);

Do we really want to call tgen_arithi32() here, that will redo part of the above tests again? It might be better to simply remove the REX.W prefix above instead.

Quoted 7 lines

Pardon? Do you mean the inc/dec tests? Otherwise I don't see what "above tests again" you're talking about.

I am looking to handle more than 0xff, 0xffff with the new test in gen_arithi64 -- 0x1234 is an appropriate mask to shorten to 32-bit AND as well. I have no idea if that answers your question.

Yes it does, I missed that fact. Viewing your patch on this side gives it more sense. I have applied it.

Signature · 2 lines
Aurelien Jarno                          GPG: 1024D/F1BCDB73
[email protected]                 http://www.aurel32.net