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ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig

PATCH New Kukjin Kim 2 participants 2 messages Jan 28, 2010 Arm (32-bit)

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Kukjin Kim

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PATCH 1/2 ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig

This patch adds ARM_L1_CACHE_SHIFT_6 into arch/arm/Kconfig. Basically, ARM L1 cache line size is 32Bytes. Therefore, whenever new ARCH which has 64Bytes L1 cache line size is added, have to set ARM_L1_CACHE_SHIFT to 6. That is, have to add/modify arch/arm/mm/Kconfig.
This patch is for handle it in each ARCH such as ARCH_S5PC1XX, and ARCH_S5PV210 which is in review.

Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/Kconfig    |    5 +++++
 arch/arm/mm/Kconfig |    2 +-
 2 files changed, 6 insertions(+), 1 deletions(-)
arch/arm/Kconfig +5 -0
index a5602ec..c7e98ed 100644
@@ -161,6 +161,11 @@ config ARCH_MTD_XIP
 config GENERIC_HARDIRQS_NO__DO_IRQ
 	def_bool y
 
+config ARM_L1_CACHE_SHIFT_6
+	bool
+	help
+	  Setting ARM L1 cache line size to 64 Bytes.
+
 if OPROFILE
 
 config OPROFILE_ARMV6
arch/arm/mm/Kconfig +1 -1
index 91617f7..ad0b8d3 100644
@@ -779,5 +779,5 @@ config CACHE_XSC3L2
 
 config ARM_L1_CACHE_SHIFT
 	int
-	default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
+	default 6 if ARCH_OMAP3 || ARM_L1_CACHE_SHIFT_6
 	default 5
Signature · 1 line
1.6.2.5
#1 lore raw

PATCH 1/2 ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig

Quoted 34 lines · Kukjin Kim

This patch adds ARM_L1_CACHE_SHIFT_6 into arch/arm/Kconfig. Basically, ARM L1 cache line size is 32Bytes. Therefore, whenever new ARCH which has 64Bytes L1 cache line size is added, have to set ARM_L1_CACHE_SHIFT to 6. That is, have to add/modify arch/arm/mm/Kconfig.
This patch is for handle it in each ARCH such as ARCH_S5PC1XX, and ARCH_S5PV210 which is in review.

Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/Kconfig    |    5 +++++
 arch/arm/mm/Kconfig |    2 +-
 2 files changed, 6 insertions(+), 1 deletions(-)
arch/arm/Kconfig +5 -0
index a5602ec..c7e98ed 100644
@@ -161,6 +161,11 @@ config ARCH_MTD_XIP
 config GENERIC_HARDIRQS_NO__DO_IRQ
 	def_bool y
 
+config ARM_L1_CACHE_SHIFT_6
+	bool
+	help
+	  Setting ARM L1 cache line size to 64 Bytes.
+
 if OPROFILE
 
 config OPROFILE_ARMV6
arch/arm/mm/Kconfig +0 -0
index 91617f7..ad0b8d3 100644

arch/arm/mm/Kconfig config CACHE_XSC3L2 · line 783

Quoted 6 lines
arch/arm/mm/Kconfig +1 -1
@@ -779,5 +779,5 @@ config CACHE_XSC3L2
 
 config ARM_L1_CACHE_SHIFT
 	int
-	default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
+	default 6 if ARCH_OMAP3 || ARM_L1_CACHE_SHIFT_6
 	default 5

A couple of comments:

1) Change ARCH_OMAP3 to use this
2) Could ARM_L1_CACHE_SHIFT_6 go before this, or is there an ordering issue?

Quoted 3 lines
Signature · 1 line
1.6.2.5
Signature · 5 lines
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