ARM: Initial SuperH Mobile ARM support

ARM: Initial SuperH Mobile ARM support

[PATCH 01/06] ARM: SuperH Mobile ARM, sh7367 and G3EVM support [PATCH 02/06] ARM: Add sh7377 and G4EVM support [PATCH 03/06] ARM: Add sh7372 and AP4EVB support [PATCH 04/06] sh: Build drivers/sh for SuperH Mobile ARM [PATCH 05/06] sh: Let INTC set IRQF_VALID on ARM platforms [PATCH 06/06] sh-sci: Preliminary SuperH Mobile ARM support

Here comes a set of SuperH Mobile ARM patches. Nothing ground breaking really, just the bare minimum to get a kernel up and running with serial and timer on G3EVM, G4EVM and AP4EVB.

Features:
- Console: Serial console using drivers/serial/sh-sci.c
- Timer: Early platform driver using drivers/clocksource/sh_cmt.c
- Interrupts: Minimal INTC support using drivers/sh/intc.c
- Clocks: Dummy static implementation to enable above drivers
- Defconfigs: Omitted for now to simplify review

On top of this there will be a bunch of feature patches for the interrupt controller, gpio, clock framework, runtime pm and of course driver support.

I intend to throw this into a git repository at some point, but I may have to rework these patches a bit first depending on feedback.

Please let me know if there is anything you want me to rework and perhaps if you have some shared ARM code that you want me to spend time on. Thanks!

---

 arch/arm/Kconfig                                  |    7 
 arch/arm/Makefile                                 |    1 
 arch/arm/mach-shmobile/Kconfig                    |   81 ++++++
 arch/arm/mach-shmobile/Makefile                   |   16 +
 arch/arm/mach-shmobile/Makefile.boot              |    9 
 arch/arm/mach-shmobile/board-ap4evb.c             |  127 ++++++++++
 arch/arm/mach-shmobile/board-g3evm.c              |  127 ++++++++++
 arch/arm/mach-shmobile/board-g4evm.c              |  127 ++++++++++
 arch/arm/mach-shmobile/clock-sh7367.c             |   89 +++++++
 arch/arm/mach-shmobile/include/mach/clkdev.h      |    7 
 arch/arm/mach-shmobile/include/mach/common.h      |   19 +
 arch/arm/mach-shmobile/include/mach/dma.h         |    1 
 arch/arm/mach-shmobile/include/mach/entry-macro.S |   39 +++
 arch/arm/mach-shmobile/include/mach/gpio.h        |    1 
 arch/arm/mach-shmobile/include/mach/hardware.h    |    7 
 arch/arm/mach-shmobile/include/mach/io.h          |    9 
 arch/arm/mach-shmobile/include/mach/irqs.h        |   10 
 arch/arm/mach-shmobile/include/mach/memory.h      |    7 
 arch/arm/mach-shmobile/include/mach/system.h      |   14 +
 arch/arm/mach-shmobile/include/mach/timex.h       |    6 
 arch/arm/mach-shmobile/include/mach/uncompress.h  |   21 +
 arch/arm/mach-shmobile/include/mach/vmalloc.h     |    6 
 arch/arm/mach-shmobile/setup-sh7367.c             |  241 +++++++++++++++++++
 arch/arm/mach-shmobile/setup-sh7372.c             |  241 +++++++++++++++++++
 arch/arm/mach-shmobile/setup-sh7377.c             |  260 +++++++++++++++++++++
 arch/arm/mach-shmobile/timer.c                    |   46 +++
 arch/arm/tools/mach-types                         |    1 
 drivers/Makefile                                  |    1 
 drivers/serial/Kconfig                            |    2 
 drivers/serial/sh-sci.h                           |   23 +
 drivers/sh/intc.c                                 |    5 
 31 files changed, 1545 insertions(+), 6 deletions(-)

From: Magnus Damm <[email protected]>

This patch contains the SuperH Mobile ARM base support together with sh7367 CPU and G3EVM board support. Only timer, serial console and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this.

---

Applies on top of linux-next 20100119

 arch/arm/Kconfig                                  |    7 
 arch/arm/Makefile                                 |    1 
 arch/arm/mach-shmobile/Kconfig                    |   53 ++++
 arch/arm/mach-shmobile/Makefile                   |   12 +
 arch/arm/mach-shmobile/Makefile.boot              |    9 
 arch/arm/mach-shmobile/board-g3evm.c              |  127 +++++++++++
 arch/arm/mach-shmobile/clock-sh7367.c             |   89 +++++++
 arch/arm/mach-shmobile/include/mach/clkdev.h      |    7 
 arch/arm/mach-shmobile/include/mach/common.h      |   11 
 arch/arm/mach-shmobile/include/mach/dma.h         |    1 
 arch/arm/mach-shmobile/include/mach/entry-macro.S |   39 +++
 arch/arm/mach-shmobile/include/mach/gpio.h        |    1 
 arch/arm/mach-shmobile/include/mach/hardware.h    |    7 
 arch/arm/mach-shmobile/include/mach/io.h          |    9 
 arch/arm/mach-shmobile/include/mach/irqs.h        |   10 
 arch/arm/mach-shmobile/include/mach/memory.h      |    7 
 arch/arm/mach-shmobile/include/mach/system.h      |   14 +
 arch/arm/mach-shmobile/include/mach/timex.h       |    6 
 arch/arm/mach-shmobile/include/mach/uncompress.h  |   21 +
 arch/arm/mach-shmobile/include/mach/vmalloc.h     |    6 
 arch/arm/mach-shmobile/setup-sh7367.c             |  241 +++++++++++++++++++++
 arch/arm/mach-shmobile/timer.c                    |   46 ++++
 22 files changed, 724 insertions(+)

@@ -740,6 +740,11 @@ config ARCH_U8500
 	help
 	  Support for ST-Ericsson's Ux500 architecture
 
+config ARCH_SHMOBILE
+	bool "Renesas SH-Mobile"
+	help
+	  Support for Renesas's SH-Mobile ARM platforms
+
 endchoice
 
 source "arch/arm/mach-aaec2000/Kconfig"

@@ -851,6 +856,8 @@ source "arch/arm/mach-versatile/Kconfig"
 
 source "arch/arm/mach-w90x900/Kconfig"
 
+source "arch/arm/mach-shmobile/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
 	bool

@@ -166,6 +166,7 @@ machine-$(CONFIG_ARCH_S5P6440)		:= s5p64
 machine-$(CONFIG_ARCH_S5PC1XX)		:= s5pc100
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
+machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
 machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
 machine-$(CONFIG_ARCH_STMP37XX)		:= stmp37xx
 machine-$(CONFIG_ARCH_U300)		:= u300

@@ -0,0 +1,12 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common objects
+obj-y				:= timer.o
+
+# CPU objects
+obj-$(CONFIG_ARCH_SH7367)	+= setup-sh7367.o clock-sh7367.o
+
+# Board objects
+obj-$(CONFIG_MACH_G3EVM)	+= board-g3evm.o

@@ -0,0 +1,9 @@
+__ZRELADDR	:= $(shell /bin/bash -c 'printf "0x%08x" \
+		     $$[$(CONFIG_MEMORY_START) + 0x8000]')
+
+   zreladdr-y   := $(__ZRELADDR)
+
+# Unsupported legacy stuff
+#
+#params_phys-y (Instead: Pass atags pointer in r2)
+#initrd_phys-y (Instead: Use compiled-in initramfs)

@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+int __clk_get(struct clk *clk);
+void __clk_put(struct clk *clk);
+
+#endif /* __ASM_MACH_CLKDEV_H */

@@ -0,0 +1,11 @@
+#ifndef __ARCH_MACH_COMMON_H
+#define __ARCH_MACH_COMMON_H
+
+extern struct sys_timer shmobile_timer;
+
+extern void sh7367_init_irq(void);
+extern void sh7367_add_early_devices(void);
+extern void sh7367_add_standard_devices(void);
+extern void sh7367_clock_init(void);
+
+#endif /* __ARCH_MACH_COMMON_H */

@@ -0,0 +1 @@
+/* empty */

@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+	.macro  disable_fiq
+	.endm
+
+	.macro  get_irqnr_preamble, base, tmp
+	.endm
+
+	.macro  arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+	ldr     \base, =INTFLGA
+	ldr     \irqnr, [\base]
+	cmp	\irqnr, #0
+	beq	1000f
+	/* intevt to irq number */
+	lsr	\irqnr, \irqnr, #0x5
+	subs	\irqnr, \irqnr, #16
+
+1000:
+	.endm

@@ -0,0 +1 @@
+/* empty */

@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_HARDWARE_H
+#define __ASM_MACH_HARDWARE_H
+
+/* INTFLGA register - used by low level interrupt code in entry-macro.S */
+#define INTFLGA			0xe6980018
+
+#endif /* __ASM_MACH_HARDWARE_H */

@@ -0,0 +1,9 @@
+#ifndef __ASM_MACH_IO_H
+#define __ASM_MACH_IO_H
+
+#define IO_SPACE_LIMIT		0xffffffff
+
+#define __io(a)			((void __iomem *)(a))
+#define __mem_pci(a)		(a)
+
+#endif /* __ASM_MACH_IO_H */

@@ -0,0 +1,10 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#define NR_IRQS         512
+#define NR_IRQS_LEGACY  8
+
+#define evt2irq(evt)		(((evt) >> 5) - 16)
+#define irq2evt(irq)		(((irq) + 16) << 5)
+
+#endif /* __ASM_MACH_IRQS_H */

@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_MEMORY_H
+#define __ASM_MACH_MEMORY_H
+
+#define PHYS_OFFSET	UL(CONFIG_MEMORY_START)
+#define MEM_SIZE	UL(CONFIG_MEMORY_SIZE)
+
+#endif /* __ASM_MACH_MEMORY_H */

@@ -0,0 +1,14 @@
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+	cpu_reset(0);
+}
+
+#endif

@@ -0,0 +1,6 @@
+#ifndef __ASM_MACH_TIMEX_H
+#define __ASM_MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE		1193180 /* unused i8253 PIT value */
+
+#endif /* __ASM_MACH_TIMEX_H */

@@ -0,0 +1,21 @@
+#ifndef __ASM_MACH_UNCOMPRESS_H
+#define __ASM_MACH_UNCOMPRESS_H
+
+/*
+ * This does not append a newline
+ */
+static void putc(int c)
+{
+}
+
+static inline void flush(void)
+{
+}
+
+static void arch_decomp_setup(void)
+{
+}
+
+#define arch_decomp_wdog()
+
+#endif /* __ASM_MACH_UNCOMPRESS_H */

@@ -0,0 +1,6 @@
+#ifndef __ASM_MACH_VMALLOC_H
+#define __ASM_MACH_VMALLOC_H
+
+#define VMALLOC_END       (PAGE_OFFSET + 0x24000000)
+
+#endif /* __ASM_MACH_VMALLOC_H */

Ok, will make sure it gets sorted properly.

At this early stage there is not so much to do. When I get around to implement the clock framework and runtime pm for SuperH Mobile ARM then I'll have a close look at clkdev.

I'll update and resend these patches next week.

Thanks!

/ magnus

Hi!

...

I guess I'm confused. I thought superh was architecture, like arm is.....?

I superh actually manufacturer? And can we get shorter name than mach-shmobile? mach-shm?
Pavel

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

SH-Mobile (G series, in this case) is a line of SH/ARM multi-cores. They contain both SH and ARM MPUs and are built up almost entirely on SH IP blocks. There are some SH-Mobiles that are SH-only, and those are taken care of in arch/sh/ as normal. Most of the shared code sits in drivers/sh and so forth, requiring fairly little glue on the ARM architecture side. As support for these CPUs is extended, we'll likely see more of arch/sh/ being generalized. There's likely not going to be enough that is directly reusable between the two to warrant a split out architecture directory of its own, but we'll see how it goes.

It's forseeable that we will also see support for the same CPU in arch/sh/ aimed at the SH MPU, and that we can have linux running on both the SH and the ARM at the same time sharing the same peripheral domain. However, all of these things are out of scope for this patch set, which is just getting the groundwork established for the ARM MPU.

shmobile is what the line is called, and matches the naming scheme we already have in-tree today. Changing that around would only lead to more confusion. It's also not really any longer than many of the other mach types, so I don't really see the point.

2010/2/1 Paul Mundt <[email protected]>:

Jaysis, that's one odd bird. There must be some upside to designing things like this, is there some paper or conference presentation on the idea behind this thing somewhere out there? I just get very curious!

Linus Walleij

Most of it comes down to customer requirements, where the application stack is primarily running on a single MPU and the other is primarily used as a co-processor. In the Japanese cellular market (what this series was designed for) many people have a lot of existing ITRON code tied to one architecture or the other that they don't wish to part with, are unable to port, etc. a lot of that ends up being multimedia bits, but people have done other things with it, too. We've also done SH/M32R multi-cores in the past for similar reasons, although those had a limited production run.

The multiple kernels on multiple CPUs thing is pretty standard for the Japanese market at least, we face similar issues on SH SMP where we have a need for lightweight CPU and memory hotplug/unplug in order to offline different CPUs temporarily for one-shot ITRON/uITRON applications (which gets to be tricky if that CPUs memory is an active NUMA node that we've already spread allocations to), this is something quite common in automotive at least.

The real problem with ITRON is that many of the existing applications do fairly questionable things with register accesses, which can cause troubles for things like dynamic clock gating and the like. On the other hand, it only runs in a single address space, so simply paravirtualizing the parts we care about should be lightweight enough. Outside of the Japanese market, ITRON and its variants are much more of an unknown, so providing Linux for both cores is becoming gradually more important. The previous generations all contained an integrated cellular baseband which largely restricted it to the domestic market, although this has been changing over the last couple of years with multi-band FOMA becoming more commonplace. In any event, things like AP4 are more intended for general use and decouple the baseband completely.

The domestic market will likely gradually transition over to Linux on both cores, but it will take some time, and even then we'll likely never be rid of ITRON completely (and especially not uITRON). These CPUs have been in the majority of Japanese cell phones for almost a decade, with a lot of the underlying code changing very little. The ARM MPU itself is a new addition on the side that was only added a couple of years ago, but we still have to wait and see if people are able to make effective use of both.

As far as public information, there's very little in either english or japanese. I couldn't really point you at anything specific that you couldn't find with google. In any event, now that these sorts of things are no longer restricted to the Japanese domestic market we'll hopefully be able to employ a greater degree of transparency.

From: Magnus Damm <[email protected]>

This patch adds base support for the SuperH Mobile ARM processor sh7377 together with G4EVM board support. Only timer, serial console and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this.

---

Applies on top of linux-next 20100119 and the sh7367 patch.

 arch/arm/mach-shmobile/Kconfig               |   14 +
 arch/arm/mach-shmobile/Makefile              |    2 
 arch/arm/mach-shmobile/board-g4evm.c         |  127 ++++++++++++
 arch/arm/mach-shmobile/include/mach/common.h |    4 
 arch/arm/mach-shmobile/setup-sh7377.c        |  260 ++++++++++++++++++++++++++
 5 files changed, 407 insertions(+)

@@ -10,12 +10,24 @@ config ARCH_SH7367
 	select GENERIC_TIME
 	select GENERIC_CLOCKEVENTS
 
+config ARCH_SH7377
+	bool "SH-Mobile SH7377 (G4)"
+	select CPU_V7
+	select HAVE_CLK
+	select COMMON_CLKDEV
+	select GENERIC_TIME
+	select GENERIC_CLOCKEVENTS
+
 comment "SH-Mobile Board Type"
 
 config MACH_G3EVM
 	bool "G3EVM board"
 	depends on ARCH_SH7367
 
+config MACH_G4EVM
+	bool "G4EVM board"
+	depends on ARCH_SH7377
+
 comment "SH-Mobile System Configuration"
 
 menu "Memory configuration"

@@ -23,6 +35,7 @@ menu "Memory configuration"
 config MEMORY_START
 	hex "Physical memory start address"
 	default "0x50000000" if MACH_G3EVM
+	default "0x40000000" if MACH_G4EVM
 	default "0x00000000"
 	---help---
 	  Tweak this only when porting to a new machine which does not

@@ -32,6 +45,7 @@ config MEMORY_START
 config MEMORY_SIZE
 	hex "Physical memory size"
 	default "0x08000000" if MACH_G3EVM
+	default "0x08000000" if MACH_G4EVM
 	default "0x04000000"
 	help
 	  This sets the default memory size assumed by your kernel. It can

@@ -7,6 +7,8 @@ obj-y				:= timer.o
 
 # CPU objects
 obj-$(CONFIG_ARCH_SH7367)	+= setup-sh7367.o clock-sh7367.o
+obj-$(CONFIG_ARCH_SH7377)	+= setup-sh7377.o clock-sh7367.o
 
 # Board objects
 obj-$(CONFIG_MACH_G3EVM)	+= board-g3evm.o
+obj-$(CONFIG_MACH_G4EVM)	+= board-g4evm.o

@@ -8,4 +8,8 @@ extern void sh7367_add_early_devices(voi
 extern void sh7367_add_standard_devices(void);
 extern void sh7367_clock_init(void);
 
+extern void sh7377_init_irq(void);
+extern void sh7377_add_early_devices(void);
+extern void sh7377_add_standard_devices(void);
+
 #endif /* __ARCH_MACH_COMMON_H */

From: Magnus Damm <[email protected]>

This patch adds base support for the SuperH Mobile ARM processor sh7372 together with AP4EVB board support. Only timer, serial console and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this.

The mach-type entry has been submitted but is included here for now.

---

Applies on top of linux-next 20100119 and the sh7367+sh7377 patches.

 arch/arm/mach-shmobile/Kconfig               |   14 +
 arch/arm/mach-shmobile/Makefile              |    2 
 arch/arm/mach-shmobile/board-ap4evb.c        |  127 +++++++++++++
 arch/arm/mach-shmobile/include/mach/common.h |    4 
 arch/arm/mach-shmobile/setup-sh7372.c        |  241 ++++++++++++++++++++++++++
 arch/arm/tools/mach-types                    |    1 
 6 files changed, 389 insertions(+)

@@ -18,6 +18,14 @@ config ARCH_SH7377
 	select GENERIC_TIME
 	select GENERIC_CLOCKEVENTS
 
+config ARCH_SH7372
+	bool "SH-Mobile SH7372 (AP4)"
+	select CPU_V7
+	select HAVE_CLK
+	select COMMON_CLKDEV
+	select GENERIC_TIME
+	select GENERIC_CLOCKEVENTS
+
 comment "SH-Mobile Board Type"
 
 config MACH_G3EVM

@@ -28,6 +36,10 @@ config MACH_G4EVM
 	bool "G4EVM board"
 	depends on ARCH_SH7377
 
+config MACH_AP4EVB
+	bool "AP4EVB board"
+	depends on ARCH_SH7372
+
 comment "SH-Mobile System Configuration"
 
 menu "Memory configuration"

@@ -36,6 +48,7 @@ config MEMORY_START
 	hex "Physical memory start address"
 	default "0x50000000" if MACH_G3EVM
 	default "0x40000000" if MACH_G4EVM
+	default "0x40000000" if MACH_AP4EVB
 	default "0x00000000"
 	---help---
 	  Tweak this only when porting to a new machine which does not

@@ -46,6 +59,7 @@ config MEMORY_SIZE
 	hex "Physical memory size"
 	default "0x08000000" if MACH_G3EVM
 	default "0x08000000" if MACH_G4EVM
+	default "0x10000000" if MACH_AP4EVB
 	default "0x04000000"
 	help
 	  This sets the default memory size assumed by your kernel. It can

@@ -8,7 +8,9 @@ obj-y				:= timer.o
 # CPU objects
 obj-$(CONFIG_ARCH_SH7367)	+= setup-sh7367.o clock-sh7367.o
 obj-$(CONFIG_ARCH_SH7377)	+= setup-sh7377.o clock-sh7367.o
+obj-$(CONFIG_ARCH_SH7372)	+= setup-sh7372.o clock-sh7367.o
 
 # Board objects
 obj-$(CONFIG_MACH_G3EVM)	+= board-g3evm.o
 obj-$(CONFIG_MACH_G4EVM)	+= board-g4evm.o
+obj-$(CONFIG_MACH_AP4EVB)	+= board-ap4evb.o

@@ -12,4 +12,8 @@ extern void sh7377_init_irq(void);
 extern void sh7377_add_early_devices(void);
 extern void sh7377_add_standard_devices(void);
 
+extern void sh7372_init_irq(void);
+extern void sh7372_add_early_devices(void);
+extern void sh7372_add_standard_devices(void);
+
 #endif /* __ARCH_MACH_COMMON_H */

@@ -2578,3 +2578,4 @@ glacier			MACH_GLACIER		GLACIER			2592
 phrazer_bulldog		MACH_PHRAZER_BULLDOG	PHRAZER_BULLDOG		2593
 omap3_bulldog		MACH_OMAP3_BULLDOG	OMAP3_BULLDOG		2594
 pca101			MACH_PCA101		PCA101			2595
+ap4evb			MACH_AP4EVB		AP4EVB			2630

From: Magnus Damm <[email protected]>

Build drivers/sh in the case for SuperH Mobile ARM. Shared code for the interrupt controller (INTC) and the gpio/pinmux (PFC) is located there.

---

 drivers/Makefile |    1 +
 1 file changed, 1 insertion(+)

@@ -99,6 +99,7 @@ obj-$(CONFIG_SGI_SN)		+= sn/
 obj-y				+= firmware/
 obj-$(CONFIG_CRYPTO)		+= crypto/
 obj-$(CONFIG_SUPERH)		+= sh/
+obj-$(CONFIG_ARCH_SHMOBILE)	+= sh/
 obj-$(CONFIG_GENERIC_TIME)	+= clocksource/
 obj-$(CONFIG_DMA_ENGINE)	+= dma/
 obj-$(CONFIG_DCA)		+= dca/

From: Magnus Damm <[email protected]>

Reuse the SuperH INTC code on ARM by using set_irq_flags() to set IRQF_VALID on ARM platforms. Reworking the shared ARM interrupt code and removing IRQF_VALID is another option.

---

 drivers/sh/intc.c |    5 +++++
 1 file changed, 5 insertions(+)

@@ -658,6 +658,11 @@ static void __init intc_register_irq(str
 
 	if (desc->ack_regs)
 		ack_handle[irq] = intc_ack_data(desc, d, enum_id);
+
+	/* Set IRQF_VALID to enable IRQ on ARM systems */
+#ifdef CONFIG_ARCH_SHMOBILE
+	set_irq_flags(irq, IRQF_VALID);
+#endif
 }
 
 static unsigned int __init save_reg(struct intc_desc_int *d,

From: Magnus Damm <[email protected]>

Add preliminary SuperH Mobile ARM support to the sh-sci driver. Enough to get serial console working. Needs more work. Is really disconnected from the ARM support code but is included here for completeness.

---

 drivers/serial/Kconfig  |    2 +-
 drivers/serial/sh-sci.h |   23 ++++++++++++++++++-----
 2 files changed, 19 insertions(+), 6 deletions(-)

@@ -996,7 +996,7 @@ config SERIAL_IP22_ZILOG_CONSOLE
 
 config SERIAL_SH_SCI
 	tristate "SuperH SCI(F) serial port support"
-	depends on HAVE_CLK && (SUPERH || H8300)
+	depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE)
 	select SERIAL_CORE
 
 config SERIAL_SH_SCI_NR_UARTS

@@ -174,6 +174,10 @@
 # define SCSPTR3 0xffc60020		/* 16 bit SCIF */
 # define SCIF_ORER 0x0001		/* Overrun error bit */
 # define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_ARCH_SHMOBILE)
+# define SCSCR_INIT(port)	0x0030
+# define SCIF_ONLY
+# define SCIF_ORER		0x0200
 #else
 # error CPU subtype not defined
 #endif

@@ -261,7 +265,8 @@
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721)
+    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_ARCH_SHMOBILE)
 # define SCxSR_RDxF_CLEAR(port)	 (sci_in(port, SCxSR) & 0xfffc)
 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
 # define SCxSR_TDxE_CLEAR(port)	 (sci_in(port, SCxSR) & 0xffdf)

@@ -356,7 +361,7 @@
     SCI_OUT(sci_size, sci_offset, value);				\
   }
 
-#ifdef CONFIG_CPU_SH3
+#if defined(CONFIG_CPU_SH3) || defined(CONFIG_ARCH_SHMOBILE)
 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 		                sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \

@@ -366,7 +371,8 @@
 	  CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7721)
+      defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+      defined(CONFIG_ARCH_SHMOBILE)
 #define SCIF_FNS(name, scif_offset, scif_size) \
   CPU_SCIF_FNS(name, scif_offset, scif_size)
 #else

@@ -401,7 +407,8 @@
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721)
+    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_ARCH_SHMOBILE)
 
 SCIF_FNS(SCSMR,  0x00, 16)
 SCIF_FNS(SCBRR,  0x04,  8)

@@ -548,6 +555,11 @@ static inline int sci_rxd_in(struct uart
 		return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 	return 1;
 }
+#elif defined(CONFIG_ARCH_SHMOBILE)
+static inline int sci_rxd_in(struct uart_port *port)
+{
+	return 1;
+}
 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \

@@ -801,7 +813,8 @@ static inline int sci_rxd_in(struct uart
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7721)
+      defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+      defined(CONFIG_ARCH_SHMOBILE)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
       defined(CONFIG_CPU_SUBTYPE_SH7724)

SCIF_ONLY should be killed off, nothing is checking for it these days. I thought they were all gone already, but it looks like SH7757 snuck one back in, too..