sh: clock-cpg div4 set_rate() shift fix

PATCH In review Magnus Damm 2 participants 2 messages Feb 19, 2010 – Feb 22, 2010 SuperH

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Magnus Damm

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2010-02-19 09:12 UTC #0 lore raw

PATCH 1/1 sh: clock-cpg div4 set_rate() shift fix

From: Magnus Damm <[email protected]>

Make sure the div4 bitfield is shifted according to the enable_bit value in sh_clk_div4_set_rate().

Signed-off-by Magnus Damm <[email protected]>

---

 arch/sh/kernel/cpu/clock-cpg.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/sh/kernel/cpu/clock-cpg.c +2 -2

@@ -192,8 +192,8 @@ static int sh_clk_div4_set_rate(struct c
 		return idx;
 
 	value = __raw_readl(clk->enable_reg);
-	value &= ~0xf;
-	value |= idx;
+	value &= ~(0xf << clk->enable_bit);
+	value |= (idx << clk->enable_bit);
 	__raw_writel(value, clk->enable_reg);
 
 	return 0;

Paul Mundt

2010-02-22 10:15 UTC #1 lore raw

Quoted 2 lines · Magnus Damm

Make sure the div4 bitfield is shifted according to the enable_bit value in sh_clk_div4_set_rate().

Quoted 4 lines · Magnus Damm

This patch introduces struct clk_div4_table. The structure will be used to keep div4 specific data, and is with this patch replacing the struct clk_div_mult_table pointer arg used by the sh_clk_div4_register() functions.

Quoted 5 lines · Magnus Damm

This patch adds a ->kick() callback to clk_div4_table and ties it into sh_clk_div4_set_rate(). A sh7724 specific kick function is also added that updates the KICK bit whenever div4 clocks in FRQCRA and FRQCRB have been set. Allows us to set the VPU clock.

Quoted 7 lines · Magnus Damm

Update the sh7724 processor code to always enable vpu_clk.
On the Ecovec board, set the vpu_clk to 166 Mhz.
The 166MHz setting results in a divide-by-6 setup for vpu_clk and improves the VPU performance compared to the power-on-reset/bootloader configuration.

All applied, thanks.