Allow SOC to be two-levels deep inside CPU
Subsystems (3)
PATCH 1/2 Allow SOC to be two-levels deep inside CPU
On ARM, it has been suggested to place Cortex-A8 SoC directories in arch/arm/cpu/cortex/a8 and Cortex-A9 SoC directories in arch/arm/cpu/cortex/a9, with common code kept in arch/arm/cpu/cortex.
To allow this, if the mkconfig argument for the CPU includes a slash, make mkconfig split the variable, at the slash, into a $CPU and a $SUBCPU.
SOC directories will be expected to be present in $SOCDIR, which will either be $CPUDIR/$SOC or $CPUDIR/$SUBCPU/$SOC, depending on whether a SUBCPU is used.
The top-level Makefile will continue to look for the CPU-specific config.mk and Makefile inside $CPUDIR. CPU-specific Makefiles can choose to include code from inside $SUBCPU as necessary.
Acked-by Michael Brandt <[email protected]>
Signed-off-by Rabin Vincent <[email protected]>
--- Makefile | 2 +- board/freescale/mx51evk/config.mk | 2 +- config.mk | 7 ++++++- doc/README.ARM-SoC | 8 +++++--- mkconfig | 3 ++- 5 files changed, 15 insertions(+), 7 deletions(-)
Makefile +1 -1
@@ -190,7 +190,7 @@ LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \ "board/$(VENDOR)/common/lib$(VENDOR).a"; fi) LIBS += $(CPUDIR)/lib$(CPU).a ifdef SOC -LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).a +LIBS += $(SOCDIR)/lib$(SOC).a endif ifeq ($(CPU),ixp) LIBS += arch/arm/cpu/ixp/npe/libnpe.a
board/freescale/mx51evk/config.mk +1 -1
@@ -20,6 +20,6 @@ # MA 02111-1307 USA # -LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds +LDSCRIPT = $(SOCDIR)/u-boot.lds TEXT_BASE = 0x97800000 IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
config.mk +6 -1
@@ -119,11 +119,16 @@ ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR))) CPUDIR=arch/$(ARCH)/cpu endif +SOCDIR = $(CPUDIR)/$(SOC) +ifdef SUBCPU +SOCDIR = $(CPUDIR)/$(SUBCPU)/$(SOC) +endif + sinclude $(TOPDIR)/arch/$(ARCH)/config.mk # include architecture dependend rules sinclude $(TOPDIR)/$(CPUDIR)/config.mk # include CPU specific rules ifdef SOC -sinclude $(TOPDIR)/$(CPUDIR)/$(SOC)/config.mk # include SoC specific rules +sinclude $(TOPDIR)/$(SOCDIR)/config.mk # include SoC specific rules endif ifdef VENDOR BOARDDIR = $(VENDOR)/$(BOARD)
doc/README.ARM-SoC +5 -3
@@ -10,12 +10,14 @@ resides in $(CPUDIR)/ and code that is specific to some SoC (i.e. vendor specific -peripherals around the core) is moved into +peripherals around the core) is moved into $(SOCDIR), which is +one of $(CPUDIR)/$(SOC)/ + $(CPUDIR)/$(SUBCPU)/$(SOC)/ -Thus a library/archive "$(CPUDIR)/$(SOC)/lib$(SOC).a" will be build -and linked. Examples will be +Thus a library/archive "$(SOCDIR)/lib$(SOC).a" will be build and linked. +Examples will be arch/arm/cpu/arm920t/imx/ arch/arm/cpu/arm920t/s3c24x0
mkconfig +2 -1
@@ -70,7 +70,8 @@ fi # Create include file for Make # echo "ARCH = $2" > config.mk -echo "CPU = $3" >> config.mk +echo "CPU =" `echo $3 | cut -f1 -d/` >> config.mk +echo "SUBCPU =" `echo $3 | cut -f2 -s -d/` >> config.mk echo "BOARD = $4" >> config.mk [ "$5" ] && [ "$5" != "NULL" ] && echo "VENDOR = $5" >> config.mk
Signature · 1 line
1.7.0
PATCH 2/2 ARM: reorganize Cortex directory
Rename arch/arm/cpu/arm_cortexa8 to arch/arm/cpu/cortex, and move Cortex-A8 SOC directories into arch/arm/cpu/cortex/a8. This will allow a logical separation between the A8 and A9 variants while at the same time allowing them to share code.
Since currently all code can be shared between A8 and A9, we don't put any source files in the top-level a8 directory. When such code is needed, we can put the a8-specific code and Makefiles in arch/arm/cpu/cortex/a8 and use $SUBCPU to reference it from the arch/arm/cpu/cortex Makefiles.
Acked-by Michael Brandt <[email protected]>
Signed-off-by Rabin Vincent <[email protected]>
---
Makefile | 20 ++++++++++----------
arch/arm/cpu/{arm_cortexa8 => cortex}/Makefile | 0
.../cpu/{arm_cortexa8 => cortex/a8}/mx51/Makefile | 0
.../cpu/{arm_cortexa8 => cortex/a8}/mx51/clock.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/mx51/iomux.c | 0
.../a8}/mx51/lowlevel_init.S | 0
.../arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/soc.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/mx51/speed.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/mx51/timer.c | 0
.../{arm_cortexa8 => cortex/a8}/mx51/u-boot.lds | 2 +-
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/Makefile | 0
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/board.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/cache.S | 0
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/clock.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/gpio.c | 0
.../a8}/omap3/lowlevel_init.S | 0
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/mem.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/reset.S | 0
.../{arm_cortexa8 => cortex/a8}/omap3/sys_info.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/syslib.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/omap3/timer.c | 0
.../{arm_cortexa8 => cortex/a8}/s5pc1xx/Makefile | 0
.../{arm_cortexa8 => cortex/a8}/s5pc1xx/cache.S | 2 +-
.../{arm_cortexa8 => cortex/a8}/s5pc1xx/clock.c | 0
.../{arm_cortexa8 => cortex/a8}/s5pc1xx/cpu_info.c | 0
.../cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/gpio.c | 0
.../{arm_cortexa8 => cortex/a8}/s5pc1xx/reset.S | 0
.../{arm_cortexa8 => cortex/a8}/s5pc1xx/sromc.c | 0
.../{arm_cortexa8 => cortex/a8}/s5pc1xx/timer.c | 0
arch/arm/cpu/{arm_cortexa8 => cortex}/config.mk | 0
arch/arm/cpu/{arm_cortexa8 => cortex}/cpu.c | 0
arch/arm/cpu/{arm_cortexa8 => cortex}/start.S | 0
arch/arm/cpu/{arm_cortexa8 => cortex}/u-boot.lds | 2 +-
arch/arm/include/asm/arch-mx51/asm-offsets.h | 2 +-
board/logicpd/zoom2/zoom2.c | 2 +-
35 files changed, 15 insertions(+), 15 deletions(-)
rename arch/arm/cpu/{arm_cortexa8 => cortex}/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/iomux.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/lowlevel_init.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/soc.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/speed.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/mx51/u-boot.lds (97%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/board.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/cache.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/gpio.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/lowlevel_init.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/mem.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/reset.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/sys_info.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/syslib.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/omap3/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/cache.S (98%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/cpu_info.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/gpio.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/reset.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/sromc.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex/a8}/s5pc1xx/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex}/config.mk (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex}/cpu.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex}/start.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => cortex}/u-boot.lds (97%)Makefile +10 -10
@@ -3150,31 +3150,31 @@ SMN42_config : unconfig ######################################################################### devkit8000_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 devkit8000 timll omap3 omap3_beagle_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle ti omap3 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 beagle ti omap3 omap3_overo_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 overo NULL omap3 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 overo NULL omap3 omap3_evm_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm ti omap3 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 evm ti omap3 omap3_pandora_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 pandora NULL omap3 omap3_sdp3430_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 sdp3430 ti omap3 omap3_zoom1_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 logicpd omap3 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 zoom1 logicpd omap3 omap3_zoom2_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 zoom2 logicpd omap3 smdkc100_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx + @$(MKCONFIG) $(@:_config=) arm cortex/a8 smdkc100 samsung s5pc1xx ######################################################################### ## XScale Systems
@@ -3293,7 +3293,7 @@ mx31pdk_nand_config : unconfig @$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31 mx51evk_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51 + @$(MKCONFIG) $(@:_config=) arm cortex/a8 mx51evk freescale mx51 omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
arch/arm/cpu/cortex/Makefile renamed from arch/arm/cpu/arm_cortexa8/Makefile +0 -0
arch/arm/cpu/cortex/a8/mx51/Makefile renamed from arch/arm/cpu/arm_cortexa8/mx51/Makefile +0 -0
arch/arm/cpu/cortex/a8/mx51/clock.c renamed from arch/arm/cpu/arm_cortexa8/mx51/clock.c +0 -0
arch/arm/cpu/cortex/a8/mx51/iomux.c renamed from arch/arm/cpu/arm_cortexa8/mx51/iomux.c +0 -0
arch/arm/cpu/cortex/a8/mx51/lowlevel_init.S renamed from arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S +0 -0
arch/arm/cpu/cortex/a8/mx51/soc.c renamed from arch/arm/cpu/arm_cortexa8/mx51/soc.c +0 -0
arch/arm/cpu/cortex/a8/mx51/speed.c renamed from arch/arm/cpu/arm_cortexa8/mx51/speed.c +0 -0
arch/arm/cpu/cortex/a8/mx51/timer.c renamed from arch/arm/cpu/arm_cortexa8/mx51/timer.c +0 -0
arch/arm/cpu/cortex/a8/mx51/u-boot.lds renamed from arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds +1 -1
@@ -36,7 +36,7 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/arm_cortexa8/start.o + arch/arm/cpu/cortex/start.o *(.text) }
arch/arm/cpu/cortex/a8/omap3/Makefile renamed from arch/arm/cpu/arm_cortexa8/omap3/Makefile +0 -0
arch/arm/cpu/cortex/a8/omap3/board.c renamed from arch/arm/cpu/arm_cortexa8/omap3/board.c +0 -0
arch/arm/cpu/cortex/a8/omap3/cache.S renamed from arch/arm/cpu/arm_cortexa8/omap3/cache.S +0 -0
arch/arm/cpu/cortex/a8/omap3/clock.c renamed from arch/arm/cpu/arm_cortexa8/omap3/clock.c +0 -0
arch/arm/cpu/cortex/a8/omap3/gpio.c renamed from arch/arm/cpu/arm_cortexa8/omap3/gpio.c +0 -0
arch/arm/cpu/cortex/a8/omap3/lowlevel_init.S renamed from arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S +0 -0
arch/arm/cpu/cortex/a8/omap3/mem.c renamed from arch/arm/cpu/arm_cortexa8/omap3/mem.c +0 -0
arch/arm/cpu/cortex/a8/omap3/reset.S renamed from arch/arm/cpu/arm_cortexa8/omap3/reset.S +0 -0
arch/arm/cpu/cortex/a8/omap3/sys_info.c renamed from arch/arm/cpu/arm_cortexa8/omap3/sys_info.c +0 -0
arch/arm/cpu/cortex/a8/omap3/syslib.c renamed from arch/arm/cpu/arm_cortexa8/omap3/syslib.c +0 -0
arch/arm/cpu/cortex/a8/omap3/timer.c renamed from arch/arm/cpu/arm_cortexa8/omap3/timer.c +0 -0
arch/arm/cpu/cortex/a8/s5pc1xx/Makefile renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile +0 -0
arch/arm/cpu/cortex/a8/s5pc1xx/cache.S renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S +1 -1
@@ -2,7 +2,7 @@ * Copyright (C) 2009 Samsung Electronics * Minkyu Kang <[email protected]> * - * based on arch/arm/cpu/arm_cortexa8/omap3/cache.S + * based on arch/arm/cpu/cortex/a8/omap3/cache.S * * See file CREDITS for list of people who contributed to this * project.
arch/arm/cpu/cortex/a8/s5pc1xx/clock.c renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c +0 -0
arch/arm/cpu/cortex/a8/s5pc1xx/cpu_info.c renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c +0 -0
arch/arm/cpu/cortex/a8/s5pc1xx/gpio.c renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/gpio.c +0 -0
arch/arm/cpu/cortex/a8/s5pc1xx/reset.S renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S +0 -0
arch/arm/cpu/cortex/a8/s5pc1xx/sromc.c renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c +0 -0
arch/arm/cpu/cortex/a8/s5pc1xx/timer.c renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c +0 -0
arch/arm/cpu/cortex/config.mk renamed from arch/arm/cpu/arm_cortexa8/config.mk +0 -0
arch/arm/cpu/cortex/cpu.c renamed from arch/arm/cpu/arm_cortexa8/cpu.c +0 -0
arch/arm/cpu/cortex/start.S renamed from arch/arm/cpu/arm_cortexa8/start.S +0 -0
arch/arm/cpu/cortex/u-boot.lds renamed from arch/arm/cpu/arm_cortexa8/u-boot.lds +1 -1
@@ -34,7 +34,7 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/arm_cortexa8/start.o (.text) + arch/arm/cpu/cortex/start.o (.text) *(.text) }
arch/arm/include/asm/arch-mx51/asm-offsets.h +1 -1
@@ -1,5 +1,5 @@/* -* needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S +* needed for arch/arm/cpu/cortex/a8/mx51/lowlevel_init.S * * These should be auto-generated */
board/logicpd/zoom2/zoom2.c +1 -1
@@ -46,7 +46,7 @@/* * This the the zoom2, board specific, gpmc configuration for the * quad uart on the debug board. The more general gpmc configurations -* are setup at the cpu level in arch/arm/cpu/arm_cortexa8/omap3/mem.c +* are setup at the cpu level in arch/arm/cpu/cortex/a8/omap3/mem.c * * The details of the setting of the serial gpmc setup are not available. * The values were provided by another party.
Signature · 1 line
1.7.0
PATCH 1/2 Allow SOC to be two-levels deep inside CPU
In reply to Rabin VincentDear Rabin Vincent,
config.mk ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR))) · line 125
Quoted 11 lines · In message <[email protected]>…
config.mk +4
-0@@ -119,11 +119,16 @@ ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR))) CPUDIR=arch/$(ARCH)/cpu endif +SOCDIR = $(CPUDIR)/$(SOC) +ifdef SUBCPU +SOCDIR = $(CPUDIR)/$(SUBCPU)/$(SOC) +endif
Using an ifdef' / else' / `endif' would seem more logical to me.
Best regards,
Wolfgang Denk
Signature · 6 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Tactical? TACTICAL!?!? Hey, buddy, we went from kilotons to megatons several minutes ago. We don't need no stinkin' tactical nukes. (By the way, do you have change for 10 million people?) - lwall
PATCH 1/2 Allow SOC to be two-levels deep inside CPU
Quoted 7 lines · Wolfgang Denk
config.mk ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR))) · line 125
Quoted 4 lines · In message <[email protected]>…
config.mk +4
-0+SOCDIR = $(CPUDIR)/$(SOC) +ifdef SUBCPU +SOCDIR = $(CPUDIR)/$(SUBCPU)/$(SOC) +endifUsing an
ifdef' /else' / `endif' would seem more logical to me.
Updated patch below.
Rabin