Add i.MX51 3-stack board support

PATCH Superseded Jason Wang 5 participants 28 messages Jun 3, 2010 – Jun 10, 2010

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape

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Jason Wang

author

2010-06-03 12:05 UTC #0 lore raw

v2 cover Add i.MX51 3-stack board support

Comparing with V1, several changes are made in V2:

1) drop iomux-mx51-3ds.h and move its contents to iomux-mx51.h
2) move keypad device definition to devices.c
3) fix all remaining comments from Sascha, Amit and Fabio.

[V2 1/3] mxc: Add support for the imx51 3-stack board [V2 2/3] mxc/iomux: add GPIO bank offset for iomux v3 platforms [V2 3/3] mx51/keypad: add keypad support for i.MX51 platforms

Jason Wang

author

2010-06-03 12:05 UTC #1 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

3-stack is a reference board from Freescale for their i.MX51 SoC.

Add board definition, Kconfig and Makefile to enable Freescale 3-stack board.

Boot tested on a i.MX51 3-stack Rev2.0 board

Signed-off-by Jason Wang <[email protected]>

---
 arch/arm/mach-mx5/Kconfig                       |    5 +
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
 arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
 5 files changed, 345 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h

arch/arm/mach-mx5/Kconfig +5 -0

index 1576d51..6d45f44 100644
@@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
 	  u-boot. This includes specific configurations for the board and its
 	  peripherals.
 
+config MACH_MX51_3DS
+	bool "Support MX51PDK (3DS)"
+	help
+	  Include support for MX51PDK (3DS) platform. This includes specific
+	  configurations for the board and its peripherals.
 endif

arch/arm/mach-mx5/Makefile +1 -1

index bf23f86..c757c59 100644
@@ -6,4 +6,4 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o

arch/arm/mach-mx5/board-mx51_3ds.c new file +263 -0

263 lines not on this page · raw message

arch/arm/plat-mxc/include/mach/board-mx51_3ds.h new file +70 -0

70 lines not on this page · raw message

arch/arm/plat-mxc/include/mach/iomux-mx51.h +6 -4

index ab0f95d..895c750 100644
@@ -70,8 +70,10 @@ typedef enum iomux_config {
 /* Babbage UART3 */
 #define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
 
 #define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)

@@ -202,8 +204,8 @@ typedef enum iomux_config {
 #define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
 
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)

@@ -306,7 +308,7 @@ typedef enum iomux_config {
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
 						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))

Signature · 1 line

1.5.6.5

Jason Wang

author

2010-06-03 12:05 UTC #2 lore raw

PATCH v2 2/3 mxc/iomux: add GPIO bank offset for iomux v3 platforms

From: Wang Hui <[email protected]>

These GPIO bank offsets are useful when define a gpio number. E.G. when GPIO PORTC pin 6 is used for irq request pin of external expanding device, we can define it like:
#define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6)

Signed-off-by Jason Wang <[email protected]>

---
 arch/arm/plat-mxc/include/mach/iomux-v3.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

arch/arm/plat-mxc/include/mach/iomux-v3.h +15 -0

index f2f73d3..0880a4a 100644
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST		(1 << 0)
 #define PAD_CTL_SRE_SLOW		(0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT	4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA	(0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB	(1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC	(2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD	(3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE	(4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF	(5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */

Signature · 1 line

1.5.6.5

Jason Wang

author

2010-06-03 12:05 UTC #3 lore raw

PATCH v2 3/3 mx51/keypad: add keypad support for i.MX51 platforms

Add keypad controller device definition for all i.MX51 platforms, add a dummy kpp clock for imx keypad driver and add keypad device registration on i.MX51 3-stack board.

Signed-off-by Jason Wang <[email protected]>

---
 arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx5/clock-mx51.c     |    5 +++
 arch/arm/mach-mx5/devices.c        |   19 +++++++++++
 arch/arm/mach-mx5/devices.h        |    1 +
 4 files changed, 84 insertions(+), 0 deletions(-)

arch/arm/mach-mx5/board-mx51_3ds.c +59 -0

index 5da90e9..abc9f87 100644
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>

@@ -54,8 +55,65 @@ static struct pad_desc mx51_3ds_pads[] = {
 
 	/* CPLD PARENT IRQ PIN */
 	MX51_PAD_GPIO_1_6__GPIO1_6,
+
+	/* KPP */
+	MX51_PAD_KEY_ROW0__KEY_ROW0,
+	MX51_PAD_KEY_ROW1__KEY_ROW1,
+	MX51_PAD_KEY_ROW2__KEY_ROW2,
+	MX51_PAD_KEY_ROW3__KEY_ROW3,
+	MX51_PAD_KEY_COL0__KEY_COL0,
+	MX51_PAD_KEY_COL1__KEY_COL1,
+	MX51_PAD_KEY_COL2__KEY_COL2,
+	MX51_PAD_KEY_COL3__KEY_COL3,
+	MX51_PAD_KEY_COL4__KEY_COL4,
+	MX51_PAD_KEY_COL5__KEY_COL5,
+};
+
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+	KEY(0, 0, KEY_1),
+	KEY(0, 1, KEY_2),
+	KEY(0, 2, KEY_3),
+	KEY(0, 3, KEY_F1),
+	KEY(0, 4, KEY_UP),
+	KEY(0, 5, KEY_F2),
+
+	KEY(1, 0, KEY_4),
+	KEY(1, 1, KEY_5),
+	KEY(1, 2, KEY_6),
+	KEY(1, 3, KEY_LEFT),
+	KEY(1, 4, KEY_SELECT),
+	KEY(1, 5, KEY_RIGHT),
+
+	KEY(2, 0, KEY_7),
+	KEY(2, 1, KEY_8),
+	KEY(2, 2, KEY_9),
+	KEY(2, 3, KEY_F3),
+	KEY(2, 4, KEY_DOWN),
+	KEY(2, 5, KEY_F4),
+
+	KEY(3, 0, KEY_0),
+	KEY(3, 1, KEY_OK),
+	KEY(3, 2, KEY_ESC),
+	KEY(3, 3, KEY_ENTER),
+	KEY(3, 4, KEY_MENU),
+	KEY(3, 5, KEY_BACK)
 };
 
+static struct matrix_keymap_data mx51_3ds_map_data = {
+	.keymap		= mx51_3ds_board_keymap,
+	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static void mxc_init_keypad(void)
+{
+	mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 static struct resource smsc911x_resources[] = {

@@ -241,6 +299,7 @@ static void __init mxc_board_init(void)
 	mxc_init_imx_uart();
 	mxc_expio_init();
 	mxc_init_enet();
+	mxc_init_keypad();
 }
 
 static void __init mx51_3ds_timer_init(void)

arch/arm/mach-mx5/clock-mx51.c +5 -0

index d9f612d..60fced6 100644
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
 	.parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+	.id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
 	static struct clk name = {			\
 		.id		= i,			\

@@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
 };
 
 static void clk_tree_init(void)

arch/arm/mach-mx5/devices.c +19 -0

index 7130449..2aa4ea0 100644
@@ -168,6 +168,25 @@ struct platform_device mxc_wdt = {
 	.resource = mxc_wdt_resources,
 };
 
+static struct resource mxc_kpp_resources[] = {
+	{
+		.start = MX51_MXC_INT_KPP,
+		.end = MX51_MXC_INT_KPP,
+		.flags = IORESOURCE_IRQ,
+	} , {
+		.start = MX51_KPP_BASE_ADDR,
+		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device mxc_keypad_device = {
+	.name = "imx-keypad",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(mxc_kpp_resources),
+	.resource = mxc_kpp_resources,
+};
+
 static struct mxc_gpio_port mxc_gpio_ports[] = {
 	{
 		.chip.label = "gpio-0",

arch/arm/mach-mx5/devices.h +1 -0

index c879ae7..1fef140 100644
@@ -6,3 +6,4 @@ extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_keypad_device;

Signature · 1 line

1.5.6.5

Alberto Panizzo

2010-06-05 09:35 UTC #4 lore raw

PATCH v2 3/3 mx51/keypad: add keypad support for i.MX51 platforms

Quoted 11 lines · Jason Wang

Add keypad controller device definition for all i.MX51 platforms, add a dummy kpp clock for imx keypad driver and add keypad device registration on i.MX51 3-stack board.
Signed-off-by Jason Wang <[email protected]>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx5/clock-mx51.c     |    5 +++
 arch/arm/mach-mx5/devices.c        |   19 +++++++++++
 arch/arm/mach-mx5/devices.h        |    1 +
 4 files changed, 84 insertions(+), 0 deletions(-)

May you wont divide platform vs machine code in two different patches.

and, Eric B?nard is working on imx_keypad suspend/resume features[1] and about it, he is going to modify the platform interface that make us able to register the device.. this patch could look old in a few.

[1]http://thread.gmane.org/gmane.linux.ports.arm.kernel/80968/focus=13131

Best regards,
Alberto!

Quoted 149 lines

arch/arm/mach-mx5/board-mx51_3ds.c +59 -0

index 5da90e9..abc9f87 100644
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>

@@ -54,8 +55,65 @@ static struct pad_desc mx51_3ds_pads[] = {
 
 	/* CPLD PARENT IRQ PIN */
 	MX51_PAD_GPIO_1_6__GPIO1_6,
+
+	/* KPP */
+	MX51_PAD_KEY_ROW0__KEY_ROW0,
+	MX51_PAD_KEY_ROW1__KEY_ROW1,
+	MX51_PAD_KEY_ROW2__KEY_ROW2,
+	MX51_PAD_KEY_ROW3__KEY_ROW3,
+	MX51_PAD_KEY_COL0__KEY_COL0,
+	MX51_PAD_KEY_COL1__KEY_COL1,
+	MX51_PAD_KEY_COL2__KEY_COL2,
+	MX51_PAD_KEY_COL3__KEY_COL3,
+	MX51_PAD_KEY_COL4__KEY_COL4,
+	MX51_PAD_KEY_COL5__KEY_COL5,
+};
+
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+	KEY(0, 0, KEY_1),
+	KEY(0, 1, KEY_2),
+	KEY(0, 2, KEY_3),
+	KEY(0, 3, KEY_F1),
+	KEY(0, 4, KEY_UP),
+	KEY(0, 5, KEY_F2),
+
+	KEY(1, 0, KEY_4),
+	KEY(1, 1, KEY_5),
+	KEY(1, 2, KEY_6),
+	KEY(1, 3, KEY_LEFT),
+	KEY(1, 4, KEY_SELECT),
+	KEY(1, 5, KEY_RIGHT),
+
+	KEY(2, 0, KEY_7),
+	KEY(2, 1, KEY_8),
+	KEY(2, 2, KEY_9),
+	KEY(2, 3, KEY_F3),
+	KEY(2, 4, KEY_DOWN),
+	KEY(2, 5, KEY_F4),
+
+	KEY(3, 0, KEY_0),
+	KEY(3, 1, KEY_OK),
+	KEY(3, 2, KEY_ESC),
+	KEY(3, 3, KEY_ENTER),
+	KEY(3, 4, KEY_MENU),
+	KEY(3, 5, KEY_BACK)
 };
 
+static struct matrix_keymap_data mx51_3ds_map_data = {
+	.keymap		= mx51_3ds_board_keymap,
+	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static void mxc_init_keypad(void)
+{
+	mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 static struct resource smsc911x_resources[] = {

@@ -241,6 +299,7 @@ static void __init mxc_board_init(void)
 	mxc_init_imx_uart();
 	mxc_expio_init();
 	mxc_init_enet();
+	mxc_init_keypad();
 }
 
 static void __init mx51_3ds_timer_init(void)

arch/arm/mach-mx5/clock-mx51.c +5 -0

index d9f612d..60fced6 100644
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
 	.parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+	.id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
 	static struct clk name = {			\
 		.id		= i,			\

@@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
 };
 
 static void clk_tree_init(void)

arch/arm/mach-mx5/devices.c +19 -0

index 7130449..2aa4ea0 100644
@@ -168,6 +168,25 @@ struct platform_device mxc_wdt = {
 	.resource = mxc_wdt_resources,
 };
 
+static struct resource mxc_kpp_resources[] = {
+	{
+		.start = MX51_MXC_INT_KPP,
+		.end = MX51_MXC_INT_KPP,
+		.flags = IORESOURCE_IRQ,
+	} , {
+		.start = MX51_KPP_BASE_ADDR,
+		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device mxc_keypad_device = {
+	.name = "imx-keypad",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(mxc_kpp_resources),
+	.resource = mxc_kpp_resources,
+};
+
 static struct mxc_gpio_port mxc_gpio_ports[] = {
 	{
 		.chip.label = "gpio-0",

arch/arm/mach-mx5/devices.h +1 -0

index c879ae7..1fef140 100644
@@ -6,3 +6,4 @@ extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_keypad_device;

jason

author

2010-06-05 14:13 UTC #5 lore raw

PATCH v2 3/3 mx51/keypad: add keypad support for i.MX51 platforms

Quoted 15 lines · Alberto Panizzo

Quoted 4 lines · Jason Wang
Add keypad controller device definition for all i.MX51 platforms, add a dummy kpp clock for imx keypad driver and add keypad device registration on i.MX51 3-stack board.
Quoted 8 lines
Signed-off-by Jason Wang <[email protected]>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx5/clock-mx51.c     |    5 +++
 arch/arm/mach-mx5/devices.c        |   19 +++++++++++
 arch/arm/mach-mx5/devices.h        |    1 +
 4 files changed, 84 insertions(+), 0 deletions(-)

Quoted 2 lines

May you wont divide platform vs machine code in two different patches.

Thanks for your comments, but here i don't really know what you mean, should i divide this patch to 2 patches or ?

Quoted 10 lines

and, Eric B?nard is working on imx_keypad suspend/resume features[1] and about it, he is going to modify the platform interface that make us able to register the device.. this patch could look old in a few.
[1]http://thread.gmane.org/gmane.linux.ports.arm.kernel/80968/focus=13131
Best regards,
Alberto!

Yes, reading this thread, my platform interface is old.
I just git pull the upstream, it seems that new interface change hasn't been merged,
i will modify this interface if it is merged into the upstream.

Thanks,
Jason.

Quoted 6 lines

Quoted 6 lines
arch/arm/mach-mx5/board-mx51_3ds.c +0 -0
index 5da90e9..abc9f87 100644
@@ -16,6 +16,7 @@
 

<snip>

Alberto Panizzo

2010-06-06 18:11 UTC #6 lore raw

PATCH v2 3/3 mx51/keypad: add keypad support for i.MX51 platforms

Hi Jason,

Quoted 16 lines · jason

Quoted 15 lines · Alberto Panizzo
Quoted 12 lines · Jason Wang
Add keypad controller device definition for all i.MX51 platforms, add a dummy kpp clock for imx keypad driver and add keypad device registration on i.MX51 3-stack board.
Signed-off-by Jason Wang <[email protected]>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx5/clock-mx51.c     |    5 +++
 arch/arm/mach-mx5/devices.c        |   19 +++++++++++
 arch/arm/mach-mx5/devices.h        |    1 +
 4 files changed, 84 insertions(+), 0 deletions(-)

Quoted 4 lines

Quoted 2 lines
May you wont divide platform vs machine code in two different patches.
Thanks for your comments, but here i don't really know what you mean, should i divide this patch to 2 patches or ?

Code that stays into devices.[c|h] is general code that shall not be modified together with machine code (board-mx51_3ds.c).

Quoted 6 lines

Quoted 6 lines
and, Eric B?nard is working on imx_keypad suspend/resume features[1] and about it, he is going to modify the platform interface that make us able to register the device.. this patch could look old in a few.
[1]http://thread.gmane.org/gmane.linux.ports.arm.kernel/80968/focus=13131

Quoted 8 lines

Quoted 4 lines
Best regards,
Alberto!
Yes, reading this thread, my platform interface is old.
I just git pull the upstream, it seems that new interface change hasn't been merged,
i will modify this interface if it is merged into the upstream.

Well Dmitry (linux input maintainer) asked Eric some clarifications before merging his work.
In all case, Eric work is going to be part of the next merge window through the linux input tree if all goes in the right way. So in the imx tree you would see it at least since .35

Sascha, what is your policy about this? Shall Jason support the keypad with the current interface and update it's support in the next merge window? or it is better to wait?

Alberto!

jason

author

2010-06-07 23:22 UTC #7 lore raw

PATCH v2 3/3 mx51/keypad: add keypad support for i.MX51 platforms

Quoted 25 lines · Alberto Panizzo

Hi Jason,
Quoted 21 lines · jason
Quoted 19 lines · Alberto Panizzo
Quoted 4 lines · Jason Wang
Add keypad controller device definition for all i.MX51 platforms, add a dummy kpp clock for imx keypad driver and add keypad device registration on i.MX51 3-stack board.
Quoted 9 lines
Signed-off-by Jason Wang <[email protected]>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx5/clock-mx51.c     |    5 +++
 arch/arm/mach-mx5/devices.c        |   19 +++++++++++
 arch/arm/mach-mx5/devices.h        |    1 +
 4 files changed, 84 insertions(+), 0 deletions(-)
May you wont divide platform vs machine code in two different patches.

Quoted 8 lines

Quoted 3 lines
Thanks for your comments, but here i don't really know what you mean, should i divide this patch to 2 patches or ?
Code that stays into devices.[c|h] is general code that shall not be modified together with machine code (board-mx51_3ds.c).

OK, accept.

Thanks,
Jason.

Quoted 32 lines

Quoted 11 lines
Quoted 11 lines
and, Eric B?nard is working on imx_keypad suspend/resume features[1] and about it, he is going to modify the platform interface that make us able to register the device.. this patch could look old in a few.
[1]http://thread.gmane.org/gmane.linux.ports.arm.kernel/80968/focus=13131
Best regards,
Alberto!
Quoted 5 lines
Yes, reading this thread, my platform interface is old.
I just git pull the upstream, it seems that new interface change hasn't been merged,
i will modify this interface if it is merged into the upstream.
Well Dmitry (linux input maintainer) asked Eric some clarifications before merging his work.
In all case, Eric work is going to be part of the next merge window through the linux input tree if all goes in the right way. So in the imx tree you would see it at least since .35
Sascha, what is your policy about this? Shall Jason support the keypad with the current interface and update it's support in the next merge window? or it is better to wait?
Alberto!

Amit Kucheria

2010-06-03 12:39 UTC #8 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

In reply to Jason Wang

Two comments inline.

Quoted 124 lines · Jason Wang

3-stack is a reference board from Freescale for their i.MX51 SoC.

Add board definition, Kconfig and Makefile to enable Freescale 3-stack board.

Boot tested on a i.MX51 3-stack Rev2.0 board

Signed-off-by Jason Wang <[email protected]>

---
 arch/arm/mach-mx5/Kconfig                       |    5 +
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
 arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
 5 files changed, 345 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h

arch/arm/mach-mx5/Kconfig +5 -0

index 1576d51..6d45f44 100644
@@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
 	  u-boot. This includes specific configurations for the board and its
 	  peripherals.
 
+config MACH_MX51_3DS
+	bool "Support MX51PDK (3DS)"
+	help
+	  Include support for MX51PDK (3DS) platform. This includes specific
+	  configurations for the board and its peripherals.
 endif

arch/arm/mach-mx5/Makefile +1 -1

index bf23f86..c757c59 100644
@@ -6,4 +6,4 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o

arch/arm/mach-mx5/board-mx51_3ds.c new file +76 -0

new file mode 100644
index 0000000..5da90e9
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/board-mx51_3ds.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static void __iomem *brd_io;
+
+static void expio_ack_irq(u32 irq);
+
+static struct pad_desc mx51_3ds_pads[] = {
+	/* UART1 */
+	MX51_PAD_UART1_RXD__UART1_RXD,
+	MX51_PAD_UART1_TXD__UART1_TXD,
+	MX51_PAD_UART1_RTS__UART1_RTS,
+	MX51_PAD_UART1_CTS__UART1_CTS,
+
+	/* UART2 */
+	MX51_PAD_UART2_RXD__UART2_RXD,
+	MX51_PAD_UART2_TXD__UART2_TXD,
+	MX51_PAD_EIM_D25__UART2_CTS,
+	MX51_PAD_EIM_D26__UART2_RTS,
+
+	/* UART3 */
+	MX51_PAD_GPIO_1_22__UART3_RXD,
+	MX51_PAD_GPIO_1_23__UART3_TXD,
+	MX51_PAD_EIM_D24__UART3_CTS,
+	MX51_PAD_EIM_D27__UART3_RTS,
+
+	/* CPLD PARENT IRQ PIN */
+	MX51_PAD_GPIO_1_6__GPIO1_6,
+};
+
+
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct resource smsc911x_resources[] = {
+	{
+		.start = LAN9217_BASE_ADDR,
+		.end = LAN9217_BASE_ADDR + 0x100 - 1,
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = EXPIO_INT_ENET,
+		.end = EXPIO_INT_ENET,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};

arch/arm/mach-mx5/board-mx51_3ds.c line 86

Quoted 10 lines

arch/arm/mach-mx5/board-mx51_3ds.c new file +10 -0

+
+static struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};

You forgot to move this platform_device to devices.c

Quoted 191 lines

arch/arm/mach-mx5/board-mx51_3ds.c new file +176 -0

+static void mxc_init_enet(void)
+{
+	if (brd_io != NULL)
+		platform_device_register(&smsc_lan9217_device);
+}
+#else
+static inline void mxc_init_enet(void)
+{
+}
+#endif
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr_val;
+	u32 int_valid;
+	u32 expio_irq;
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+	expio_irq = MXC_BOARD_IRQ_START;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq)))
+			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+		else
+			d->handle_irq(expio_irq, d);
+	}
+
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * @param irq		an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg |= (1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+/*
+ * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
+ * @param irq		an expanded io virtual irq number
+ */
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	expio_mask_irq(irq);
+}
+
+/*
+ * Enable a expio pin's interrupt by clearing the bit in the imr.
+ * @param irq		a expio virtual irq number
+ */
+static void expio_unmask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg &= ~(1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+static int __init mxc_expio_init(void)
+{
+	int i;
+
+	brd_io = ioremap(BOARD_IO_ADDR, SZ_4K);
+	if (brd_io == NULL)
+		return -ENOMEM;
+
+	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+		pr_info("3-Stack Debug board not detected\n");
+		iounmap(brd_io);
+		brd_io = NULL;
+		return -ENODEV;
+	}
+
+	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+		readw(brd_io + CPLD_CODE_VER_REG));
+
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_request(MX51_3DS_CPLD_IRQ_PIN, "gpio1_6");
+	gpio_direction_input(MX51_3DS_CPLD_IRQ_PIN);
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0, brd_io + INTR_MASK_REG);
+	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
+	for (i = MXC_EXP_IO_BASE;
+	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(EXPIO_PARENT_INT, IRQF_TRIGGER_LOW);
+	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
+
+	return 0;
+}
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	mxc_register_device(&mxc_uart_device2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+					ARRAY_SIZE(mx51_3ds_pads));
+	mxc_init_imx_uart();
+	mxc_expio_init();
+	mxc_init_enet();
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+	mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+	.init	= mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+	.phys_io = MX51_AIPS1_BASE_ADDR,
+	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.map_io = mx51_map_io,
+	.init_irq = mx51_init_irq,
+	.init_machine = mxc_board_init,
+	.timer = &mxc_timer,
+MACHINE_END

arch/arm/plat-mxc/include/mach/board-mx51_3ds.h new file +9 -0

new file mode 100644
index 0000000..035f7bc
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html

arch/arm/plat-mxc/include/mach/board-mx51_3ds.h line 19

Quoted 10 lines

arch/arm/plat-mxc/include/mach/board-mx51_3ds.h new file +10 -0

+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+
+/*
+ * @file plat-mxc/include/mach/board-mx51_3ds.h
+ *
+ * @brief This file contains all the board level configuration options.

Remove this @file, @brief.

Quoted 89 lines

arch/arm/plat-mxc/include/mach/board-mx51_3ds.h new file +50 -0

+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ */
+
+#define DEBUG_BOARD_BASE_ADDRESS MX51_CS5_BASE_ADDR
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR	(DEBUG_BOARD_BASE_ADDRESS + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x8000)
+#define UARTB_BASE_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x10000)
+
+#define BOARD_IO_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES	16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
+
+/* Define CPLD interrupt pin */
+#define MX51_3DS_CPLD_IRQ_PIN	(GPIO_PORTA + 6)
+
+#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */

arch/arm/plat-mxc/include/mach/iomux-mx51.h +6 -4

index ab0f95d..895c750 100644
@@ -70,8 +70,10 @@ typedef enum iomux_config {
 /* Babbage UART3 */
 #define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
 
 #define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)

@@ -202,8 +204,8 @@ typedef enum iomux_config {
 #define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
 
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)

@@ -306,7 +308,7 @@ typedef enum iomux_config {
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
 						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))

Signature · 1 line

1.5.6.5

Signature · 3 lines

----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------

Sascha Hauer

maintainer

2010-06-03 13:57 UTC #9 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

Quoted 131 lines · Amit Kucheria

Two comments inline.

Quoted 128 lines · Jason Wang

3-stack is a reference board from Freescale for their i.MX51 SoC.

Add board definition, Kconfig and Makefile to enable Freescale 3-stack board.

Boot tested on a i.MX51 3-stack Rev2.0 board

Signed-off-by Jason Wang <[email protected]>

---
 arch/arm/mach-mx5/Kconfig                       |    5 +
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
 arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
 5 files changed, 345 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h

arch/arm/mach-mx5/Kconfig +5 -0

index 1576d51..6d45f44 100644
@@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
 	  u-boot. This includes specific configurations for the board and its
 	  peripherals.
 
+config MACH_MX51_3DS
+	bool "Support MX51PDK (3DS)"
+	help
+	  Include support for MX51PDK (3DS) platform. This includes specific
+	  configurations for the board and its peripherals.
 endif

arch/arm/mach-mx5/Makefile +1 -1

index bf23f86..c757c59 100644
@@ -6,4 +6,4 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o

arch/arm/mach-mx5/board-mx51_3ds.c new file +80 -0

new file mode 100644
index 0000000..5da90e9
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/board-mx51_3ds.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static void __iomem *brd_io;
+
+static void expio_ack_irq(u32 irq);
+
+static struct pad_desc mx51_3ds_pads[] = {
+	/* UART1 */
+	MX51_PAD_UART1_RXD__UART1_RXD,
+	MX51_PAD_UART1_TXD__UART1_TXD,
+	MX51_PAD_UART1_RTS__UART1_RTS,
+	MX51_PAD_UART1_CTS__UART1_CTS,
+
+	/* UART2 */
+	MX51_PAD_UART2_RXD__UART2_RXD,
+	MX51_PAD_UART2_TXD__UART2_TXD,
+	MX51_PAD_EIM_D25__UART2_CTS,
+	MX51_PAD_EIM_D26__UART2_RTS,
+
+	/* UART3 */
+	MX51_PAD_GPIO_1_22__UART3_RXD,
+	MX51_PAD_GPIO_1_23__UART3_TXD,
+	MX51_PAD_EIM_D24__UART3_CTS,
+	MX51_PAD_EIM_D27__UART3_RTS,
+
+	/* CPLD PARENT IRQ PIN */
+	MX51_PAD_GPIO_1_6__GPIO1_6,
+};
+
+
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct resource smsc911x_resources[] = {
+	{
+		.start = LAN9217_BASE_ADDR,
+		.end = LAN9217_BASE_ADDR + 0x100 - 1,
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = EXPIO_INT_ENET,
+		.end = EXPIO_INT_ENET,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,

Quoted 8 lines

arch/arm/mach-mx5/board-mx51_3ds.c line 86
Quoted 6 lines
arch/arm/mach-mx5/board-mx51_3ds.c new file +6 -0
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
You forgot to move this platform_device to devices.c

No, devices.c is the place for the i.MX51 integrated peripherals, not for externally conntected peripherals.

Sascha

Signature · 4 lines

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Amit Kucheria

2010-06-03 14:35 UTC #10 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

Quoted 15 lines · Sascha Hauer

Quoted 13 lines · Amit Kucheria
Two comments inline.
arch/arm/mach-mx5/board-mx51_3ds.c line 86
Quoted 9 lines
arch/arm/mach-mx5/board-mx51_3ds.c new file +9 -0
+static struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
You forgot to move this platform_device to devices.c

Quoted 2 lines

No, devices.c is the place for the i.MX51 integrated peripherals, not for externally conntected peripherals.

OK. Didn't know this was an externally connected peripheral. Which, BTW, is also why I had suggested that the smsc and the debug board support were added as separate patches. But it is a preference thing.

Signature · 3 lines

----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------

jason

author

2010-06-03 14:36 UTC #11 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

In reply to Sascha Hauer

Quoted 74 lines · Sascha Hauer

Quoted 72 lines · Amit Kucheria

Two comments inline.

Quoted 68 lines · Jason Wang

3-stack is a reference board from Freescale for their i.MX51 SoC.

Add board definition, Kconfig and Makefile to enable Freescale 3-stack board.

Boot tested on a i.MX51 3-stack Rev2.0 board

Signed-off-by Jason Wang <[email protected]>

---
 arch/arm/mach-mx5/Kconfig                       |    5 +
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
 arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
 5 files changed, 345 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h

arch/arm/mach-mx5/Kconfig +5 -0

index 1576d51..6d45f44 100644
@@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
 	  u-boot. This includes specific configurations for the board and its
 	  peripherals.
 
+config MACH_MX51_3DS
+	bool "Support MX51PDK (3DS)"
+	help
+	  Include support for MX51PDK (3DS) platform. This includes specific
+	  configurations for the board and its peripherals.
 endif

arch/arm/mach-mx5/Makefile +1 -1

index bf23f86..c757c59 100644
@@ -6,4 +6,4 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o

arch/arm/mach-mx5/board-mx51_3ds.c new file +18 -0

new file mode 100644
index 0000000..5da90e9
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>

<snip>

Quoted 13 lines

Quoted 12 lines
arch/arm/mach-mx5/board-mx51_3ds.c line 86
Quoted 10 lines
arch/arm/mach-mx5/board-mx51_3ds.c new file +9 -0
+static struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
You forgot to move this platform_device to devices.c

Quoted 6 lines

No, devices.c is the place for the i.MX51 integrated peripherals, not for externally conntected peripherals.
Sascha

Yes, this device is board specific, not the one of i.MX51 SOC. I think it's better to keep it in the board specific file.

Thanks,
Jason.

jason

author

2010-06-03 14:39 UTC #12 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

In reply to Amit Kucheria

Quoted 24 lines · Amit Kucheria

Two comments inline.
Quoted 20 lines · Jason Wang
3-stack is a reference board from Freescale for their i.MX51 SoC.
Add board definition, Kconfig and Makefile to enable Freescale 3-stack board.
Boot tested on a i.MX51 3-stack Rev2.0 board
Signed-off-by Jason Wang <[email protected]>
---
 arch/arm/mach-mx5/Kconfig                       |    5 +
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
 arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
 5 files changed, 345 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h

<snip>

Quoted 20 lines

arch/arm/plat-mxc/include/mach/board-mx51_3ds.h new file +14 -0

new file mode 100644
index 0000000..035f7bc
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__

Quoted 10 lines

arch/arm/plat-mxc/include/mach/board-mx51_3ds.h line 19
Quoted 6 lines
arch/arm/plat-mxc/include/mach/board-mx51_3ds.h new file +5 -0
+
+/*
+ * @file plat-mxc/include/mach/board-mx51_3ds.h
+ *
+ * @brief This file contains all the board level configuration options.
Remove this @file, @brief.

OK, i will fix it in V3.

Thanks,
Jason.

Quoted 7 lines

Quoted 6 lines
arch/arm/plat-mxc/include/mach/board-mx51_3ds.h new file +5 -0
+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ */
+
+#define DEBUG_BOARD_BASE_ADDRESS MX51_CS5_BASE_ADDR

<snip>

Sascha Hauer

maintainer

2010-06-04 08:53 UTC #13 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

In reply to Jason Wang

arch/arm/mach-mx5/board-mx51_3ds.c line 100

Quoted 3 lines · Jason Wang

arch/arm/mach-mx5/board-mx51_3ds.c new file +3 -0
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{

I'm not willing to accept another 3ds_debug board support in the kernel given that it's no rocket science to seperate this into another file and we still have plenty of time before the next merge window. Jason, can you please move this to plat-mxc? I think we could find someone else to switch the mx31_3ds support to the generic debug board support then.

[snip]

Quoted 11 lines

#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)

arch/arm/plat-mxc/include/mach/iomux-mx51.h +3 -1

+#define MX51_PAD_EIM_D25__UART2_CTS	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
 
 #define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)

arch/arm/plat-mxc/include/mach/iomux-mx51.h typedef enum iomux_config { · line 208

Quoted 7 lines

arch/arm/plat-mxc/include/mach/iomux-mx51.h +2 -2

@@ -202,8 +204,8 @@ typedef enum iomux_config {
 #define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
 
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)

Urgs, there really is something wrong here.

First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22 as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be wrong with many (all?) defines in this file. Amit, you should have read the comment ontop of this file which you copied from the i.MX35 part:

/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/

This should be fixed before doing any other change to this file.

Then Jason, what you are looking for is the following:

#define MX51_PAD_UART3_RXD__UART3_RXD

because you want the UART3_RXD pad in its native mode.

Here is how the defines in this file should look like (modulo bugs):

#define MX51_PAD_EIM_D16__GPIO_2_0		(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D17__GPIO_2_1		(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D18__GPIO_2_2		(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D19__GPIO_2_3		(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D20__GPIO_2_4		(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D21__GPIO_2_5		(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D22__GPIO_2_6		(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D23__GPIO_2_7		(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)

#define MX51_PAD_EIM_D24__UART3_CTS (0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D25__UART3_RXD (0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D26__UART3_TXD (0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D27__UART3_RTS (0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)

#define MX51_PAD_EIM_D28__EIM_D28		(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D29__EIM_D29		(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D30__EIM_D30		(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D31__EIM_D31		(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A16__GPIO_2_10		(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A17__GPIO_2_11		(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A18__GPIO_2_12		(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A19__GPIO_2_13		(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A20__GPIO_2_14		(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A21__GPIO_2_15		(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A22__GPIO_2_16		(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A23__GPIO_2_17		(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A24__GPIO_2_18		(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A25__GPIO_2_19		(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A26__GPIO_2_20		(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A27__GPIO_2_21		(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)

#define MX51_PAD_EIM_EB0__EIM_EB0 (0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB1__EIM_EB1 (0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB2__GPIO_2_22 (0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB3__GPIO_2_23 (0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_OE__GPIO_2_24 (0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_EIM_CS0__GPIO_2_25		(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS1__GPIO_2_26		(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS2__GPIO_2_27		(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS3__GPIO_2_28		(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS4__GPIO_2_29		(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS5__GPIO_2_30		(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)

#define MX51_PAD_EIM_DTACK__GPIO_2_31 (0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_LBA__GPIO_3_1 (0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CRE__GPIO_3_2 (0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DRAM_CS1__DRAM_CS1 (0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_WE_B__GPIO_3_3 (0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RE_B__GPIO_3_4 (0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_ALE__GPIO_3_5 (0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CLE__GPIO_3_6 (0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_WP_B__GPIO_3_7 (0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB0__GPIO_3_8 (0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__GPIO_3_9 (0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_NANDF_RB2__GPIO_3_10		(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB3__GPIO_3_11		(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_NAND__GPIO_3_12		(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB6__GPIO_3_14		(0x5DC, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS0__GPIO_3_16		(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS1__GPIO_3_17		(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS2__GPIO_3_18		(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS3__GPIO_3_19		(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS4__GPIO_3_20		(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS5__GPIO_3_21		(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS6__GPIO_3_22		(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS7__GPIO_3_23		(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24	(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D15__GPIO_3_25		(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D14__GPIO_3_26		(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D13__GPIO_3_27		(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D12__GPIO_3_28		(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D11__GPIO_3_29		(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D10__GPIO_3_30		(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D9__GPIO_3_31		(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D8__GPIO_4_0		(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D7__GPIO_4_1		(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D6__GPIO_4_2		(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D5__GPIO_4_3		(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D4__GPIO_4_4		(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D3__GPIO_4_5		(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D2__GPIO_4_6		(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D1__GPIO_4_7		(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D0__GPIO_4_8		(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D8__GPIO_3_12		(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D9__GPIO_3_13		(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D10__CSI1_D10		(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D11__CSI1_D11		(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D12__CSI1_D12		(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D13__CSI1_D13		(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D14__CSI1_D14		(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D15__CSI1_D15		(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D16__CSI1_D16		(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D17__CSI1_D17		(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D18__CSI1_D18		(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D19__CSI1_D19		(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)

#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK (0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 (0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D12__GPIO_4_9 (0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_CSI2_D13__GPIO_4_10		(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D14__GPIO_4_11		(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D15__GPIO_4_12		(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D16__GPIO_4_11		(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D17__GPIO_4_12		(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D18__GPIO_4_11		(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D19__GPIO_4_12		(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)

#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 (0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 (0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 (0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 (0x81C, 0x000, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_CLK__GPIO_4_16 (0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_DAT__GPIO_4_17 (0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 (0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 (0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_AUD3_BB_CK__GPIO_4_20		(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_FS__GPIO_4_21		(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MOSI__GPIO_4_22		(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MISO__GPIO_4_23		(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS0__GPIO_4_24		(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS1__GPIO_4_25		(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_RDY__GPIO_4_26		(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)

#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 (0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART1_RXD__UART1_RXD (0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_TXD__UART1_TXD (0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_RTS__UART1_RTS (0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
#define MX51_PAD_UART1_CTS__UART1_CTS (0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL)
#define MX51_PAD_UART2_RXD__UART2_RXD (0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)

#define MX51_PAD_UART2_TXD__UART2_TXD		(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
#define MX51_PAD_UART3_RXD__GPIO_1_22		(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_UART3_TXD__GPIO_1_23		(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_OWIRE_LINE__GPIO_1_24		(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW0__KEY_ROW0		(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW1__KEY_ROW1		(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW2__KEY_ROW2		(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW3__KEY_ROW3		(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL0__KEY_COL0		(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL1__KEY_COL1		(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL2__KEY_COL2		(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL3__KEY_COL3		(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL4__KEY_COL4		(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL5__KEY_COL5		(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_CLK__USBH1_CLK		(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DIR__USBH1_DIR		(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_STP__USBH1_STP		(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_STP__GPIO_1_27		(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_NXT__USBH1_NXT		(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_DI1_PIN11__GPIO_3_0		(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN12__GPIO_3_1		(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN13__GPIO_3_2		(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_D0_CS__GPIO_3_3		(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_D1_CS__GPIO_3_4		(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5	(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6	(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7	(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8	(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0		(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1		(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2		(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3		(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4		(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5		(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6		(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7		(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8		(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9		(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN3__DI1_PIN3		(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN2__DI1_PIN2		(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP1__DI_GP1			(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP2__DI_GP2			(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP3__DI_GP3			(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN4__DI2_PIN4		(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN2__DI2_PIN2		(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN3__DI2_PIN3		(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP4__DI_GP4			(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0		(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1		(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2		(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3		(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4		(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5		(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT6__GPIO_1_19		(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT7__GPIO_1_29		(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT8__GPIO_1_30		(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT9__GPIO_1_31		(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CMD__SD1_CMD		(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CLK__SD1_CLK		(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__SD1_DATA0		(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__SD1_DATA1		(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__SD1_DATA2		(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__SD1_DATA3		(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)

#define MX51_PAD_GPIO1_0__GPIO_1_0 (0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_1__GPIO_1_1 (0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD (0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CLK__SD2_CLK (0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_SD2_DATA0__SD2_DATA0		(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA1__SD2_DATA1		(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA2__SD2_DATA2		(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA3__SD2_DATA3		(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_2__GPIO_1_2		(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_3__GPIO_1_3		(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_4__GPIO_1_4		(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_5__GPIO_1_5		(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_6__GPIO_1_6		(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_7__GPIO_1_7		(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_8__GPIO_1_8		(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)

#define MX51_PAD_GPIO1_9__GPIO_1_9 (0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)

Signature · 4 lines

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Alberto Panizzo

2010-06-04 09:48 UTC #14 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

Quoted 8 lines · Sascha Hauer

I'm not willing to accept another 3ds_debug board support in the kernel
given that it's no rocket science to seperate this into another file and
we still have plenty of time before the next merge window. Jason, can you please move this to plat-mxc? I think we could find someone else to switch the mx31_3ds support to the generic debug board support then.

Sascha, what do you mean with: switch the mx31_3ds support to the generic one in plat-mxc?
We are going to have a single machine file for all imx(2-3-5) based debug boards? I think it will look so messy..

I read the Linus concerns about ARM stuffs and RMK answer to your ask for pull.. May we need to start a thread to discuss how we can restructure the imx support?

Signature · 4 lines

Alberto!

        Be Persistent!
                - Greg Kroah-Hartman (FOSDEM 2010)

Sascha Hauer

maintainer

2010-06-04 15:22 UTC #15 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

Quoted 10 lines · Alberto Panizzo

Quoted 8 lines · Sascha Hauer
I'm not willing to accept another 3ds_debug board support in the kernel
given that it's no rocket science to seperate this into another file and
we still have plenty of time before the next merge window. Jason, can you please move this to plat-mxc? I think we could find someone else to switch the mx31_3ds support to the generic debug board support then.

Quoted 2 lines

Sascha, what do you mean with: switch the mx31_3ds support to the generic one in plat-mxc?

Only the 3ds debug board, not the mx31_3ds board as a whole.

Quoted 2 lines

We are going to have a single machine file for all imx(2-3-5) based debug boards? I think it will look so messy..

Look at Jasons next patch, this is what I meant. We can reuse the 3ds debug board stuff in the mx31_3ds.

Quoted 3 lines

I read the Linus concerns about ARM stuffs and RMK answer to your ask for pull.. May we need to start a thread to discuss how we can restructure the imx support?

Well, the ultimate goal is to support all i.MX ports in one kernel, but this is still a long way to go. We made quite some progress with Uwes patches to avoid namespace collisions in the different register defines, but there is still enough left to do. Try to tweak Kconfig to enable for example i.MX27 and i.MX25 support and see what happens...

Sascha

Signature · 4 lines

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Amit Kucheria

2010-06-04 10:53 UTC #16 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

In reply to Sascha Hauer

Quoted 9 lines · Sascha Hauer

arch/arm/plat-mxc/include/mach/iomux-mx51.h typedef enum iomux_config { · line 208
Quoted 5 lines · Jason Wang
arch/arm/plat-mxc/include/mach/iomux-mx51.h +2 -2
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
Urgs, there really is something wrong here.

Quoted 4 lines

First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22 as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be wrong with many (all?) defines in this file. Amit, you should have read the comment ontop of this file which you copied from the i.MX35 part:

I'll admit that I was not completely conversant with the naming scheme then. All the GPIO-related names have been reversed. The others seem fine.

Quoted 5 lines

/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/

There was a comment below this:
/*
* FIXME: This was converted using scripts from existing Freescale code to
* this form used upstream. Need to verify the name format.
*/

I obviously reversed the naming for all the GPIO pads.

Quoted 1 line

This should be fixed before doing any other change to this file.

I'm preparing a patch now.

Quoted 5 lines

Then Jason, what you are looking for is the following:
#define MX51_PAD_UART3_RXD__UART3_RXD
because you want the UART3_RXD pad in its native mode.

Cheers,
Amit

Signature · 3 lines

----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------

Amit Kucheria

2010-06-04 14:09 UTC #17 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 30 lines · Amit Kucheria

Quoted 9 lines · Sascha Hauer
arch/arm/plat-mxc/include/mach/iomux-mx51.h typedef enum iomux_config { · line 208
Quoted 5 lines · Jason Wang
arch/arm/plat-mxc/include/mach/iomux-mx51.h +2 -2
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
Urgs, there really is something wrong here.
Quoted 4 lines
First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22 as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be wrong with many (all?) defines in this file. Amit, you should have read the comment ontop of this file which you copied from the i.MX35 part:
I'll admit that I was not completely conversant with the naming scheme then. All the GPIO-related names have been reversed. The others seem fine.
Quoted 5 lines
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
There was a comment below this:
/*
* FIXME: This was converted using scripts from existing Freescale code to
* this form used upstream. Need to verify the name format.
*/

Quoted 6 lines

I obviously reversed the naming for all the GPIO pads.
Quoted 1 line
This should be fixed before doing any other change to this file.
I'm preparing a patch now.

Please find the patch attached.

You can see the output of diff without the whitespace changes here:
http://paste.ubuntu.com/444628/

Troy Kisky

2010-06-07 20:41 UTC #18 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 609 lines · Amit Kucheria

Quoted 27 lines · Amit Kucheria

Quoted 8 lines · Sascha Hauer
arch/arm/plat-mxc/include/mach/iomux-mx51.h typedef enum iomux_config { · line 208
Quoted 5 lines · Jason Wang
arch/arm/plat-mxc/include/mach/iomux-mx51.h +2 -2
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
Urgs, there really is something wrong here.
Quoted 4 lines
First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22 as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be wrong with many (all?) defines in this file. Amit, you should have read the comment ontop of this file which you copied from the i.MX35 part:
I'll admit that I was not completely conversant with the naming scheme then. All the GPIO-related names have been reversed. The others seem fine.
Quoted 5 lines
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
There was a comment below this:
/*
* FIXME: This was converted using scripts from existing Freescale code to
* this form used upstream. Need to verify the name format.
*/

Quoted 5 lines

I obviously reversed the naming for all the GPIO pads.
Quoted 1 line
This should be fixed before doing any other change to this file.
I'm preparing a patch now.

Please find the patch attached.

You can see the output of diff without the whitespace changes here:
http://paste.ubuntu.com/444628/

Quoted 1 line

From 00a83837915e2056367b09dfc322ced601e67658 Mon Sep 17 00:00:00 2001

Message-Id: <00a83837915e2056367b09dfc322ced601e67658.1275659667.git.amit.kucheria@canonical.com>
From: Amit Kucheria <[email protected]>
Date: Fri, 4 Jun 2010 16:50:27 +0300
Subject: [PATCH] mxc: Fix pad names for imx51

The pads capable of being used as GPIOs had their pad-name and mode-name switched. Also fix the following:

- Whitespace fixes
- Replace IOMUX_CONFIG_ALTn with 'n'

Signed-off-by Amit Kucheria <[email protected]>

---
 arch/arm/mach-mx5/board-mx51_babbage.c      |    2 +-
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |  533 +++++++++++++--------------
 2 files changed, 252 insertions(+), 283 deletions(-)

arch/arm/mach-mx5/board-mx51_babbage.c +1 -1

index ed885f9..4f96d9c 100644
@@ -78,7 +78,7 @@ static struct pad_desc mx51babbage_pads[] = {
 	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
 	/* USB HUB reset line*/
-	MX51_PAD_GPIO_1_7__GPIO1_7,
+	MX51_PAD_GPIO_1_7__GPIO_1_7,
 };
 
 /* Serial ports */

arch/arm/plat-mxc/include/mach/iomux-mx51.h +241 ~~-282~~

index ab0f95d..e8648bc 100644
@@ -27,8 +27,8 @@ typedef enum iomux_config {
 	IOMUX_CONFIG_ALT5,
 	IOMUX_CONFIG_ALT6,
 	IOMUX_CONFIG_ALT7,
-	IOMUX_CONFIG_GPIO,	/* added to help user use GPIO mode */
-	IOMUX_CONFIG_SION = 0x1 << 4,	/* LOOPBACK:MUX SION bit */
+	IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
+	IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
 } iomux_pin_cfg_t;
 
 /* Pad control groupings */

@@ -50,285 +50,254 @@ typedef enum iomux_config {
  * GPIO_<unit>_<num> see also iomux-v3.h
  */
 
-/*
- * FIXME: This was converted using scripts from existing Freescale code to
- * this form used upstream. Need to verify the name format.
- */
-
-/*						PAD      MUX   ALT INPSE PATH PADCTRL */
-
-#define MX51_PAD_GPIO_2_0__EIM_D16	IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18	IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_3__EIM_D19	IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20	IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21	IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5	IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22	IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23	IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30	IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31	IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16	IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17	IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18	IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19	IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20	IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21	IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22	IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23	IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24	IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25	IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26	IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27	IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0	IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1	IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2	IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3	IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE	IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0	IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1	IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2	IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3	IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4	IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5	IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA	IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE	IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1	IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B	IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B	IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE	IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE	IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B	IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0	IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1	IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2	IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3	IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND	IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4	IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5	IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7	IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6	IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0	IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1	IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2	IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3	IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4	IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5	IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6	IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7	IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15	IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14	IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13	IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12	IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11	IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10	IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9	IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8	IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7	IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6	IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5	IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4	IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3	IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2	IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1	IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0	IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8	IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9	IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10	IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11	IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12	IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13	IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14	IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15	IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16	IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17	IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18	IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19	IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC	IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC	IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK	IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0	IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12	IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13	IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14	IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15	IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16	IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17	IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18	IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19	IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC	IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC	IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK	IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0	IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_16__I2C1_CLK	IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_17__I2C1_DAT	IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD	IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD	IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK	IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS	IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO	IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0	IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY	IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x618, 0x228,	IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2	IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3	IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0	IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1	IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2	IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3	IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4	IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5	IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK	IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR	IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT	IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11	IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12	IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13	IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS	IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS	IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0	IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1	IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2	IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3	IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4	IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5	IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6	IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7	IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8	IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9	IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3	IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2	IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1	IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2	IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3	IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4	IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2	IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3	IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4	IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0	IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1	IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2	IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3	IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4	IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5	IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6	IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7	IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8	IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9	IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0	IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1	IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD	IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK	IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0	IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1	IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2	IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3	IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2	IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3	IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9	IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0	IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1	IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2	IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3	IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4	IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5	IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6	IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7	IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8	IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9	IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10	IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11	IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12	IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13	IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14	IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15	IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+/*							  PAD    MUX   ALT INPSE PATH PADCTRL */
+#define MX51_PAD_EIM_DA0__EIM_DA0		IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1		IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2		IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3		IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4		IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5		IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6		IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7		IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8		IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9		IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10		IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11		IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12		IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13		IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14		IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15		IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5		IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_0__GPIO_1_0		IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1		IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)

arch/arm/plat-mxc/include/mach/iomux-mx51.h typedef enum iomux_config { · line 301

Quoted 10 lines

arch/arm/plat-mxc/include/mach/iomux-mx51.h +10 -0

+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)

Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?

Quoted 2 lines

arch/arm/plat-mxc/include/mach/iomux-mx51.h +0 -0
 #endif /* __MACH_IOMUX_MX51_H__ */

Amit Kucheria

2010-06-07 21:04 UTC #19 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 2 lines · Troy Kisky

Quoted 2 lines · Amit Kucheria

<snip>

Quoted 1 line

Quoted 1 line
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)

<snip>

Quoted 4 lines

(quoted diff) +4 -0

+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)

Quoted 9 lines

Review

Quoted 5 lines

(quoted diff) +5 -0

+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)

Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?

Just following the convention use in the rest of imx devices. See the following comment at the top of the file:

/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/

We could use the short names for pads being used in their "native mode". But as soon as we use the pad in a different mode, such as PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.

Regards,
Amit

Signature · 3 lines

----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------

Troy Kisky

2010-06-07 21:15 UTC #20 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 33 lines · Amit Kucheria

Quoted 2 lines · Troy Kisky
Quoted 2 lines · Amit Kucheria
<snip>
Quoted 1 line
Quoted 1 line
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
<snip>
Quoted 12 lines
Review
Quoted 9 lines
(quoted diff) +9 -0
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
Just following the convention use in the rest of imx devices. See the following comment at the top of the file:
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/

Quoted 7 lines

We could use the short names for pads being used in their "native mode". But as soon as we use the pad in a different mode, such as PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
Regards,
Amit

I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to

/*
* The naming convention for the pad modes is MX51_PAD_<padname>
* or MX51_PAD_<padname>__<padmode> if padname != padmode.
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/

Sascha Hauer

maintainer

2010-06-08 06:30 UTC #21 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 45 lines · Troy Kisky

Quoted 33 lines · Amit Kucheria
Quoted 2 lines · Troy Kisky
Quoted 2 lines · Amit Kucheria
<snip>
Quoted 1 line
Quoted 1 line
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
<snip>
Quoted 12 lines
Review
Quoted 9 lines
(quoted diff) +9 -0
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
Just following the convention use in the rest of imx devices. See the following comment at the top of the file:
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
Quoted 7 lines
We could use the short names for pads being used in their "native mode". But as soon as we use the pad in a different mode, such as PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
Regards,
Amit
I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to

Quoted 6 lines

/*
* The naming convention for the pad modes is MX51_PAD_<padname>
* or MX51_PAD_<padname>__<padmode> if padname != padmode.
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/

If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long name to get a consistent naming and to express the fact that the pad has a name and the mode has a name which can but don't has to be the same.

Sascha

Signature · 4 lines

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Amit Kucheria

2010-06-09 13:09 UTC #22 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 53 lines · Sascha Hauer

Quoted 45 lines · Troy Kisky
Quoted 33 lines · Amit Kucheria
Quoted 2 lines · Troy Kisky
Quoted 2 lines · Amit Kucheria
<snip>
Quoted 1 line
Quoted 1 line
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
<snip>
Quoted 12 lines
Review
Quoted 9 lines
(quoted diff) +9 -0
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
Just following the convention use in the rest of imx devices. See the following comment at the top of the file:
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
Quoted 7 lines
We could use the short names for pads being used in their "native mode". But as soon as we use the pad in a different mode, such as PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
Regards,
Amit
I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
Quoted 6 lines
/*
* The naming convention for the pad modes is MX51_PAD_<padname>
* or MX51_PAD_<padname>__<padmode> if padname != padmode.
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/

Quoted 4 lines

If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long name to get a consistent naming and to express the fact that the pad has a name and the mode has a name which can but don't has to be the same.

So will you take a modified patch to reflect this new naming convention?

Regards,
Amit

Signature · 3 lines

----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------

Sascha Hauer

maintainer

2010-06-10 11:49 UTC #23 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 54 lines · Amit Kucheria

Quoted 53 lines · Sascha Hauer
Quoted 51 lines · Troy Kisky
Quoted 33 lines · Amit Kucheria
Quoted 2 lines · Troy Kisky
Quoted 2 lines · Amit Kucheria
<snip>
Quoted 1 line
Quoted 1 line
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
<snip>
Quoted 12 lines
Review
Quoted 9 lines
(quoted diff) +9 -0
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
Just following the convention use in the rest of imx devices. See the following comment at the top of the file:
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
Quoted 7 lines
We could use the short names for pads being used in their "native mode". But as soon as we use the pad in a different mode, such as PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
Regards,
Amit
I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
/*
* The naming convention for the pad modes is MX51_PAD_<padname>
* or MX51_PAD_<padname>__<padmode> if padname != padmode.
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/

Quoted 6 lines

Quoted 4 lines
If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long name to get a consistent naming and to express the fact that the pad has a name and the mode has a name which can but don't has to be the same.
So will you take a modified patch to reflect this new naming convention?

Unless there are strong opinions for short names I'd like to keep the old naming scheme as it is also used for other i.MX SoCs.

Sascha

Signature · 4 lines

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

jason

author

2010-06-10 13:04 UTC #24 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 68 lines · Sascha Hauer

Quoted 66 lines · Amit Kucheria
Quoted 64 lines · Sascha Hauer
Quoted 50 lines · Troy Kisky
Quoted 37 lines · Amit Kucheria
Quoted 3 lines · Troy Kisky
Quoted 3 lines · Amit Kucheria
<snip>
Quoted 2 lines
Quoted 2 lines
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
<snip>
Quoted 4 lines
Quoted 4 lines
(quoted diff) +4 -0
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
Quoted 10 lines
Review
Quoted 6 lines
(quoted diff) +5 -0
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
Just following the convention use in the rest of imx devices. See the following comment at the top of the file:
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
Quoted 8 lines
We could use the short names for pads being used in their "native mode". But as soon as we use the pad in a different mode, such as PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
Regards,
Amit
I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
Quoted 7 lines
/*
* The naming convention for the pad modes is MX51_PAD_<padname>
* or MX51_PAD_<padname>__<padmode> if padname != padmode.
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long name to get a consistent naming and to express the fact that the pad has a name and the mode has a name which can but don't has to be the same.

Quoted 10 lines

Quoted 2 lines
So will you take a modified patch to reflect this new naming convention?
Unless there are strong opinions for short names I'd like to keep the old naming scheme as it is also used for other i.MX SoCs.
Sascha

From the discussion, it seems that Amit's patch for iomux-mx51.h is the
best choice,
So i will rebase my patches off that. Is it acceptable?

Thanks,
Jason.

Sascha Hauer

maintainer

2010-06-10 13:59 UTC #25 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

Quoted 75 lines · jason

Quoted 74 lines · Sascha Hauer
Quoted 61 lines · Amit Kucheria
Quoted 59 lines · Sascha Hauer
Quoted 57 lines · Troy Kisky
Quoted 37 lines · Amit Kucheria
Quoted 3 lines · Troy Kisky
Quoted 3 lines · Amit Kucheria
<snip>
Quoted 2 lines
Quoted 2 lines
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
<snip>
Quoted 4 lines
Quoted 4 lines
(quoted diff) +4 -0
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
Quoted 10 lines
Review
Quoted 6 lines
(quoted diff) +5 -0
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
Just following the convention use in the rest of imx devices. See the following comment at the top of the file:
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
Quoted 8 lines
We could use the short names for pads being used in their "native mode". But as soon as we use the pad in a different mode, such as PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
Regards,
Amit
I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
/*
* The naming convention for the pad modes is MX51_PAD_<padname>
* or MX51_PAD_<padname>__<padmode> if padname != padmode.
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
Quoted 7 lines
Quoted 5 lines
If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long name to get a consistent naming and to express the fact that the pad has a name and the mode has a name which can but don't has to be the same.
So will you take a modified patch to reflect this new naming convention?
Unless there are strong opinions for short names I'd like to keep the old naming scheme as it is also used for other i.MX SoCs.

Quoted 7 lines

Quoted 4 lines
Sascha
From the discussion, it seems that Amit's patch for iomux-mx51.h is the best choice,
So i will rebase my patches off that. Is it acceptable?

Yes, ok.

Sascha

Signature · 4 lines

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Amit Kucheria

2010-06-10 19:24 UTC #26 lore raw

PATCH 1/1 mxc: Fix pad names for imx51

In reply to Sascha Hauer

Quoted 60 lines · Sascha Hauer

Quoted 59 lines · Amit Kucheria
Quoted 57 lines · Sascha Hauer
Quoted 45 lines · Troy Kisky
Quoted 33 lines · Amit Kucheria
Quoted 2 lines · Troy Kisky
Quoted 2 lines · Amit Kucheria
<snip>
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+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
<snip>
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Review
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(quoted diff) +9 -0
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
Just following the convention use in the rest of imx devices. See the following comment at the top of the file:
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
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We could use the short names for pads being used in their "native mode". But as soon as we use the pad in a different mode, such as PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
Regards,
Amit
I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
Quoted 6 lines
/*
* The naming convention for the pad modes is MX51_PAD_<padname>
* or MX51_PAD_<padname>__<padmode> if padname != padmode.
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long name to get a consistent naming and to express the fact that the pad has a name and the mode has a name which can but don't has to be the same.

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So will you take a modified patch to reflect this new naming convention?
Unless there are strong opinions for short names I'd like to keep the old naming scheme as it is also used for other i.MX SoCs.

I don't have a strong opinion, but I think that the existing naming scheme makes things a little more explicit by separating out pad name from pad mode. I like it a little better.

Regards,
Amit

Signature · 3 lines

----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------

jason

author

2010-06-04 12:50 UTC #27 lore raw

PATCH v2 1/3 mxc: Add support for the imx51 3-stack board

In reply to Sascha Hauer

Quoted 15 lines · Sascha Hauer

arch/arm/mach-mx5/board-mx51_3ds.c line 100
Quoted 4 lines · Jason Wang
arch/arm/mach-mx5/board-mx51_3ds.c new file +3 -0
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
I'm not willing to accept another 3ds_debug board support in the kernel given that it's no rocket science to seperate this into another file and we still have plenty of time before the next merge window. Jason, can you please move this to plat-mxc? I think we could find someone else to switch the mx31_3ds support to the generic debug board support then.

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[snip]

OK, i will add a common part for debug board in V3.

Thanks,
Jason.

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#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
arch/arm/plat-mxc/include/mach/iomux-mx51.h +2 -1
+#define MX51_PAD_EIM_D25__UART2_CTS	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, MX51_UART2_PAD_CTRL)

<snip>

Quoted 22 lines

Urgs, there really is something wrong here.
First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22 as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be wrong with many (all?) defines in this file. Amit, you should have read the comment ontop of this file which you copied from the i.MX35 part:
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named
* GPIO_<unit>_<num> see also iomux-v3.h
*/
This should be fixed before doing any other change to this file.
Then Jason, what you are looking for is the following:
#define MX51_PAD_UART3_RXD__UART3_RXD
because you want the UART3_RXD pad in its native mode.

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Here is how the defines in this file should look like (modulo bugs):

#define MX51_PAD_EIM_D16__GPIO_2_0		(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D17__GPIO_2_1		(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D18__GPIO_2_2		(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D19__GPIO_2_3		(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D20__GPIO_2_4		(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)

Yes, some pin names are wrong. It seems that you have already got a update for cleanup of those pad names, but it haven't pushed to upstream, i will cherry pick this update and basing on it add mx51_3ds specific pads.

Thanks,
Jason.

Quoted 4 lines

#define MX51_PAD_EIM_D21__GPIO_2_5		(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D22__GPIO_2_6		(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D23__GPIO_2_7		(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)

<snip>