Some Cavium CNS3xxx updates for 2.6.36

GIT PULL New Anton Vorontsov 1 participant 7 messages Jun 8, 2010 – Jul 22, 2010

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Anton Vorontsov

author

2010-06-08 17:00 UTC #0 lore raw

Hi Russell,

The main reason for the v2 is, obviously, the defconfigs situation. I dropped the defconfig update in this pull request.

There are also few improvements as suggested by by Ben Dooks and Sergei Shtylyov, plus there is no longer the ugly "../../../drivers/mmc/host/sdhci.h" include anymore.

As usual, I'm posting the updated patches as well.

The following changes since commit 9dda696f0de87a2e5cfabb147e28c76b7d3c6846:
Linus Torvalds (1):

        Merge branch 'release' of git://git.kernel.org/.../aegl/linux-2.6

are available in the git repository at:

git://git.infradead.org/users/cbou/linux-cns3xxx.git master

Anton Vorontsov (4):
ARM: cns3xxx: Use IO memory accessors everywhere
ARM: cns3xxx: Add support for PCI Express ports
ARM: cns3xxx: Add support for SDHCI controllers
ARM: cns3xxx: Add support for AHCI controllers

 arch/arm/Kconfig                             |    3 +-
 arch/arm/mach-cns3xxx/Makefile               |    3 +-
 arch/arm/mach-cns3xxx/cns3420vb.c            |    4 +
 arch/arm/mach-cns3xxx/devices.c              |  111 ++++++++
 arch/arm/mach-cns3xxx/devices.h              |   20 ++
 arch/arm/mach-cns3xxx/include/mach/cns3xxx.h |   91 +++---
 arch/arm/mach-cns3xxx/pcie.c                 |  389 ++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/pm.c                   |   31 ++-
 8 files changed, 596 insertions(+), 56 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/devices.c
 create mode 100644 arch/arm/mach-cns3xxx/devices.h
 create mode 100644 arch/arm/mach-cns3xxx/pcie.c

Anton Vorontsov

author

2010-06-08 17:01 UTC #1 lore raw

PATCH 1/4 ARM: cns3xxx: Use IO memory accessors everywhere

Before it isn't too late let's switch to IO memory accessors. This patch converts all current _REG users and _REG definitions. There should be no functional changes.

Suggested-by Ben Dooks <[email protected]>

Signed-off-by Anton Vorontsov <[email protected]>

---
 arch/arm/mach-cns3xxx/include/mach/cns3xxx.h |   91 +++++++++++++-------------
 arch/arm/mach-cns3xxx/pm.c                   |   31 +++++++--
 2 files changed, 68 insertions(+), 54 deletions(-)

arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +45 ~~-46~~

index 8a2f5a2..6dbce13 100644
@@ -247,37 +247,36 @@
  * Misc block
  */
 #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
-#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
-
-#define MISC_MEMORY_REMAP_REG			MISC_MEM_MAP_VALUE(0x00)
-#define MISC_CHIP_CONFIG_REG			MISC_MEM_MAP_VALUE(0x04)
-#define MISC_DEBUG_PROBE_DATA_REG		MISC_MEM_MAP_VALUE(0x08)
-#define MISC_DEBUG_PROBE_SELECTION_REG		MISC_MEM_MAP_VALUE(0x0C)
-#define MISC_IO_PIN_FUNC_SELECTION_REG		MISC_MEM_MAP_VALUE(0x10)
-#define MISC_GPIOA_PIN_ENABLE_REG		MISC_MEM_MAP_VALUE(0x14)
-#define MISC_GPIOB_PIN_ENABLE_REG		MISC_MEM_MAP_VALUE(0x18)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A	MISC_MEM_MAP_VALUE(0x1C)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B	MISC_MEM_MAP_VALUE(0x20)
-#define MISC_GPIOA_15_0_PULL_CTRL_REG		MISC_MEM_MAP_VALUE(0x24)
-#define MISC_GPIOA_16_31_PULL_CTRL_REG		MISC_MEM_MAP_VALUE(0x28)
-#define MISC_GPIOB_15_0_PULL_CTRL_REG		MISC_MEM_MAP_VALUE(0x2C)
-#define MISC_GPIOB_16_31_PULL_CTRL_REG		MISC_MEM_MAP_VALUE(0x30)
-#define MISC_IO_PULL_CTRL_REG			MISC_MEM_MAP_VALUE(0x34)
-#define MISC_E_FUSE_31_0_REG			MISC_MEM_MAP_VALUE(0x40)
-#define MISC_E_FUSE_63_32_REG			MISC_MEM_MAP_VALUE(0x44)
-#define MISC_E_FUSE_95_64_REG			MISC_MEM_MAP_VALUE(0x48)
-#define MISC_E_FUSE_127_96_REG			MISC_MEM_MAP_VALUE(0x4C)
-#define MISC_SOFTWARE_TEST_1_REG		MISC_MEM_MAP_VALUE(0x50)
-#define MISC_SOFTWARE_TEST_2_REG		MISC_MEM_MAP_VALUE(0x54)
-
-#define MISC_SATA_POWER_MODE			MISC_MEM_MAP_VALUE(0x310)
-
-#define MISC_USB_CFG_REG			MISC_MEM_MAP_VALUE(0x800)
-#define MISC_USB_STS_REG			MISC_MEM_MAP_VALUE(0x804)
-#define MISC_USBPHY00_CFG_REG			MISC_MEM_MAP_VALUE(0x808)
-#define MISC_USBPHY01_CFG_REG			MISC_MEM_MAP_VALUE(0x80c)
-#define MISC_USBPHY10_CFG_REG			MISC_MEM_MAP_VALUE(0x810)
-#define MISC_USBPHY11_CFG_REG			MISC_MEM_MAP_VALUE(0x814)
+
+#define MISC_MEMORY_REMAP_REG			MISC_MEM_MAP(0x00)
+#define MISC_CHIP_CONFIG_REG			MISC_MEM_MAP(0x04)
+#define MISC_DEBUG_PROBE_DATA_REG		MISC_MEM_MAP(0x08)
+#define MISC_DEBUG_PROBE_SELECTION_REG		MISC_MEM_MAP(0x0C)
+#define MISC_IO_PIN_FUNC_SELECTION_REG		MISC_MEM_MAP(0x10)
+#define MISC_GPIOA_PIN_ENABLE_REG		MISC_MEM_MAP(0x14)
+#define MISC_GPIOB_PIN_ENABLE_REG		MISC_MEM_MAP(0x18)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A	MISC_MEM_MAP(0x1C)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B	MISC_MEM_MAP(0x20)
+#define MISC_GPIOA_15_0_PULL_CTRL_REG		MISC_MEM_MAP(0x24)
+#define MISC_GPIOA_16_31_PULL_CTRL_REG		MISC_MEM_MAP(0x28)
+#define MISC_GPIOB_15_0_PULL_CTRL_REG		MISC_MEM_MAP(0x2C)
+#define MISC_GPIOB_16_31_PULL_CTRL_REG		MISC_MEM_MAP(0x30)
+#define MISC_IO_PULL_CTRL_REG			MISC_MEM_MAP(0x34)
+#define MISC_E_FUSE_31_0_REG			MISC_MEM_MAP(0x40)
+#define MISC_E_FUSE_63_32_REG			MISC_MEM_MAP(0x44)
+#define MISC_E_FUSE_95_64_REG			MISC_MEM_MAP(0x48)
+#define MISC_E_FUSE_127_96_REG			MISC_MEM_MAP(0x4C)
+#define MISC_SOFTWARE_TEST_1_REG		MISC_MEM_MAP(0x50)
+#define MISC_SOFTWARE_TEST_2_REG		MISC_MEM_MAP(0x54)
+
+#define MISC_SATA_POWER_MODE			MISC_MEM_MAP(0x310)
+
+#define MISC_USB_CFG_REG			MISC_MEM_MAP(0x800)
+#define MISC_USB_STS_REG			MISC_MEM_MAP(0x804)
+#define MISC_USBPHY00_CFG_REG			MISC_MEM_MAP(0x808)
+#define MISC_USBPHY01_CFG_REG			MISC_MEM_MAP(0x80c)
+#define MISC_USBPHY10_CFG_REG			MISC_MEM_MAP(0x810)
+#define MISC_USBPHY11_CFG_REG			MISC_MEM_MAP(0x814)
 
 #define MISC_PCIEPHY_CMCTL(x)			MISC_MEM_MAP(0x900 + (x) * 0x004)
 #define MISC_PCIEPHY_CTL(x)			MISC_MEM_MAP(0x940 + (x) * 0x100)

@@ -300,21 +299,21 @@
 /*
  * Power management and clock control
  */
-#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
-
-#define PM_CLK_GATE_REG					PMU_REG_VALUE(0x000)
-#define PM_SOFT_RST_REG					PMU_REG_VALUE(0x004)
-#define PM_HS_CFG_REG					PMU_REG_VALUE(0x008)
-#define PM_CACTIVE_STA_REG				PMU_REG_VALUE(0x00C)
-#define PM_PWR_STA_REG					PMU_REG_VALUE(0x010)
-#define PM_CLK_CTRL_REG					PMU_REG_VALUE(0x014)
-#define PM_PLL_LCD_I2S_CTRL_REG				PMU_REG_VALUE(0x018)
-#define PM_PLL_HM_PD_CTRL_REG				PMU_REG_VALUE(0x01C)
-#define PM_REGULAT_CTRL_REG				PMU_REG_VALUE(0x020)
-#define PM_WDT_CTRL_REG					PMU_REG_VALUE(0x024)
-#define PM_WU_CTRL0_REG					PMU_REG_VALUE(0x028)
-#define PM_WU_CTRL1_REG					PMU_REG_VALUE(0x02C)
-#define PM_CSR_REG					PMU_REG_VALUE(0x030)
+#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
+
+#define PM_CLK_GATE_REG					PMU_MEM_MAP(0x000)
+#define PM_SOFT_RST_REG					PMU_MEM_MAP(0x004)
+#define PM_HS_CFG_REG					PMU_MEM_MAP(0x008)
+#define PM_CACTIVE_STA_REG				PMU_MEM_MAP(0x00C)
+#define PM_PWR_STA_REG					PMU_MEM_MAP(0x010)
+#define PM_CLK_CTRL_REG					PMU_MEM_MAP(0x014)
+#define PM_PLL_LCD_I2S_CTRL_REG				PMU_MEM_MAP(0x018)
+#define PM_PLL_HM_PD_CTRL_REG				PMU_MEM_MAP(0x01C)
+#define PM_REGULAT_CTRL_REG				PMU_MEM_MAP(0x020)
+#define PM_WDT_CTRL_REG					PMU_MEM_MAP(0x024)
+#define PM_WU_CTRL0_REG					PMU_MEM_MAP(0x028)
+#define PM_WU_CTRL1_REG					PMU_MEM_MAP(0x02C)
+#define PM_CSR_REG					PMU_MEM_MAP(0x030)
 
 /* PM_CLK_GATE_REG */
 #define PM_CLK_GATE_REG_OFFSET_SDIO			(25)

arch/arm/mach-cns3xxx/pm.c +23 -8

index 725e1a4..38e4470 100644
@@ -6,18 +6,25 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/system.h>
 #include <mach/cns3xxx.h>
 
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
-	PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
+	u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+	reg |= (block & PM_CLK_GATE_REG_MASK);
+	__raw_writel(reg, PM_CLK_GATE_REG);
 }
 
 void cns3xxx_pwr_power_up(unsigned int block)
 {
-	PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
+	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
+	reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
+	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 
 	/* Wait for 300us for the PLL output clock locked. */
 	udelay(300);

@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
 
 void cns3xxx_pwr_power_down(unsigned int block)
 {
+	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
 	/* write '1' to power down */
-	PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
+	reg |= (block & CNS3XXX_PWR_PLL_ALL);
+	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 };
 
 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
 {
+	u32 reg = __raw_readl(PM_SOFT_RST_REG);
+
 	/*
 	 * bit 0, 28, 29 => program low to reset,
 	 * the other else program low and then high
 	 */
 	if (block & 0x30000001) {
-		PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+		reg &= ~(block & PM_SOFT_RST_REG_MASK);
 	} else {
-		PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
-		PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
+		reg &= ~(block & PM_SOFT_RST_REG_MASK);
+		reg |= (block & PM_SOFT_RST_REG_MASK);
 	}
+
+	__raw_writel(reg, PM_SOFT_RST_REG);
 }
 
 void cns3xxx_pwr_soft_rst(unsigned int block)

@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
  */
 int cns3xxx_cpu_clock(void)
 {
+	u32 reg = __raw_readl(PM_CLK_CTRL_REG);
 	int cpu;
 	int cpu_sel;
 	int div_sel;
 
-	cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
-	div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
+	cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
+	div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
 
 	cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;

Signature · 1 line

1.7.0.5

Anton Vorontsov

author

2010-06-08 17:01 UTC #2 lore raw

PATCH 2/4 ARM: cns3xxx: Add support for PCI Express ports

In reply to Anton Vorontsov

This patch adds PCIe support for CNS3xxx-based boards. The support was tested with a directly attached SKY2 NIC, and EHCI USB controller behind the PLX PEX8112 P2P bridge (to make sure that type1 cfg cycles work as expected).

Signed-off-by Anton Vorontsov <[email protected]>

---
 arch/arm/Kconfig               |    3 +-
 arch/arm/mach-cns3xxx/Makefile |    1 +
 arch/arm/mach-cns3xxx/pcie.c   |  389 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 392 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/pcie.c

arch/arm/Kconfig +2 -1

index 1f254bd..fab2ddd 100644
@@ -301,6 +301,7 @@ config ARCH_CNS3XXX
 	select CPU_V6
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
+	select PCI_DOMAINS if PCI
 	help
 	  Support for Cavium Networks CNS3XXX platform.

@@ -1059,7 +1060,7 @@ config ISA_DMA_API
 	bool
 
 config PCI
-	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
 	  bus system, i.e. the way the CPU talks to the other stuff inside

arch/arm/mach-cns3xxx/Makefile +1 -0

index 427507a..683f117 100644
@@ -1,2 +1,3 @@
 obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o
+obj-$(CONFIG_PCI)			+= pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o

arch/arm/mach-cns3xxx/pcie.c new file +389 -0

389 lines not on this page · raw message

Signature · 1 line

1.7.0.5

Anton Vorontsov

author

2010-06-08 17:01 UTC #3 lore raw

PATCH 3/4 ARM: cns3xxx: Add support for SDHCI controllers

In reply to Anton Vorontsov

CNS3xxx chips have SDHCI-compatible SDIO/SD/MMC controller. This patch adds the support using sdhci-cns3xxx driver.

Signed-off-by Anton Vorontsov <[email protected]>

---
 arch/arm/mach-cns3xxx/Makefile    |    2 +-
 arch/arm/mach-cns3xxx/cns3420vb.c |    3 ++
 arch/arm/mach-cns3xxx/devices.c   |   59 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/devices.h   |   19 ++++++++++++
 4 files changed, 82 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/devices.c
 create mode 100644 arch/arm/mach-cns3xxx/devices.h

arch/arm/mach-cns3xxx/Makefile +1 -1

index 683f117..11033f1 100644
@@ -1,3 +1,3 @@
-obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o
+obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o devices.o
 obj-$(CONFIG_PCI)			+= pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o

arch/arm/mach-cns3xxx/cns3420vb.c +3 -0

index 2e30c82..04ae1ce 100644
@@ -32,6 +32,7 @@
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
 #include "core.h"
+#include "devices.h"
 
 /*
  * NOR Flash

@@ -117,6 +118,8 @@ static void __init cns3420_init(void)
 {
 	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
+	cns3xxx_sdhci_init();
+
 	pm_power_off = cns3xxx_power_off;
 }

arch/arm/mach-cns3xxx/devices.c new file +59 -0

59 lines not on this page · raw message

arch/arm/mach-cns3xxx/devices.h new file +19 -0

new file mode 100644
index 0000000..0735a45
@@ -0,0 +1,19 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *		  Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *		  Anton Vorontsov <[email protected]>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_DEVICES_H_
+#define __CNS3XXX_DEVICES_H_
+
+void __init cns3xxx_sdhci_init(void);
+
+#endif /* __CNS3XXX_DEVICES_H_ */

Signature · 1 line

1.7.0.5

Anton Vorontsov

author

2010-06-08 17:02 UTC #4 lore raw

PATCH 4/4 ARM: cns3xxx: Add support for AHCI controllers

In reply to Anton Vorontsov

CNS3xxx chips have AHCI-compatible SATA controller. This patch adds the support using generic ahci_platform driver.

Signed-off-by Anton Vorontsov <[email protected]>

---
 arch/arm/mach-cns3xxx/cns3420vb.c |    1 +
 arch/arm/mach-cns3xxx/devices.c   |   52 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/devices.h   |    1 +
 3 files changed, 54 insertions(+), 0 deletions(-)

arch/arm/mach-cns3xxx/cns3420vb.c +1 -0

index 04ae1ce..9df8391 100644
@@ -118,6 +118,7 @@ static void __init cns3420_init(void)
 {
 	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
+	cns3xxx_ahci_init();
 	cns3xxx_sdhci_init();
 
 	pm_power_off = cns3xxx_power_off;

arch/arm/mach-cns3xxx/devices.c +52 -0

64 lines not on this page · raw message

arch/arm/mach-cns3xxx/devices.h +1 -0

index 0735a45..27e15a1 100644
@@ -14,6 +14,7 @@
 #ifndef __CNS3XXX_DEVICES_H_
 #define __CNS3XXX_DEVICES_H_
 
+void __init cns3xxx_ahci_init(void);
 void __init cns3xxx_sdhci_init(void);
 
 #endif /* __CNS3XXX_DEVICES_H_ */

Signature · 1 line

1.7.0.5

Anton Vorontsov

author

2010-06-30 21:11 UTC #5 lore raw

In reply to Anton Vorontsov

Hello Russell,

Quoted 9 lines · Anton Vorontsov

The main reason for the v2 is, obviously, the defconfigs situation. I dropped the defconfig update in this pull request.
There are also few improvements as suggested by by Ben Dooks and Sergei Shtylyov, plus there is no longer the ugly "../../../drivers/mmc/host/sdhci.h" include anymore.
As usual, I'm posting the updated patches as well.

Quoted 7 lines

The following changes since commit 9dda696f0de87a2e5cfabb147e28c76b7d3c6846:
Linus Torvalds (1):
        Merge branch 'release' of git://git.kernel.org/.../aegl/linux-2.6
are available in the git repository at:
git://git.infradead.org/users/cbou/linux-cns3xxx.git master

I noticed that you pulled some other trees, but not this one. Is there any particular reason, or it's in the queue?

Thanks,

Signature · 3 lines

Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2

Anton Vorontsov

author

2010-07-22 14:56 UTC #6 lore raw

Quoted 16 lines · Anton Vorontsov

Hello Russell,
Quoted 13 lines · Anton Vorontsov
The main reason for the v2 is, obviously, the defconfigs situation. I dropped the defconfig update in this pull request.
There are also few improvements as suggested by by Ben Dooks and Sergei Shtylyov, plus there is no longer the ugly "../../../drivers/mmc/host/sdhci.h" include anymore.
As usual, I'm posting the updated patches as well.
The following changes since commit 9dda696f0de87a2e5cfabb147e28c76b7d3c6846:
Linus Torvalds (1):
        Merge branch 'release' of git://git.kernel.org/.../aegl/linux-2.6

Quoted 8 lines

Quoted 3 lines
are available in the git repository at:
git://git.infradead.org/users/cbou/linux-cns3xxx.git master
I noticed that you pulled some other trees, but not this one. Is there any particular reason, or it's in the queue?
Thanks,

Ping?