xen: mce: use MSR_IA32_MCx_* macros

PATCH In review Christoph Egger 2 participants 3 messages Jun 9, 2010

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Christoph Egger

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2010-06-09 12:26 UTC #0 lore raw

PATCH 1/1 xen: mce: use MSR_IA32_MCx_* macros

Hi!

Attached makes makes xen mce use MSR_IA32_MCx_* macros consequently. No functional changes.

Signed-off-by Christoph Egger <[email protected]>

Signature · 6 lines

---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach b. Muenchen
Geschaeftsfuehrer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632

xen/arch/x86/cpu/mcheck/amd_k8.c +2 -2

diff -r 180acc6332a2 xen/arch/x86/cpu/mcheck/amd_k8.c
@@ -95,8 +95,8 @@ enum mcheck_type amd_k8_mcheck_init(stru
 			mcequirk_amd_apply(quirkflag);
 		} else {
 			/* Enable error reporting of all errors */
-			wrmsrl(MSR_IA32_MC0_CTL + 4 * i, 0xffffffffffffffffULL);
-			wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL);
+			wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL);
+			wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
 			break;
 		}
 	}

xen/arch/x86/cpu/mcheck/k7.c +6 -6

diff -r 180acc6332a2 xen/arch/x86/cpu/mcheck/k7.c
@@ -32,7 +32,7 @@ static fastcall void k7_machine_check(st
 		smp_processor_id(), mcgsth, mcgstl);
 
 	for (i=1; i<nr_mce_banks; i++) {
-		rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
+		rdmsr (MSR_IA32_MCx_STATUS(i),low, high);
 		if (high&(1<<31)) {
 			if (high & (1<<29))
 				recover |= 1;

@@ -41,16 +41,16 @@ static fastcall void k7_machine_check(st
 			printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
 			high &= ~(1<<31);
 			if (high & (1<<27)) {
-				rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
+				rdmsr (MSR_IA32_MCx_MISC(i), alow, ahigh);
 				printk ("[%08x%08x]", ahigh, alow);
 			}
 			if (high & (1<<26)) {
-				rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
+				rdmsr (MSR_IA32_MCx_ADDR(i), alow, ahigh);
 				printk (" at %08x%08x", ahigh, alow);
 			}
 			printk ("\n");
 			/* Clear it */
-			wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
+			wrmsr (MSR_IA32_MCx_STATUS(i), 0UL, 0UL);
 			/* Serialize */
 			wmb();
 			add_taint(TAINT_MACHINE_CHECK);

@@ -88,8 +88,8 @@ enum mcheck_type amd_k7_mcheck_init(stru
 	 * as some Athlons cause spurious MCEs when its enabled. */
 	wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
 	for (i=1; i<nr_mce_banks; i++) {
-		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
-		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+		wrmsr (MSR_IA32_MCx_CTL(i), 0xffffffff, 0xffffffff);
+		wrmsr (MSR_IA32_MCx_STATUS(i), 0x0, 0x0);
 	}
 
 	set_in_cr4 (X86_CR4_MCE);

xen/arch/x86/cpu/mcheck/mce.c +9 -9

diff -r 180acc6332a2 xen/arch/x86/cpu/mcheck/mce.c
@@ -142,7 +142,7 @@ static struct mcinfo_bank *mca_init_bank
 	}
 
 	memset(mib, 0, sizeof (struct mcinfo_bank));
-	mca_rdmsrl(MSR_IA32_MC0_STATUS + bank * 4, mib->mc_status);
+	mca_rdmsrl(MSR_IA32_MCx_STATUS(bank), mib->mc_status);
 
 	mib->common.type = MC_TYPE_BANK;
 	mib->common.size = sizeof (struct mcinfo_bank);

@@ -150,11 +150,11 @@ static struct mcinfo_bank *mca_init_bank
 
 	addr = misc = 0;
 	if (mib->mc_status & MCi_STATUS_MISCV)
-		mca_rdmsrl(MSR_IA32_MC0_MISC + 4 * bank, mib->mc_misc);
+		mca_rdmsrl(MSR_IA32_MCx_MISC(bank), mib->mc_misc);
 
 	if (mib->mc_status & MCi_STATUS_ADDRV)
 	{
-		mca_rdmsrl(MSR_IA32_MC0_ADDR + 4 * bank, mib->mc_addr);
+		mca_rdmsrl(MSR_IA32_MCx_ADDR(bank), mib->mc_addr);
 
 		if (mfn_valid(paddr_to_pfn(mib->mc_addr))) {
 			struct domain *d;

@@ -266,7 +266,7 @@ mctelem_cookie_t mcheck_mca_logout(enum 
 		if (!test_bit(i, bankmask))
 			continue;
 
-		mca_rdmsrl(MSR_IA32_MC0_STATUS + i * 4, status);
+		mca_rdmsrl(MSR_IA32_MCx_STATUS(i), status);
 		if (!(status & MCi_STATUS_VAL))
 			continue;	/* this bank has no valid telemetry */

@@ -316,7 +316,7 @@ mctelem_cookie_t mcheck_mca_logout(enum 
 		/* By default, need_clear = 1 */
 		if (who != MCA_MCE_SCAN && need_clear)
 			/* Clear status */
-			mca_wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL);
+			mca_wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
 		else if ( who == MCA_MCE_SCAN && need_clear)
 			set_bit(i, clear_bank);

@@ -576,10 +576,10 @@ void mcheck_mca_clearbanks(cpu_banks_t b
 	for (i = 0; i < 32 && i < nr_mce_banks; i++) {
 		if (!test_bit(i, bankmask))
 			continue;
-		mca_rdmsrl(MSR_IA32_MC0_STATUS + i * 4, status);
+		mca_rdmsrl(MSR_IA32_MCx_STATUS(i), status);
 		if (!(status & MCi_STATUS_VAL))
 			continue;
-		mca_wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL);
+		mca_wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
 	}
 }

@@ -711,7 +711,7 @@ void mcheck_init(struct cpuinfo_x86 *c)
         /* Don't care banks before firstbank */
         memset(h_mci_ctrl, 0xff, sizeof(h_mci_ctrl));
         for (i = firstbank; i < nr_mce_banks; i++)
-            rdmsrl(MSR_IA32_MC0_CTL + 4*i, h_mci_ctrl[i]);
+            rdmsrl(MSR_IA32_MCx_CTL(i), h_mci_ctrl[i]);
     }
     if (g_mcg_cap & MCG_CTL_P)
         rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl);

@@ -1037,7 +1037,7 @@ void intpose_inval(unsigned int cpu_nr, 
 
 #define	IS_MCA_BANKREG(r) \
     ((r) >= MSR_IA32_MC0_CTL && \
-    (r) <= MSR_IA32_MC0_MISC + (nr_mce_banks - 1) * 4 && \
+    (r) <= MSR_IA32_MCx_MISC(nr_mce_banks - 1) && \
     ((r) - MSR_IA32_MC0_CTL) % 4 != 0)	/* excludes MCi_CTL */
 
 int mca_ctl_conflict(struct mcinfo_bank *bank, struct domain *d)

xen/arch/x86/cpu/mcheck/mce.h +1 -1

diff -r 180acc6332a2 xen/arch/x86/cpu/mcheck/mce.h
@@ -188,7 +188,7 @@ static inline int mce_vendor_bank_msr(ui
 static inline int mce_bank_msr(uint32_t msr)
 {
     if ( (msr > MSR_IA32_MC0_CTL2 &&
-         msr < (MSR_IA32_MC0_CTL + 4 * nr_mce_banks - 1)) ||
+         msr < (MSR_IA32_MCx_CTL(nr_mce_banks - 1))) ||
         mce_vendor_bank_msr(msr) )
         return 1;
     return 0;

xen/arch/x86/cpu/mcheck/mce_intel.c +3 -3

diff -r 180acc6332a2 xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -940,13 +940,13 @@ static void mce_init(void)
     {
         /* Some banks are shared across cores, use MCi_CTRL to judge whether
          * this bank has been initialized by other cores already. */
-        rdmsr(MSR_IA32_MC0_CTL + 4*i, l, h);
+        rdmsr(MSR_IA32_MCx_CTL(i), l, h);
         if (!(l | h))
         {
             /* if ctl is 0, this bank is never initialized */
             mce_printk(MCE_VERBOSE, "mce_init: init bank%d\n", i);
-            wrmsr (MSR_IA32_MC0_CTL + 4*i, 0xffffffff, 0xffffffff);
-            wrmsr (MSR_IA32_MC0_STATUS + 4*i, 0x0, 0x0);
+            wrmsr (MSR_IA32_MCx_CTL(i), 0xffffffff, 0xffffffff);
+            wrmsr (MSR_IA32_MCx_STATUS(i), 0x0, 0x0);
         }
     }
     if (firstbank) /* if cmci enabled, firstbank = 0 */

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Keir Fraser

2010-06-09 12:56 UTC #1 lore raw

Rebase to xen-unstable:21569 or later (available in staging tree) and resend.

-- Keir

Quoted 7 lines · Christoph Egger

Hi!
Attached makes makes xen mce use MSR_IA32_MCx_* macros consequently. No functional changes.
Signed-off-by Christoph Egger <[email protected]>

Christoph Egger

author

2010-06-09 13:34 UTC #2 lore raw

Done. Here we go.

Quoted 12 lines · On Wednesday 09 June 2010 14:56:42 Keir Fraser wrote:

Rebase to xen-unstable:21569 or later (available in staging tree) and resend.
-- Keir
Quoted 6 lines · Christoph Egger
Hi!
Attached makes makes xen mce use MSR_IA32_MCx_* macros consequently. No functional changes.
Signed-off-by Christoph Egger <[email protected]>