Skip to contentSkip to conversation

mce: cleanup msr handling

PATCH New Christoph Egger 1 participant 1 message Jun 11, 2010

lore
Share & tools
lore

Christoph Egger

author
#0 lore raw

PATCH 1/1 mce: cleanup msr handling

Hi!

Attached patch cleans up mce msr-handling. This patch is extracted from the big msr cleanup patch.

Signed-off-by Christoph Egger <[email protected]>
Signature · 6 lines
---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach b. Muenchen
Geschaeftsfuehrer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632
xen/arch/x86/cpu/mcheck/amd_f10.c +3 -3
diff -r 886494c9fda4 xen/arch/x86/cpu/mcheck/amd_f10.c
@@ -81,9 +81,9 @@ amd_f10_handler(struct mc_info *mi, uint
 	mc_ext->mc_msr[1].reg = MSR_F10_MC4_MISC2;
 	mc_ext->mc_msr[2].reg = MSR_F10_MC4_MISC3;
 
-	mca_rdmsrl(MSR_F10_MC4_MISC1, mc_ext->mc_msr[0].value);
-	mca_rdmsrl(MSR_F10_MC4_MISC2, mc_ext->mc_msr[1].value);
-	mca_rdmsrl(MSR_F10_MC4_MISC3, mc_ext->mc_msr[2].value);
+	mc_ext->mc_msr[0].value = mca_rdmsr(MSR_F10_MC4_MISC1);
+	mc_ext->mc_msr[1].value = mca_rdmsr(MSR_F10_MC4_MISC2);
+	mc_ext->mc_msr[2].value = mca_rdmsr(MSR_F10_MC4_MISC3);
 
 	return mc_ext;
 }
xen/arch/x86/cpu/mcheck/amd_nonfatal.c +2 -2
diff -r 886494c9fda4 xen/arch/x86/cpu/mcheck/amd_nonfatal.c
@@ -144,7 +144,7 @@ static void mce_amd_work_fn(void *data)
 		uint64_t value;
 		uint32_t counter;
 
-		mca_rdmsrl(MSR_IA32_MC4_MISC, value);
+		value = mca_rdmsr(MSR_IA32_MC4_MISC);
 		/* Only the error counter field is of interest
 		 * Bit field is described in AMD K8 BKDG chapter 6.4.5.5
 		 */

@@ -169,7 +169,7 @@ static void mce_amd_work_fn(void *data)
 			value &= ~(0x60FFF00000000ULL);
 			/* Counter enable */
 			value |= (1ULL << 51);
-			mca_wrmsrl(MSR_IA32_MC4_MISC, value);
+			mca_wrmsr(MSR_IA32_MC4_MISC, value);
 			wmb();
 		}
 	}
xen/arch/x86/cpu/mcheck/mce.c +12 -12
diff -r 886494c9fda4 xen/arch/x86/cpu/mcheck/mce.c
@@ -164,7 +164,7 @@ static struct mcinfo_bank *mca_init_bank
     }
 
     memset(mib, 0, sizeof (struct mcinfo_bank));
-    mca_rdmsrl(MSR_IA32_MCx_STATUS(bank), mib->mc_status);
+    mib->mc_status = mca_rdmsr(MSR_IA32_MCx_STATUS(bank));
 
     mib->common.type = MC_TYPE_BANK;
     mib->common.size = sizeof (struct mcinfo_bank);

@@ -172,11 +172,11 @@ static struct mcinfo_bank *mca_init_bank
 
     addr = misc = 0;
     if (mib->mc_status & MCi_STATUS_MISCV)
-        mca_rdmsrl(MSR_IA32_MCx_MISC(bank), mib->mc_misc);
+        mib->mc_misc = mca_rdmsr(MSR_IA32_MCx_MISC(bank));
 
     if (mib->mc_status & MCi_STATUS_ADDRV)
     {
-        mca_rdmsrl(MSR_IA32_MCx_ADDR(bank), mib->mc_addr);
+        mib->mc_addr = mca_rdmsr(MSR_IA32_MCx_ADDR(bank));
 
         if (mfn_valid(paddr_to_pfn(mib->mc_addr))) {
             struct domain *d;

@@ -189,7 +189,7 @@ static struct mcinfo_bank *mca_init_bank
     }
 
     if (who == MCA_CMCI_HANDLER) {
-        mca_rdmsrl(MSR_IA32_MC0_CTL2 + bank, mib->mc_ctrl2);
+        mib->mc_ctrl2 = mca_rdmsr(MSR_IA32_MC0_CTL2 + bank);
         rdtscll(mib->mc_tsc);
     }
 

@@ -207,7 +207,7 @@ static int mca_init_global(uint32_t flag
     memset(mig, 0, sizeof (struct mcinfo_global));
     mig->common.type = MC_TYPE_GLOBAL;
     mig->common.size = sizeof (struct mcinfo_global);
-    mca_rdmsrl(MSR_IA32_MCG_STATUS, status);
+    status = mca_rdmsr(MSR_IA32_MCG_STATUS);
     mig->mc_gstatus = status;
     mig->mc_domid = mig->mc_vcpuid = -1;
     mig->mc_flags = flags;

@@ -252,7 +252,7 @@ mctelem_cookie_t mcheck_mca_logout(enum 
     int errcnt = 0;
     int i;
 
-    mca_rdmsrl(MSR_IA32_MCG_STATUS, gstatus);
+    gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS);
     switch (who) {
     case MCA_MCE_HANDLER:
     case MCA_MCE_SCAN:

@@ -287,7 +287,7 @@ mctelem_cookie_t mcheck_mca_logout(enum 
         if (!mcabanks_test(i, bankmask))
             continue;
 
-        mca_rdmsrl(MSR_IA32_MCx_STATUS(i), status);
+        status = mca_rdmsr(MSR_IA32_MCx_STATUS(i));
         if (!(status & MCi_STATUS_VAL))
             continue; /* this bank has no valid telemetry */
 

@@ -345,7 +345,7 @@ mctelem_cookie_t mcheck_mca_logout(enum 
         /* By default, need_clear = 1 */
         if (who != MCA_MCE_SCAN && need_clear)
             /* Clear status */
-            mca_wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
+            mca_wrmsr(MSR_IA32_MCx_STATUS(i), 0x0ULL);
         else if ( who == MCA_MCE_SCAN && need_clear)
             mcabanks_set(i, clear_bank);
 

@@ -407,7 +407,7 @@ void mcheck_cmn_handler(struct cpu_user_
 
     /* Read global status;  if it does not indicate machine check
      * in progress then bail as long as we have a valid ip to return to. */
-    mca_rdmsrl(MSR_IA32_MCG_STATUS, gstatus);
+    gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS);
     ripv = ((gstatus & MCG_STATUS_RIPV) != 0);
     if (!(gstatus & MCG_STATUS_MCIP) && ripv) {
         add_taint(TAINT_MACHINE_CHECK); /* questionable */

@@ -426,7 +426,7 @@ void mcheck_cmn_handler(struct cpu_user_
 
     /* Clear MCIP or another #MC will enter shutdown state */
     gstatus &= ~MCG_STATUS_MCIP;
-    mca_wrmsrl(MSR_IA32_MCG_STATUS, gstatus);
+    mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus);
     wmb();
 
     /* If no valid errors and our stack is intact, we're done */

@@ -605,10 +605,10 @@ void mcheck_mca_clearbanks(struct mca_ba
     for (i = 0; i < 32 && i < nr_mce_banks; i++) {
         if (!mcabanks_test(i, bankmask))
             continue;
-        mca_rdmsrl(MSR_IA32_MCx_STATUS(i), status);
+        status = mca_rdmsr(MSR_IA32_MCx_STATUS(i));
         if (!(status & MCi_STATUS_VAL))
             continue;
-        mca_wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
+        mca_wrmsr(MSR_IA32_MCx_STATUS(i), 0x0ULL);
     }
 }
xen/arch/x86/cpu/mcheck/mce.h +8 -5
diff -r 886494c9fda4 xen/arch/x86/cpu/mcheck/mce.h
@@ -83,13 +83,16 @@ extern struct intpose_ent *intpose_looku
     uint64_t *);
 extern void intpose_inval(unsigned int, uint64_t);
 
-#define mca_rdmsrl(msr, var) do { \
-       if (intpose_lookup(smp_processor_id(), msr, &var) == NULL) \
-               rdmsrl(msr, var); \
-} while (0)
+static inline uint64_t mca_rdmsr(unsigned int msr)
+{
+	uint64_t val;
+	if (intpose_lookup(smp_processor_id(), msr, &val) == NULL)
+		rdmsrl(msr, val);
+	return val;
+}
 
 /* Write an MSR, invalidating any interposed value */
-#define        mca_wrmsrl(msr, val) do { \
+#define mca_wrmsr(msr, val) do { \
        intpose_inval(smp_processor_id(), msr); \
        wrmsrl(msr, val); \
 } while (0)
xen/arch/x86/cpu/mcheck/mce_intel.c +3 -3
diff -r 886494c9fda4 xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -339,7 +339,7 @@ static int mce_urgent_action(struct cpu_
     if ( mctc == NULL)
         return 0;
 
-    mca_rdmsrl(MSR_IA32_MCG_STATUS, gstatus);
+    gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS);
     /* Xen is not pre-emptible */
     if ( !(gstatus & MCG_STATUS_RIPV) && !guest_mode(regs))
         return 0;

@@ -819,10 +819,10 @@ static void intel_machine_check(struct c
 
     /* Clear flags after above fatal check */
     mce_barrier_enter(&mce_trap_bar);
-    mca_rdmsrl(MSR_IA32_MCG_STATUS, gstatus);
+    gstatus = mca_rdmsr(MSR_IA32_MCG_STATUS);
     if ((gstatus & MCG_STATUS_MCIP) != 0) {
         mce_printk(MCE_CRITICAL, "MCE: Clear MCIP@ last step");
-        mca_wrmsrl(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP);
+        mca_wrmsr(MSR_IA32_MCG_STATUS, gstatus & ~MCG_STATUS_MCIP);
     }
     mce_barrier_exit(&mce_trap_bar);

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xensource.com/xen-devel