msr cleanup

PATCH New Christoph Egger 1 participant 1 message Jun 11, 2010

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Christoph Egger

author

2010-06-11 15:20 UTC #0 lore raw

PATCH 1/1 msr cleanup

Hi!

This patch cleans up msr-handling through the xen kernel. This is actually what is left and can't be cut further w/o breaking the build.

The patch changes:
rdmsr returns a 64bit value
rdmsrl is no more
wrmsrl is renamed to wrmsr

Signed-off-by Christoph Egger <[email protected]>

Signature · 6 lines

---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach b. Muenchen
Geschaeftsfuehrer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632

# HG changeset patch
# User cegger
# Date 1276269584 -7200
NetBSD development

xen/arch/x86/acpi/cpufreq/cpufreq.c +8 -8

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -137,13 +137,12 @@ struct drv_cmd {
 static void do_drv_read(void *drvcmd)
 {
     struct drv_cmd *cmd;
-    u32 h;
 
     cmd = (struct drv_cmd *)drvcmd;
 
     switch (cmd->type) {
     case SYSTEM_INTEL_MSR_CAPABLE:
-        rdmsr(cmd->addr.msr.reg, cmd->val, h);
+        cmd->val = rdmsr(cmd->addr.msr.reg);
         break;
     case SYSTEM_IO_CAPABLE:
         acpi_os_read_port((acpi_io_address)cmd->addr.io.port,

@@ -157,15 +156,16 @@ static void do_drv_read(void *drvcmd)
 static void do_drv_write(void *drvcmd)
 {
     struct drv_cmd *cmd;
-    u32 lo, hi;
+    uint64_t msr_content;
 
     cmd = (struct drv_cmd *)drvcmd;
 
     switch (cmd->type) {
     case SYSTEM_INTEL_MSR_CAPABLE:
-        rdmsr(cmd->addr.msr.reg, lo, hi);
-        lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE);
-        wrmsr(cmd->addr.msr.reg, lo, hi);
+        msr_content = rdmsr(cmd->addr.msr.reg);
+        msr_content = (msr_content & ~INTEL_MSR_RANGE)
+            | (cmd->val & INTEL_MSR_RANGE);
+        wrmsr(cmd->addr.msr.reg, msr_content);
         break;
     case SYSTEM_IO_CAPABLE:
         acpi_os_write_port((acpi_io_address)cmd->addr.io.port,

@@ -252,8 +252,8 @@ static void read_measured_perf_ctrs(void
 {
     struct perf_pair *readin = _readin;
 
-    rdmsr(MSR_IA32_APERF, readin->aperf.split.lo, readin->aperf.split.hi);
-    rdmsr(MSR_IA32_MPERF, readin->mperf.split.lo, readin->mperf.split.hi);
+    readin->aperf.whole = rdmsr(MSR_IA32_APERF);
+    readin->mperf.whole = rdmsr(MSR_IA32_MPERF);
 }
 
 /*

xen/arch/x86/acpi/cpufreq/powernow.c +10 -8

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/acpi/cpufreq/powernow.c
@@ -77,15 +77,15 @@ static void transition_pstate(void *drvc
     cmd = (struct drv_cmd *) drvcmd;
 
     if (cmd->turbo != CPUFREQ_TURBO_UNSUPPORTED) {
-        u32 lo, hi;
-        rdmsr(MSR_K8_HWCR, lo, hi);
+        uint64_t msr_content;
+        msr_content = rdmsr(MSR_K8_HWCR);
         if (cmd->turbo == CPUFREQ_TURBO_ENABLED)
-            lo &= ~MSR_HWCR_CPBDIS_MASK;
+            msr_content &= ~MSR_HWCR_CPBDIS_MASK;
         else
-            lo |= MSR_HWCR_CPBDIS_MASK; 
-        wrmsr(MSR_K8_HWCR, lo, hi);
+            msr_content |= MSR_HWCR_CPBDIS_MASK; 
+        wrmsr(MSR_K8_HWCR, msr_content);
     }
-    wrmsr(MSR_PSTATE_CTRL, cmd->val, 0);
+    wrmsr(MSR_PSTATE_CTRL, cmd->val);
 }
 
 static int powernow_cpufreq_target(struct cpufreq_policy *policy,

@@ -194,7 +194,8 @@ static int powernow_cpufreq_cpu_init(str
     struct powernow_cpufreq_data *data;
     unsigned int result = 0;
     struct processor_performance *perf;
-    u32 max_hw_pstate, hi = 0, lo = 0;
+    u32 max_hw_pstate, hi;
+    uint64_t msr_content;
     struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
 
     data = xmalloc(struct powernow_cpufreq_data);

@@ -226,7 +227,8 @@ static int powernow_cpufreq_cpu_init(str
         result = -ENODEV;
         goto err_unreg;
     }
-    rdmsr(MSR_PSTATE_CUR_LIMIT, hi, lo);
+    msr_content = rdmsr(MSR_PSTATE_CUR_LIMIT);
+    hi = (uint32_t)(msr_content >> 32);
     max_hw_pstate = (hi & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT;
 
     if (perf->control_register.space_id != perf->status_register.space_id) {

xen/arch/x86/acpi/suspend.c +13 ~~-14~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/acpi/suspend.c
@@ -25,12 +25,12 @@ void save_rest_processor_state(void)
         unlazy_fpu(current);
 
 #if defined(CONFIG_X86_64)
-    rdmsrl(MSR_CSTAR, saved_cstar);
-    rdmsrl(MSR_LSTAR, saved_lstar);
+    saved_cstar = rdmsr(MSR_CSTAR);
+    saved_lstar = rdmsr(MSR_LSTAR);
     if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
     {
-        rdmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
-        rdmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
+        saved_sysenter_esp = rdmsr(MSR_IA32_SYSENTER_ESP);
+        saved_sysenter_eip = rdmsr(MSR_IA32_SYSENTER_EIP);
     }
 #endif
 }

@@ -43,24 +43,23 @@ void restore_rest_processor_state(void)
 
 #if defined(CONFIG_X86_64)
     /* Recover syscall MSRs */
-    wrmsrl(MSR_LSTAR, saved_lstar);
-    wrmsrl(MSR_CSTAR, saved_cstar);
-    wrmsr(MSR_STAR, 0, (FLAT_RING3_CS32<<16) | __HYPERVISOR_CS);
+    wrmsr(MSR_LSTAR, saved_lstar);
+    wrmsr(MSR_CSTAR, saved_cstar);
+    wrmsr(MSR_STAR, ( (uint64_t)((FLAT_RING3_CS32<<16) | __HYPERVISOR_CS) << 32) );
     wrmsr(MSR_SYSCALL_MASK,
           X86_EFLAGS_VM|X86_EFLAGS_RF|X86_EFLAGS_NT|
-          X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_TF,
-          0U);
+          X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_TF);
 
     if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
     {
         /* Recover sysenter MSRs */
-        wrmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
-        wrmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
-        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
+        wrmsr(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
+        wrmsr(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
+        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS);
     }
 #else /* !defined(CONFIG_X86_64) */
     if ( supervisor_mode_kernel && cpu_has_sep )
-        wrmsr(MSR_IA32_SYSENTER_ESP, &this_cpu(init_tss).esp1, 0);
+        wrmsr(MSR_IA32_SYSENTER_ESP, this_cpu(init_tss).esp1);
 #endif
 
     /* Maybe load the debug registers. */

@@ -79,7 +78,7 @@ void restore_rest_processor_state(void)
     stts();
 
     if (cpu_has_pat)
-        wrmsrl(MSR_IA32_CR_PAT, host_pat);
+        wrmsr(MSR_IA32_CR_PAT, host_pat);
 
     mtrr_bp_restore();
 }

xen/arch/x86/apic.c +25 ~~-23~~

98 lines not on this page · raw message

xen/arch/x86/cpu/amd.c +40 ~~-30~~

139 lines not on this page · raw message

xen/arch/x86/cpu/centaur.c +12 ~~-11~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/centaur.c
@@ -17,7 +17,7 @@
 
 static void __init init_c3(struct cpuinfo_x86 *c)
 {
-	u32  lo, hi;
+	uint32_t msr_content;
 
 	/* Test for Centaur Extended Feature Flags presence */
 	if (cpuid_eax(0xC0000000) >= 0xC0000001) {

@@ -25,17 +25,17 @@ static void __init init_c3(struct cpuinf
 
 		/* enable ACE unit, if present and disabled */
 		if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
-			rdmsr (MSR_VIA_FCR, lo, hi);
-			lo |= ACE_FCR;		/* enable ACE unit */
-			wrmsr (MSR_VIA_FCR, lo, hi);
+			msr_content = rdmsr(MSR_VIA_FCR);
+			msr_content |= ACE_FCR;		/* enable ACE unit */
+			wrmsr(MSR_VIA_FCR, msr_content);
 			printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");
 		}
 
 		/* enable RNG unit, if present and disabled */
 		if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
-			rdmsr (MSR_VIA_RNG, lo, hi);
-			lo |= RNG_ENABLE;	/* enable RNG unit */
-			wrmsr (MSR_VIA_RNG, lo, hi);
+			msr_content = rdmsr (MSR_VIA_RNG);
+			msr_content |= RNG_ENABLE;	/* enable RNG unit */
+			wrmsr(MSR_VIA_RNG, msr_content);
 			printk(KERN_INFO "CPU: Enabled h/w RNG\n");
 		}

@@ -47,9 +47,9 @@ static void __init init_c3(struct cpuinf
 
 	/* Cyrix III family needs CX8 & PGE explicity enabled. */
 	if (c->x86_model >=6 && c->x86_model <= 9) {
-		rdmsr (MSR_VIA_FCR, lo, hi);
-		lo |= (1<<1 | 1<<7);
-		wrmsr (MSR_VIA_FCR, lo, hi);
+		msr_content = rdmsr (MSR_VIA_FCR);
+		msr_content |= (1<<1 | 1<<7);
+		wrmsr(MSR_VIA_FCR, msr_content);
 		set_bit(X86_FEATURE_CX8, c->x86_capability);
 	}

@@ -71,7 +71,8 @@ static void __init init_centaur(struct c
 		init_c3(c);
 }
 
-static unsigned int centaur_size_cache(struct cpuinfo_x86 * c, unsigned int size)
+static unsigned int
+centaur_size_cache(struct cpuinfo_x86 * c, unsigned int size)
 {
 	/* VIA C3 CPUs (670-68F) need further shifting. */
 	if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))

xen/arch/x86/cpu/common.c +6 -6

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/common.c
@@ -315,10 +315,10 @@ static void __cpuinit squash_the_stupid_
 {
 	if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
 		/* Disable processor serial number */
-		unsigned long lo,hi;
-		rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
-		lo |= 0x200000;
-		wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
+		uint64_t msr_content;
+		msr_content = rdmsr(MSR_IA32_BBL_CR_CTL);
+		msr_content |= 0x200000;
+		wrmsr(MSR_IA32_BBL_CR_CTL,msr_content);
 		printk(KERN_NOTICE "CPU serial number disabled.\n");
 		clear_bit(X86_FEATURE_PN, c->x86_capability);

@@ -595,7 +595,7 @@ void __cpuinit cpu_init(void)
 		printk("Initializing CPU#%d\n", cpu);
 
 	if (cpu_has_pat)
-		wrmsrl(MSR_IA32_CR_PAT, host_pat);
+		wrmsr(MSR_IA32_CR_PAT, host_pat);
 
 	/* Install correct page table. */
 	write_ptbase(current);

@@ -614,7 +614,7 @@ void __cpuinit cpu_init(void)
 	t->ss0  = __HYPERVISOR_DS;
 	t->esp0 = get_stack_bottom();
 	if ( supervisor_mode_kernel && cpu_has_sep )
-		wrmsr(MSR_IA32_SYSENTER_ESP, &t->esp1, 0);
+		wrmsr(MSR_IA32_SYSENTER_ESP, t->esp1);
 #elif defined(CONFIG_X86_64)
 	/* Bottom-of-stack must be 16-byte aligned! */
 	BUG_ON((get_stack_bottom() & 15) != 0);

xen/arch/x86/cpu/intel.c +11 ~~-14~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/intel.c
@@ -46,6 +46,7 @@ struct movsl_mask movsl_mask __read_most
 static void __devinit set_cpuidmask(struct cpuinfo_x86 *c)
 {
 	unsigned int model = c->x86_model;
+	uint64_t msr_content;
 
 	if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx | 
 	      opt_cpuid_mask_ext_ecx | opt_cpuid_mask_ext_edx))

@@ -54,10 +55,10 @@ static void __devinit set_cpuidmask(stru
 	if (c->x86 != 0x6)	/* Only family 6 supports this feature  */
 		return;
 
+	msr_content = (opt_cpuid_mask_ecx ? : ~0u)
+		| (uint64_t)(opt_cpuid_mask_edx ? : ~0u) << 32;
 	if ((model == 0x1d) || ((model == 0x17) && (c->x86_mask >= 4))) {
-		wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
-		      opt_cpuid_mask_ecx ? : ~0u,
-		      opt_cpuid_mask_edx ? : ~0u);
+		wrmsr(MSR_IA32_CPUID_FEATURE_MASK1, msr_content);
 	}
 /* 
  * CPU supports this feature if the processor signature meets the following:

@@ -71,12 +72,8 @@ static void __devinit set_cpuidmask(stru
 		 || model == 0x2c 
 		 || model == 0x2e 
 		 || model == 0x2f) {
-		wrmsr(MSR_IA32_CPUID1_FEATURE_MASK,
-		      opt_cpuid_mask_ecx ? : ~0u,
-		      opt_cpuid_mask_edx ? : ~0u);
-		wrmsr(MSR_IA32_CPUID80000001_FEATURE_MASK,
-		      opt_cpuid_mask_ext_ecx ? : ~0u,
-		      opt_cpuid_mask_ext_edx ? : ~0u);
+		wrmsr(MSR_IA32_CPUID1_FEATURE_MASK, msr_content);
+		wrmsr(MSR_IA32_CPUID80000001_FEATURE_MASK, msr_content);
 	}
 	else {
 		printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",

@@ -100,15 +97,15 @@ void __devinit early_intel_workaround(st
  */
 static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
 {
-	unsigned long lo, hi;
+	uint64_t msr_content;
 
 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
-		rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
-		if ((lo & (1<<9)) == 0) {
+		msr_content = rdmsr(MSR_IA32_MISC_ENABLE);
+		if ((msr_content & (1<<9)) == 0) {
 			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
-			lo |= (1<<9);	/* Disable hw prefetching */
-			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
+			msr_content |= (1<<9);	/* Disable hw prefetching */
+			wrmsr (MSR_IA32_MISC_ENABLE, msr_content);
 		}
 	}
 }

xen/arch/x86/cpu/mcheck/amd_k8.c +2 -2

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mcheck/amd_k8.c
@@ -90,8 +90,8 @@ enum mcheck_type amd_k8_mcheck_init(stru
 			mcequirk_amd_apply(quirkflag);
 		} else {
 			/* Enable error reporting of all errors */
-			wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL);
-			wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
+			wrmsr(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL);
+			wrmsr(MSR_IA32_MCx_STATUS(i), 0x0ULL);
 			break;
 		}
 	}

xen/arch/x86/cpu/mcheck/amd_nonfatal.c +2 -2

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mcheck/amd_nonfatal.c
@@ -212,7 +212,7 @@ void amd_nonfatal_mcheck_init(struct cpu
 
 		/* hw threshold registers present */
 		hw_threshold = 1;
-		rdmsrl(MSR_IA32_MC4_MISC, value);
+		value = rdmsr(MSR_IA32_MC4_MISC);
 
 		if (value & (1ULL << 61)) { /* Locked bit */
 			/* Locked by BIOS. Not available for use */

@@ -233,7 +233,7 @@ void amd_nonfatal_mcheck_init(struct cpu
 			value &= ~(0x60FFF00000000ULL);
 			/* Counter enable */
 			value |= (1ULL << 51);
-			wrmsrl(MSR_IA32_MC4_MISC, value);
+			wrmsr(MSR_IA32_MC4_MISC, value);
 			/* serialize */
 			wmb();
 			printk(XENLOG_INFO "MCA: Use hw thresholding to adjust polling frequency\n");

xen/arch/x86/cpu/mcheck/k7.c +24 ~~-24~~

79 lines not on this page · raw message

xen/arch/x86/cpu/mcheck/mce.c +11 ~~-13~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mcheck/mce.c
@@ -723,22 +723,20 @@ int set_poll_bankmask(struct cpuinfo_x86
 /* The perbank ctl/status init is platform specific because of AMD's quirk */
 int mca_cap_init(void)
 {
-    u32 l, h;
-    u64 value;
+    uint64_t value;
 
-    rdmsr(MSR_IA32_MCG_CAP, l, h);
-    value = ((u64)h << 32) | l;
+    value = rdmsr(MSR_IA32_MCG_CAP);
 
-    if (l & MCG_CTL_P) /* Control register present ? */
-        wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+    if (value & MCG_CTL_P) /* Control register present ? */
+        wrmsr(MSR_IA32_MCG_CTL, 0xffffffffffffffffULL);
 
-    if (nr_mce_banks &&  (l & MCG_CAP_COUNT) != nr_mce_banks)
+    if (nr_mce_banks && (value & MCG_CAP_COUNT) != nr_mce_banks)
     {
         dprintk(XENLOG_WARNING, "Different bank number on cpu %x\n",
                 smp_processor_id());
         return -ENODEV;
     }
-    nr_mce_banks = l & MCG_CAP_COUNT;
+    nr_mce_banks = value & MCG_CAP_COUNT;
 
     /* mcabanks_alloc depends on nr_mcebanks */
     if (!mca_allbanks)

@@ -964,7 +962,7 @@ static void do_mc_get_cpu_info(void *v)
      */
     xcp->mc_nmsrvals = __MC_NMSRS;
     xcp->mc_msrvalues[0].reg = MSR_IA32_MCG_CAP;
-    rdmsrl(MSR_IA32_MCG_CAP, xcp->mc_msrvalues[0].value);
+    xcp->mc_msrvalues[0].value = rdmsr(MSR_IA32_MCG_CAP);
 
     if (c->cpuid_level >= 1) {
         cpuid(1, &junk, &ebx, &junk, &junk);

@@ -1148,11 +1146,11 @@ static uint64_t x86_mc_hwcr_wren(void)
 {
     uint64_t old;
 
-    rdmsrl(MSR_K8_HWCR, old);
+    old = rdmsr(MSR_K8_HWCR);
 
     if (!(old & K8_HWCR_MCi_STATUS_WREN)) {
         uint64_t new = old | K8_HWCR_MCi_STATUS_WREN;
-        wrmsrl(MSR_K8_HWCR, new);
+        wrmsr(MSR_K8_HWCR, new);
     }
 
     return old;

@@ -1161,7 +1159,7 @@ static uint64_t x86_mc_hwcr_wren(void)
 static void x86_mc_hwcr_wren_restore(uint64_t hwcr)
 {
     if (!(hwcr & K8_HWCR_MCi_STATUS_WREN))
-        wrmsrl(MSR_K8_HWCR, hwcr);
+        wrmsr(MSR_K8_HWCR, hwcr);
 }
 
 static void x86_mc_msrinject(void *data)

@@ -1192,7 +1190,7 @@ static void x86_mc_msrinject(void *data)
         if (intpose)
             intpose_add(mci->mcinj_cpunr, msr->reg, msr->value);
         else
-            wrmsrl(msr->reg, msr->value);
+            wrmsr(msr->reg, msr->value);
     }
 
     if (mci->mcinj_flags & _MC_MSRINJ_F_REQ_HWCR_WREN)

xen/arch/x86/cpu/mcheck/mce.h +2 -2

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mcheck/mce.h
@@ -87,14 +87,14 @@ static inline uint64_t mca_rdmsr(unsigne
 {
 	uint64_t val;
 	if (intpose_lookup(smp_processor_id(), msr, &val) == NULL)
-		rdmsrl(msr, val);
+               return rdmsr(msr);
 	return val;
 }
 
 /* Write an MSR, invalidating any interposed value */
 #define mca_wrmsr(msr, val) do { \
        intpose_inval(smp_processor_id(), msr); \
-       wrmsrl(msr, val); \
+       wrmsr(msr, val); \
 } while (0)

xen/arch/x86/cpu/mcheck/mce_amd_quirks.c +5 -4

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mcheck/mce_amd_quirks.c
@@ -17,8 +17,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#include <asm-x86/msr.h>
-#include <asm-x86/processor.h>
+#include <xen/types.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
 
 #include "mce_quirks.h"

@@ -64,8 +65,8 @@ int mcequirk_amd_apply(enum mcequirk_amd
 		 * TBL walk error reporting, which trips off incorrectly
 		 * with AGP GART & 3ware & Cerberus.
 		 */
-		wrmsrl(MSR_IA32_MC4_CTL, ~(1ULL << 10));
-		wrmsrl(MSR_IA32_MC4_STATUS, 0ULL);
+		wrmsr(MSR_IA32_MC4_CTL, ~(1ULL << 10));
+		wrmsr(MSR_IA32_MC4_STATUS, 0ULL);
 		break;
 	}

xen/arch/x86/cpu/mcheck/mce_intel.c +38 ~~-37~~

175 lines not on this page · raw message

xen/arch/x86/cpu/mcheck/vmce.c +3 -5

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mcheck/vmce.c
@@ -439,7 +439,6 @@ int vmce_domain_inject(
 
 int vmce_init(struct cpuinfo_x86 *c)
 {
-    u32 l, h;
     u64 value;
     int i;

@@ -454,14 +453,13 @@ int vmce_init(struct cpuinfo_x86 *c)
         /* Don't care banks before firstbank */
         memset(h_mci_ctrl, 0xff, sizeof(h_mci_ctrl));
         for (i = firstbank; i < nr_mce_banks; i++)
-            rdmsrl(MSR_IA32_MCx_CTL(i), h_mci_ctrl[i]);
+            h_mci_ctrl[i] = rdmsr(MSR_IA32_MCx_CTL(i));
     }
 
     if (g_mcg_cap & MCG_CTL_P)
-        rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl);
+        h_mcg_ctl = rdmsr(MSR_IA32_MCG_CTL);
 
-    rdmsr(MSR_IA32_MCG_CAP, l, h);
-    value = ((u64)h << 32) | l;
+    value = rdmsr(MSR_IA32_MCG_CAP);
     /* For Guest vMCE usage */
     g_mcg_cap = value & ~MCG_CMCI_P;

xen/arch/x86/cpu/mtrr/amd.c +14 ~~-11~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mtrr/amd.c
@@ -9,20 +9,20 @@ static void
 amd_get_mtrr(unsigned int reg, unsigned long *base,
 	     unsigned long *size, mtrr_type * type)
 {
-	unsigned long low, high;
+	uint64_t msr_content;
 
-	rdmsr(MSR_K6_UWCCR, low, high);
+	msr_content = rdmsr(MSR_K6_UWCCR);
 	/*  Upper dword is region 1, lower is region 0  */
 	if (reg == 1)
-		low = high;
+		msr_content = (uint32_t)(msr_content >> 32);
 	/*  The base masks off on the right alignment  */
-	*base = (low & 0xFFFE0000) >> PAGE_SHIFT;
+	*base = (msr_content & 0xFFFE0000) >> PAGE_SHIFT;
 	*type = 0;
-	if (low & 1)
+	if (msr_content & 1)
 		*type = MTRR_TYPE_UNCACHABLE;
-	if (low & 2)
+	if (msr_content & 2)
 		*type = MTRR_TYPE_WRCOMB;
-	if (!(low & 3)) {
+	if (!(msr_content & 3)) {
 		*size = 0;
 		return;
 	}

@@ -41,8 +41,8 @@ amd_get_mtrr(unsigned int reg, unsigned 
 	 *  +1              000 0000 0000 0100
 	 *  *128K   ...
 	 */
-	low = (~low) & 0x1FFFC;
-	*size = (low + 4) << (15 - PAGE_SHIFT);
+	msr_content = (~msr_content) & 0x1FFFC;
+	*size = (msr_content + 4) << (15 - PAGE_SHIFT);
 	return;
 }

@@ -59,11 +59,14 @@ static void amd_set_mtrr(unsigned int re
 */
 {
 	u32 regs[2];
+	uint64_t msr_content;
 
 	/*
 	 *  Low is MTRR0 , High MTRR 1
 	 */
-	rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
+	msr_content = rdmsr(MSR_K6_UWCCR);
+	regs[0] = (uint32_t)msr_content;
+	regs[1] = (uint32_t)(msr_content >> 32);
 	/*
 	 *  Blank to disable
 	 */

@@ -85,7 +88,7 @@ static void amd_set_mtrr(unsigned int re
 	 *  disable local interrupts, write back the cache, set the mtrr
 	 */
 	wbinvd();
-	wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
+	wrmsr(MSR_K6_UWCCR, regs[0] | (uint64_t)(regs[1]) << 32);
 }
 
 static int amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)

xen/arch/x86/cpu/mtrr/generic.c +44 ~~-27~~

162 lines not on this page · raw message

xen/arch/x86/cpu/mtrr/main.c +2 -2

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mtrr/main.c
@@ -101,10 +101,10 @@ static int have_wrcomb(void)
 /*  This function returns the number of variable MTRRs  */
 static void __init set_num_var_ranges(void)
 {
-	unsigned long config = 0, dummy;
+	unsigned long config = 0;
 
 	if (use_intel()) {
-		rdmsr(MTRRcap_MSR, config, dummy);
+		config = rdmsr(MTRRcap_MSR);
 	} else if (is_cpu(AMD))
 		config = 2;
 	else if (is_cpu(CYRIX) || is_cpu(CENTAUR))

xen/arch/x86/cpu/mtrr/state.c +3 -3

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/mtrr/state.c
@@ -29,10 +29,10 @@ void set_mtrr_prepare_save(struct set_mt
 		write_cr0(cr0);
 		wbinvd();
 
-		if (use_intel()) {
+		if (use_intel())
 			/*  Save MTRR state */
-			rdmsrl(MTRRdefType_MSR, ctxt->deftype);
-		} else
+			ctxt->deftype = rdmsr(MTRRdefType_MSR);
+		else
 			/* Cyrix ARRs - everything else were excluded at the top */
 			ctxt->ccr3 = getCx86(CX86_CCR3);
 	}

xen/arch/x86/cpu/transmeta.c +5 -4

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/cpu/transmeta.c
@@ -7,7 +7,8 @@
 
 static void __init init_transmeta(struct cpuinfo_x86 *c)
 {
-	unsigned int cap_mask, uk, max, dummy;
+	uint64_t cap_mask;
+	unsigned int max, dummy;
 	unsigned int cms_rev1, cms_rev2;
 	unsigned int cpu_rev, cpu_freq, cpu_flags, new_cpu_rev;
 	char cpu_info[65];

@@ -68,10 +69,10 @@ static void __init init_transmeta(struct
 	}
 
 	/* Unhide possibly hidden capability flags */
-	rdmsr(0x80860004, cap_mask, uk);
-	wrmsr(0x80860004, ~0, uk);
+	cap_mask = rdmsr(0x80860004);
+	wrmsr(0x80860004, ~0);
 	c->x86_capability[0] = cpuid_edx(0x00000001);
-	wrmsr(0x80860004, cap_mask, uk);
+	wrmsr(0x80860004, cap_mask);
 	
 	/* If we can run i686 user-space code, call us an i686 */
 #define USER686 (X86_FEATURE_TSC|X86_FEATURE_CX8|X86_FEATURE_CMOV)

xen/arch/x86/domain.c +3 -9

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/domain.c
@@ -1088,21 +1088,15 @@ static void load_segments(struct vcpu *n
     {
         /* This can only be non-zero if selector is NULL. */
         if ( nctxt->fs_base )
-            wrmsr(MSR_FS_BASE,
-                  nctxt->fs_base,
-                  nctxt->fs_base>>32);
+            wrmsr(MSR_FS_BASE, nctxt->fs_base);
 
         /* Most kernels have non-zero GS base, so don't bother testing. */
         /* (This is also a serialising instruction, avoiding AMD erratum #88.) */
-        wrmsr(MSR_SHADOW_GS_BASE,
-              nctxt->gs_base_kernel,
-              nctxt->gs_base_kernel>>32);
+        wrmsr(MSR_SHADOW_GS_BASE, nctxt->gs_base_kernel);
 
         /* This can only be non-zero if selector is NULL. */
         if ( nctxt->gs_base_user )
-            wrmsr(MSR_GS_BASE,
-                  nctxt->gs_base_user,
-                  nctxt->gs_base_user>>32);
+            wrmsr(MSR_GS_BASE, nctxt->gs_base_user);
 
         /* If in kernel mode then switch the GS bases around. */
         if ( (n->arch.flags & TF_kernel_mode) )

xen/arch/x86/e820.c +4 -4

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/e820.c
@@ -457,8 +457,8 @@ static uint64_t mtrr_top_of_ram(void)
     }
     addr_mask = ((1ull << phys_bits) - 1) & ~((1ull << 12) - 1);
 
-    rdmsrl(MSR_MTRRcap, mtrr_cap);
-    rdmsrl(MSR_MTRRdefType, mtrr_def);
+    mtrr_cap = rdmsr(MSR_MTRRcap);
+    mtrr_def = rdmsr(MSR_MTRRdefType);
 
     if ( e820_verbose )
         printk(" MTRR cap: %"PRIx64" type: %"PRIx64"\n", mtrr_cap, mtrr_def);

@@ -474,8 +474,8 @@ static uint64_t mtrr_top_of_ram(void)
     top = 0;
     for ( i = 0; i < (uint8_t)mtrr_cap; i++ )
     {
-        rdmsrl(MSR_MTRRphysBase(i), base);
-        rdmsrl(MSR_MTRRphysMask(i), mask);
+        base = rdmsr(MSR_MTRRphysBase(i));
+        mask = rdmsr(MSR_MTRRphysMask(i) );
 
         if ( e820_verbose )
             printk(" MTRR[%d]: base %"PRIx64" mask %"PRIx64"\n",

xen/arch/x86/hvm/hvm.c +1 -1

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/hvm/hvm.c
@@ -2127,7 +2127,7 @@ int hvm_msr_write_intercept(unsigned int
         v->arch.hvm_vcpu.msr_tsc_aux = (uint32_t)msr_content;
         if ( cpu_has_rdtscp
              && (v->domain->arch.tsc_mode != TSC_MODE_PVRDTSCP) )
-            wrmsrl(MSR_TSC_AUX, (uint32_t)msr_content);
+            wrmsr(MSR_TSC_AUX, (uint32_t)msr_content);
         break;
 
     case MSR_IA32_APICBASE:

xen/arch/x86/hvm/svm/svm.c +9 ~~-12~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/hvm/svm/svm.c
@@ -684,7 +684,7 @@ static void svm_ctxt_switch_to(struct vc
     vpmu_load(v);
 
     if ( cpu_has_rdtscp )
-        wrmsrl(MSR_TSC_AUX, hvm_msr_tsc_aux(v));
+        wrmsr(MSR_TSC_AUX, hvm_msr_tsc_aux(v));
 }
 
 static void svm_do_resume(struct vcpu *v)

@@ -861,13 +861,12 @@ static void svm_init_erratum_383(struct 
 
 static int svm_cpu_up(void)
 {
-    u32 phys_hsa_lo, phys_hsa_hi;   
     uint64_t phys_hsa, msr_content;
     int rc, cpu = smp_processor_id();
     struct cpuinfo_x86 *c = &cpu_data[cpu];
  
     /* Check whether SVM feature is disabled in BIOS */
-    rdmsrl(MSR_K8_VM_CR, msr_content);
+    msr_content = rdmsr(MSR_K8_VM_CR);
     if ( msr_content & K8_VMCR_SVME_DISABLE )
     {
         printk("CPU%d: AMD SVM Extension is disabled in BIOS.\n", cpu);

@@ -881,9 +880,7 @@ static int svm_cpu_up(void)
 
     /* Initialize the HSA for this core. */
     phys_hsa = (u64)virt_to_maddr(hsa[cpu]);
-    phys_hsa_lo = (u32)phys_hsa;
-    phys_hsa_hi = (u32)(phys_hsa >> 32);    
-    wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa_lo, phys_hsa_hi);
+    wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa);
 
     /* check for erratum 383 */
     svm_init_erratum_383(c);

@@ -898,12 +895,12 @@ static int svm_cpu_up(void)
      */
     msr_content = read_efer();
     if ( wrmsr_safe(MSR_EFER, msr_content | EFER_LMSLE) == 0 )
-        rdmsrl(MSR_EFER, msr_content);
+        msr_content = rdmsr(MSR_EFER);
     if ( msr_content & EFER_LMSLE )
     {
         if ( c == &boot_cpu_data )
             cpu_has_lmsl = 1;
-        wrmsrl(MSR_EFER, msr_content ^ EFER_LMSLE);
+        wrmsr(MSR_EFER, msr_content ^ EFER_LMSLE);
     }
     else
     {

@@ -1300,7 +1297,7 @@ static int svm_is_erratum_383(struct cpu
     if ( !amd_erratum383_found )
         return 0;
 
-    rdmsrl(MSR_IA32_MC0_STATUS, msr_content);
+    msr_content = rdmsr(MSR_IA32_MC0_STATUS);
     /* Bit 62 may or may not be set for this mce */
     msr_content &= ~(1ULL << 62);

@@ -1309,10 +1306,10 @@ static int svm_is_erratum_383(struct cpu
     
     /* Clear MCi_STATUS registers */
     for (i = 0; i < nr_mce_banks; i++)
-        wrmsrl(MSR_IA32_MCx_STATUS(i), 0ULL);
+        wrmsr(MSR_IA32_MCx_STATUS(i), 0ULL);
     
-    rdmsrl(MSR_IA32_MCG_STATUS, msr_content);
-    wrmsrl(MSR_IA32_MCG_STATUS, msr_content & ~(1ULL << 2));
+    msr_content = rdmsr(MSR_IA32_MCG_STATUS);
+    wrmsr(MSR_IA32_MCG_STATUS, msr_content & ~(1ULL << 2));
 
     /* flush TLB */
     flush_tlb_mask(&v->domain->domain_dirty_cpumask);

xen/arch/x86/hvm/svm/vpmu.c +6 -6

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/hvm/svm/vpmu.c
@@ -110,11 +110,11 @@ static inline void context_restore(struc
     struct amd_vpmu_context *ctxt = vpmu->context;
 
     for ( i = 0; i < NUM_COUNTERS; i++ )
-        wrmsrl(AMD_F10H_CTRLS[i], ctxt->ctrls[i]);
+        wrmsr(AMD_F10H_CTRLS[i], ctxt->ctrls[i]);
 
     for ( i = 0; i < NUM_COUNTERS; i++ )
     {
-        wrmsrl(AMD_F10H_COUNTERS[i], ctxt->counters[i]);
+        wrmsr(AMD_F10H_COUNTERS[i], ctxt->counters[i]);
 
         /* Force an interrupt to allow guest reset the counter,
         if the value is positive */

@@ -147,10 +147,10 @@ static inline void context_save(struct v
     struct amd_vpmu_context *ctxt = vpmu->context;
 
     for ( i = 0; i < NUM_COUNTERS; i++ )
-        rdmsrl(AMD_F10H_COUNTERS[i], ctxt->counters[i]);
+        ctxt->counters[i] = rdmsr(AMD_F10H_COUNTERS[i]);
 
     for ( i = 0; i < NUM_COUNTERS; i++ )
-        rdmsrl(AMD_F10H_CTRLS[i], ctxt->ctrls[i]);
+        ctxt->ctrls[i] = rdmsr(AMD_F10H_CTRLS[i]);
 }
 
 static void amd_vpmu_save(struct vcpu *v)

@@ -220,13 +220,13 @@ static int amd_vpmu_do_wrmsr(unsigned in
     context_update(msr, msr_content);
 
     /* Write to hw counters */
-    wrmsrl(msr, msr_content);
+    wrmsr(msr, msr_content);
     return 1;
 }
 
 static int amd_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
 {
-    rdmsrl(msr, *msr_content);
+    *msr_content = rdmsr(msr);
     return 1;
 }

xen/arch/x86/hvm/vmx/vmcs.c +29 ~~-20~~

135 lines not on this page · raw message

xen/arch/x86/hvm/vmx/vmx.c +10 ~~-10~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/hvm/vmx/vmx.c
@@ -153,13 +153,13 @@ void vmx_save_host_msrs(void)
     int i;
 
     for ( i = 0; i < MSR_INDEX_SIZE; i++ )
-        rdmsrl(msr_index[i], host_msr_state->msrs[i]);
+        host_msr_state->msrs[i] = rdmsr(msr_index[i]);
 }
 
 #define WRITE_MSR(address)                                              \
         guest_msr_state->msrs[VMX_INDEX_MSR_ ## address] = msr_content; \
         set_bit(VMX_INDEX_MSR_ ## address, &guest_msr_state->flags);    \
-        wrmsrl(MSR_ ## address, msr_content);                           \
+        wrmsr(MSR_ ## address, msr_content);                           \
         set_bit(VMX_INDEX_MSR_ ## address, &host_msr_state->flags);     \
         break

@@ -184,7 +184,7 @@ long_mode_do_msr_read(unsigned int msr, 
         break;
 
     case MSR_SHADOW_GS_BASE:
-        rdmsrl(MSR_SHADOW_GS_BASE, *msr_content);
+        *msr_content = rdmsr(MSR_SHADOW_GS_BASE);
         break;
 
     case MSR_STAR:

@@ -239,7 +239,7 @@ long_mode_do_msr_write(unsigned int msr,
         else if ( msr == MSR_GS_BASE )
             __vmwrite(GUEST_GS_BASE, msr_content);
         else
-            wrmsrl(MSR_SHADOW_GS_BASE, msr_content);
+            wrmsr(MSR_SHADOW_GS_BASE, msr_content);
 
         break;

@@ -287,7 +287,7 @@ static void vmx_restore_host_msrs(void)
     while ( host_msr_state->flags )
     {
         i = find_first_set_bit(host_msr_state->flags);
-        wrmsrl(msr_index[i], host_msr_state->msrs[i]);
+        wrmsr(msr_index[i], host_msr_state->msrs[i]);
         clear_bit(i, &host_msr_state->flags);
     }
 }

@@ -298,7 +298,7 @@ static void vmx_save_guest_msrs(struct v
      * We cannot cache SHADOW_GS_BASE while the VCPU runs, as it can
      * be updated at any time via SWAPGS, which we cannot trap.
      */
-    rdmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.shadow_gs);
+    v->arch.hvm_vmx.shadow_gs = rdmsr(MSR_SHADOW_GS_BASE);
 }
 
 static void vmx_restore_guest_msrs(struct vcpu *v)

@@ -310,7 +310,7 @@ static void vmx_restore_guest_msrs(struc
     guest_msr_state = &v->arch.hvm_vmx.msr_state;
     host_msr_state = &this_cpu(host_msr_state);
 
-    wrmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.shadow_gs);
+    wrmsr(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.shadow_gs);
 
     guest_flags = guest_msr_state->flags;

@@ -322,7 +322,7 @@ static void vmx_restore_guest_msrs(struc
                     "restore guest's index %d msr %x with value %lx",
                     i, msr_index[i], guest_msr_state->msrs[i]);
         set_bit(i, &host_msr_state->flags);
-        wrmsrl(msr_index[i], guest_msr_state->msrs[i]);
+        wrmsr(msr_index[i], guest_msr_state->msrs[i]);
         clear_bit(i, &guest_flags);
     }

@@ -336,7 +336,7 @@ static void vmx_restore_guest_msrs(struc
     }
 
     if ( cpu_has_rdtscp )
-        wrmsrl(MSR_TSC_AUX, hvm_msr_tsc_aux(v));
+        wrmsr(MSR_TSC_AUX, hvm_msr_tsc_aux(v));
 }
 
 #else  /* __i386__ */

@@ -1831,7 +1831,7 @@ static int vmx_msr_read_intercept(unsign
     case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_PROCBASED_CTLS2:
         goto gp_fault;
     case MSR_IA32_MISC_ENABLE:
-        rdmsrl(MSR_IA32_MISC_ENABLE, *msr_content);
+        *msr_content = rdmsr(MSR_IA32_MISC_ENABLE);
         /* Debug Trace Store is not supported. */
         *msr_content |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL |
                        MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;

xen/arch/x86/hvm/vmx/vpmu_core2.c +13 ~~-13~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -189,9 +189,9 @@ static inline void __core2_vpmu_save(str
     struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
 
     for ( i = 0; i < core2_counters.num; i++ )
-        rdmsrl(core2_counters.msr[i], core2_vpmu_cxt->counters[i]);
+        core2_vpmu_cxt->counters[i] = rdmsr(core2_counters.msr[i]);
     for ( i = 0; i < core2_get_pmc_count(); i++ )
-        rdmsrl(MSR_IA32_PERFCTR0+i, core2_vpmu_cxt->arch_msr_pair[i].counter);
+        core2_vpmu_cxt->arch_msr_pair[i].counter = rdmsr(MSR_IA32_PERFCTR0+i);
     core2_vpmu_cxt->hw_lapic_lvtpc = apic_read(APIC_LVTPC);
     apic_write(APIC_LVTPC, PMU_APIC_VECTOR | APIC_LVT_MASKED);
 }

@@ -220,14 +220,14 @@ static inline void __core2_vpmu_load(str
     struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
 
     for ( i = 0; i < core2_counters.num; i++ )
-        wrmsrl(core2_counters.msr[i], core2_vpmu_cxt->counters[i]);
+        wrmsr(core2_counters.msr[i], core2_vpmu_cxt->counters[i]);
     for ( i = 0; i < core2_get_pmc_count(); i++ )
-        wrmsrl(MSR_IA32_PERFCTR0+i, core2_vpmu_cxt->arch_msr_pair[i].counter);
+        wrmsr(MSR_IA32_PERFCTR0+i, core2_vpmu_cxt->arch_msr_pair[i].counter);
 
     for ( i = 0; i < core2_ctrls.num; i++ )
-        wrmsrl(core2_ctrls.msr[i], core2_vpmu_cxt->ctrls[i]);
+        wrmsr(core2_ctrls.msr[i], core2_vpmu_cxt->ctrls[i]);
     for ( i = 0; i < core2_get_pmc_count(); i++ )
-        wrmsrl(MSR_P6_EVNTSEL0+i, core2_vpmu_cxt->arch_msr_pair[i].control);
+        wrmsr(MSR_P6_EVNTSEL0+i, core2_vpmu_cxt->arch_msr_pair[i].control);
 
     apic_write_around(APIC_LVTPC, core2_vpmu_cxt->hw_lapic_lvtpc);
 }

@@ -253,7 +253,7 @@ static int core2_vpmu_alloc_resource(str
     if ( !acquire_pmu_ownership(PMU_OWNER_HVM) )
         return 0;
 
-    wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+    wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
     if ( vmx_add_host_load_msr(MSR_CORE_PERF_GLOBAL_CTRL) )
         return 0;

@@ -364,13 +364,13 @@ static int core2_vpmu_do_wrmsr(unsigned 
         global_ctrl = msr_content;
         for ( i = 0; i < core2_get_pmc_count(); i++ )
         {
-            rdmsrl(MSR_P6_EVNTSEL0+i, non_global_ctrl);
+            non_global_ctrl = rdmsr(MSR_P6_EVNTSEL0+i);
             core2_vpmu_cxt->pmu_enable->arch_pmc_enable[i] =
                     global_ctrl & (non_global_ctrl >> 22) & 1;
             global_ctrl >>= 1;
         }
 
-        rdmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, non_global_ctrl);
+        non_global_ctrl = rdmsr(MSR_CORE_PERF_FIXED_CTR_CTRL);
         global_ctrl = msr_content >> 32;
         for ( i = 0; i < 3; i++ )
         {

@@ -443,7 +443,7 @@ static int core2_vpmu_do_wrmsr(unsigned 
         if (inject_gp)
             vmx_inject_hw_exception(TRAP_gp_fault, 0);
         else
-            wrmsrl(msr, msr_content);
+            wrmsr(msr, msr_content);
     }
     else
         vmx_write_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);

@@ -474,7 +474,7 @@ static int core2_vpmu_do_rdmsr(unsigned 
         vmx_read_guest_msr(MSR_CORE_PERF_GLOBAL_CTRL, msr_content);
         break;
     default:
-        rdmsrl(msr, *msr_content);
+        *msr_content = rdmsr(msr);
     }
 
     return 1;

@@ -490,12 +490,12 @@ static int core2_vpmu_do_interrupt(struc
     struct core2_vpmu_context *core2_vpmu_cxt = vpmu->context;
     struct vlapic *vlapic = vcpu_vlapic(v);
 
-    rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, msr_content);
+    msr_content = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
     if ( !msr_content )
         return 0;
     core2_vpmu_cxt->global_ovf_status |= msr_content;
     msr_content = 0xC000000700000000 | ((1 << core2_get_pmc_count()) - 1);
-    wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
+    wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
 
     apic_write_around(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);

xen/arch/x86/microcode_amd.c +4 -5

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/microcode_amd.c
@@ -47,7 +47,6 @@ struct equiv_cpu_entry *equiv_cpu_table;
 static int collect_cpu_info(int cpu, struct cpu_signature *csig)
 {
     struct cpuinfo_x86 *c = &cpu_data[cpu];
-    uint32_t dummy;
 
     memset(csig, 0, sizeof(*csig));

@@ -58,7 +57,7 @@ static int collect_cpu_info(int cpu, str
         return -EINVAL;
     }
 
-    rdmsr(MSR_AMD_PATCHLEVEL, csig->rev, dummy);
+    csig->rev = rdmsr(MSR_AMD_PATCHLEVEL);
 
     printk(KERN_INFO "microcode: collect_cpu_info: patch_id=0x%x\n",
            csig->rev);

@@ -126,7 +125,7 @@ static int apply_microcode(int cpu)
 {
     unsigned long flags;
     struct ucode_cpu_info *uci = &per_cpu(ucode_cpu_info, cpu);
-    uint32_t rev, dummy;
+    uint32_t rev;
     struct microcode_amd *mc_amd = uci->mc.mc_amd;
 
     /* We should bind the task to the CPU */

@@ -137,10 +136,10 @@ static int apply_microcode(int cpu)
 
     spin_lock_irqsave(&microcode_update_lock, flags);
 
-    wrmsrl(MSR_AMD_PATCHLOADER, (unsigned long)&mc_amd->hdr.data_code);
+    wrmsr(MSR_AMD_PATCHLOADER, (unsigned long)&mc_amd->hdr.data_code);
 
     /* get patch id after patching */
-    rdmsr(MSR_AMD_PATCHLEVEL, rev, dummy);
+    rev = rdmsr(MSR_AMD_PATCHLEVEL);
 
     spin_unlock_irqrestore(&microcode_update_lock, flags);

xen/arch/x86/microcode_intel.c +11 -8

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/microcode_intel.c
@@ -62,6 +62,7 @@ static DEFINE_SPINLOCK(microcode_update_
 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
 {
     struct cpuinfo_x86 *c = &cpu_data[cpu_num];
+    uint64_t msr_content;
     unsigned int val[2];
 
     BUG_ON(cpu_num != smp_processor_id());

@@ -81,15 +82,17 @@ static int collect_cpu_info(int cpu_num,
     if ( (c->x86_model >= 5) || (c->x86 > 6) )
     {
         /* get processor flags from MSR 0x17 */
-        rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
+        msr_content = rdmsr(MSR_IA32_PLATFORM_ID);
+        val[1] = msr_content >> 32;
         csig->pf = 1 << ((val[1] >> 18) & 7);
     }
 
-    wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+    wrmsr(MSR_IA32_UCODE_REV, 0);
     /* see notes above for revision 1.07.  Apparent chip bug */
     sync_core();
     /* get the current revision from MSR 0x8B */
-    rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
+    msr_content = rdmsr(MSR_IA32_UCODE_REV);
+    csig->rev = (uint32_t)msr_content;
     pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",
              csig->sig, csig->pf, csig->rev);

@@ -250,6 +253,7 @@ static int apply_microcode(int cpu)
 {
     unsigned long flags;
     unsigned int val[2];
+    uint64_t msr_content;
     int cpu_num = raw_smp_processor_id();
     struct ucode_cpu_info *uci = &per_cpu(ucode_cpu_info, cpu_num);

@@ -263,16 +267,15 @@ static int apply_microcode(int cpu)
     spin_lock_irqsave(&microcode_update_lock, flags);
 
     /* write microcode via MSR 0x79 */
-    wrmsr(MSR_IA32_UCODE_WRITE,
-          (unsigned long) uci->mc.mc_intel->bits,
-          (unsigned long) uci->mc.mc_intel->bits >> 16 >> 16);
-    wrmsr(MSR_IA32_UCODE_REV, 0, 0);
+    wrmsr(MSR_IA32_UCODE_WRITE, (unsigned long) uci->mc.mc_intel->bits);
+    wrmsr(MSR_IA32_UCODE_REV, 0);
 
     /* see notes above for revision 1.07.  Apparent chip bug */
     sync_core();
 
     /* get the current revision from MSR 0x8B */
-    rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
+    msr_content = rdmsr(MSR_IA32_UCODE_REV);
+    val[1] = msr_content >> 32;
 
     spin_unlock_irqrestore(&microcode_update_lock, flags);
     if ( val[1] != uci->mc.mc_intel->hdr.rev )

xen/arch/x86/nmi.c +16 ~~-16~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/nmi.c
@@ -147,7 +147,7 @@ static void disable_lapic_nmi_watchdog(v
         return;
     switch (boot_cpu_data.x86_vendor) {
     case X86_VENDOR_AMD:
-        wrmsr(MSR_K7_EVNTSEL0, 0, 0);
+        wrmsr(MSR_K7_EVNTSEL0, 0);
         break;
     case X86_VENDOR_INTEL:
         switch (boot_cpu_data.x86) {

@@ -155,14 +155,14 @@ static void disable_lapic_nmi_watchdog(v
             if (boot_cpu_data.x86_model > 0xd)
                 break;
 
-            wrmsr(MSR_P6_EVNTSEL0, 0, 0);
+            wrmsr(MSR_P6_EVNTSEL0, 0);
             break;
         case 15:
             if (boot_cpu_data.x86_model > 0x4)
                 break;
 
-            wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
-            wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
+            wrmsr(MSR_P4_IQ_CCCR0, 0);
+            wrmsr(MSR_P4_CRU_ESCR0, 0);
             break;
         }
         break;

@@ -219,7 +219,7 @@ static void __pminit clear_msr_range(uns
     unsigned int i;
 
     for (i = 0; i < n; i++)
-        wrmsr(base+i, 0, 0);
+        wrmsr(base+i, 0);
 }
 
 static inline void write_watchdog_counter(const char *descr)

@@ -229,7 +229,7 @@ static inline void write_watchdog_counte
     do_div(count, nmi_hz);
     if(descr)
         Dprintk("setting %s to -0x%"PRIx64"\n", descr, count);
-    wrmsrl(nmi_perfctr_msr, 0 - count);
+    wrmsr(nmi_perfctr_msr, 0 - count);
 }
 
 static void __pminit setup_k7_watchdog(void)

@@ -246,11 +246,11 @@ static void __pminit setup_k7_watchdog(v
         | K7_EVNTSEL_USR
         | K7_NMI_EVENT;
 
-    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
+    wrmsr(MSR_K7_EVNTSEL0, evntsel);
     write_watchdog_counter("K7_PERFCTR0");
     apic_write(APIC_LVTPC, APIC_DM_NMI);
     evntsel |= K7_EVNTSEL_ENABLE;
-    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
+    wrmsr(MSR_K7_EVNTSEL0, evntsel);
 }
 
 static void __pminit setup_p6_watchdog(unsigned counter)

@@ -267,18 +267,18 @@ static void __pminit setup_p6_watchdog(u
         | P6_EVNTSEL_USR
         | counter;
 
-    wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
+    wrmsr(MSR_P6_EVNTSEL0, evntsel);
     write_watchdog_counter("P6_PERFCTR0");
     apic_write(APIC_LVTPC, APIC_DM_NMI);
     evntsel |= P6_EVNTSEL0_ENABLE;
-    wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
+    wrmsr(MSR_P6_EVNTSEL0, evntsel);
 }
 
 static int __pminit setup_p4_watchdog(void)
 {
-    unsigned int misc_enable, dummy;
+    uint64_t misc_enable;
 
-    rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
+    misc_enable = rdmsr(MSR_IA32_MISC_ENABLE);
     if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
         return 0;

@@ -304,11 +304,11 @@ static int __pminit setup_p4_watchdog(vo
     clear_msr_range(MSR_P4_BPU_CCCR0, 18);
     clear_msr_range(MSR_P4_BPU_PERFCTR0, 18);
         
-    wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
-    wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
+    wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0);
+    wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE);
     write_watchdog_counter("P4_IQ_COUNTER0");
     apic_write(APIC_LVTPC, APIC_DM_NMI);
-    wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
+    wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val);
     return 1;
 }

@@ -442,7 +442,7 @@ void nmi_watchdog_tick(struct cpu_user_r
              * - LVTPC is masked on interrupt and must be
              *   unmasked by the LVTPC handler.
              */
-            wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
+            wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val);
             apic_write(APIC_LVTPC, APIC_DM_NMI);
         }
         else if ( nmi_perfctr_msr == MSR_P6_PERFCTR0 )

xen/arch/x86/oprofile/nmi_int.c +4 ~~-12~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/oprofile/nmi_int.c
@@ -104,15 +104,11 @@ static void nmi_cpu_save_registers(struc
 	unsigned int i;
 
 	for (i = 0; i < nr_ctrs; ++i) {
-		rdmsr(counters[i].addr,
-			counters[i].saved.low,
-			counters[i].saved.high);
+		counters[i].value = rdmsr(counters[i].addr);
 	}
  
 	for (i = 0; i < nr_ctrls; ++i) {
-		rdmsr(controls[i].addr,
-			controls[i].saved.low,
-			controls[i].saved.high);
+		controls[i].value = rdmsr(controls[i].addr);
 	}
 }

@@ -222,15 +218,11 @@ static void nmi_restore_registers(struct
 	unsigned int i;
 
 	for (i = 0; i < nr_ctrls; ++i) {
-		wrmsr(controls[i].addr,
-			controls[i].saved.low,
-			controls[i].saved.high);
+		wrmsr(controls[i].addr, controls[i].value);
 	}
  
 	for (i = 0; i < nr_ctrs; ++i) {
-		wrmsr(counters[i].addr,
-			counters[i].saved.low,
-			counters[i].saved.high);
+		wrmsr(counters[i].addr, counters[i].value);
 	}
 }

xen/arch/x86/oprofile/op_model_athlon.c +31 ~~-28~~

120 lines not on this page · raw message

xen/arch/x86/oprofile/op_model_p4.c +50 ~~-48~~

223 lines not on this page · raw message

xen/arch/x86/oprofile/op_model_ppro.c +28 ~~-28~~

121 lines not on this page · raw message

xen/arch/x86/oprofile/op_x86_model.h +1 -6

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/oprofile/op_x86_model.h
@@ -11,14 +11,9 @@
 #ifndef OP_X86_MODEL_H
 #define OP_X86_MODEL_H
 
-struct op_saved_msr {
-	unsigned int high;
-	unsigned int low;
-};
-
 struct op_msr {
 	unsigned long addr;
-	struct op_saved_msr saved;
+	uint64_t value;
 };
 
 struct op_msrs {

xen/arch/x86/setup.c +1 -1

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/setup.c
@@ -418,7 +418,7 @@ void __init __start_xen(unsigned long mb
     idle_vcpu[0] = current;
     set_processor_id(0); /* needed early, for smp_processor_id() */
     if ( cpu_has_efer )
-        rdmsrl(MSR_EFER, this_cpu(efer));
+        this_cpu(efer) = rdmsr(MSR_EFER);
     asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
 
     smp_prepare_boot_cpu();

xen/arch/x86/smpboot.c +1 -1

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/smpboot.c
@@ -314,7 +314,7 @@ void start_secondary(void *unused)
     set_current(idle_vcpu[cpu]);
     this_cpu(curr_vcpu) = idle_vcpu[cpu];
     if ( cpu_has_efer )
-        rdmsrl(MSR_EFER, this_cpu(efer));
+        this_cpu(efer) = rdmsr(MSR_EFER);
     asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
 
     /*

xen/arch/x86/traps.c +2 -5

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/traps.c
@@ -3123,18 +3123,15 @@ u64 read_efer(void)
 void write_efer(u64 val)
 {
     this_cpu(efer) = val;
-    wrmsrl(MSR_EFER, val);
+    wrmsr(MSR_EFER, val);
 }
 
 static void ler_enable(void)
 {
-    u64 debugctl;
-    
     if ( !this_cpu(ler_msr) )
         return;
 
-    rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
-    wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl | 1);
+    wrmsr(MSR_IA32_DEBUGCTLMSR, rdmsr(MSR_IA32_DEBUGCTLMSR) | 1);
 }
 
 asmlinkage void do_debug(struct cpu_user_regs *regs)

xen/arch/x86/x86_32/traps.c +7 -6

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/x86_32/traps.c
@@ -124,10 +124,11 @@ void show_registers(struct cpu_user_regs
 
     if ( this_cpu(ler_msr) && !guest_mode(regs) )
     {
-        u32 from, to, hi;
-        rdmsr(this_cpu(ler_msr), from, hi);
-        rdmsr(this_cpu(ler_msr) + 1, to, hi);
-        printk("ler: %08x -> %08x\n", from, to);
+        uint64_t msr_content_from, msr_content_to;
+        msr_content_from = rdmsr(this_cpu(ler_msr));
+        msr_content_to = rdmsr(this_cpu(ler_msr) + 1);
+        printk("ler: %16"PRIx64" -> %16"PRIx64"\n",
+            msr_content_from, msr_content_to);
     }
 }

@@ -403,8 +404,8 @@ static void do_update_sysenter(void *inf
 {
     xen_callback_t *address = info;
 
-    wrmsr(MSR_IA32_SYSENTER_CS, address->cs, 0);
-    wrmsr(MSR_IA32_SYSENTER_EIP, address->eip, 0);
+    wrmsr(MSR_IA32_SYSENTER_CS, address->cs);
+    wrmsr(MSR_IA32_SYSENTER_EIP, address->eip);
 }
 #endif

xen/arch/x86/x86_64/traps.c +9 ~~-10~~

diff -r ab385be9e2ef -r 70357840696c xen/arch/x86/x86_64/traps.c
@@ -138,8 +138,8 @@ void show_registers(struct cpu_user_regs
     if ( this_cpu(ler_msr) && !guest_mode(regs) )
     {
         u64 from, to;
-        rdmsrl(this_cpu(ler_msr), from);
-        rdmsrl(this_cpu(ler_msr) + 1, to);
+        from = rdmsr(this_cpu(ler_msr));
+        to = rdmsr(this_cpu(ler_msr) + 1);
         printk("ler: %016lx -> %016lx\n", from, to);
     }
 }

@@ -395,28 +395,27 @@ void __devinit subarch_percpu_traps_init
 
     /* Trampoline for SYSCALL entry from long mode. */
     stack = &stack[IST_MAX * PAGE_SIZE]; /* Skip the IST stacks. */
-    wrmsrl(MSR_LSTAR, (unsigned long)stack);
+    wrmsr(MSR_LSTAR, (unsigned long)stack);
     stack += write_stack_trampoline(stack, stack_bottom, FLAT_KERNEL_CS64);
 
     if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
     {
         /* SYSENTER entry. */
-        wrmsrl(MSR_IA32_SYSENTER_ESP, (unsigned long)stack_bottom);
-        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
-        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
+        wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)stack_bottom);
+        wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
+        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS);
     }
 
     /* Trampoline for SYSCALL entry from compatibility mode. */
     stack = (char *)L1_CACHE_ALIGN((unsigned long)stack);
-    wrmsrl(MSR_CSTAR, (unsigned long)stack);
+    wrmsr(MSR_CSTAR, (unsigned long)stack);
     stack += write_stack_trampoline(stack, stack_bottom, FLAT_USER_CS32);
 
     /* Common SYSCALL parameters. */
-    wrmsr(MSR_STAR, 0, (FLAT_RING3_CS32<<16) | __HYPERVISOR_CS);
+    wrmsr(MSR_STAR, ((uint64_t)(FLAT_RING3_CS32<<16) | __HYPERVISOR_CS) << 32);
     wrmsr(MSR_SYSCALL_MASK,
           X86_EFLAGS_VM|X86_EFLAGS_RF|X86_EFLAGS_NT|
-          X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_TF,
-          0U);
+          X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_TF);
 }
 
 void init_int80_direct_trap(struct vcpu *v)

xen/include/asm-x86/apic.h +5 ~~-10~~

diff -r ab385be9e2ef -r 70357840696c xen/include/asm-x86/apic.h
@@ -82,30 +82,25 @@ static __inline void apic_wrmsr(unsigned
         reg == APIC_LVR)
         return;
 
-    wrmsrl(APIC_MSR_BASE + (reg >> 4), msr_content);
+    wrmsr(APIC_MSR_BASE + (reg >> 4), msr_content);
 }
 
 static __inline uint64_t apic_rdmsr(unsigned long reg)
 {
-    uint64_t msr_content;
-
     if (reg == APIC_DFR)
         return -1u;
-
-    rdmsrl(APIC_MSR_BASE + (reg >> 4), msr_content);
-    return msr_content;
+    return rdmsr(APIC_MSR_BASE + (reg >> 4));
 }
 
-static __inline void apic_write(unsigned long reg, u32 v)
+static __inline void apic_write(unsigned long reg, uint32_t v)
 {
-
     if ( x2apic_enabled )
         apic_wrmsr(reg, v);
     else
         apic_mem_write(reg, v);
 }
 
-static __inline void apic_write_atomic(unsigned long reg, u32 v)
+static __inline void apic_write_atomic(unsigned long reg, uint32_t v)
 {
     if ( x2apic_enabled )
         apic_wrmsr(reg, v);

@@ -113,7 +108,7 @@ static __inline void apic_write_atomic(u
         apic_mem_write_atomic(reg, v);
 }
 
-static __inline u32 apic_read(unsigned long reg)
+static __inline uint32_t apic_read(unsigned long reg)
 {
     if ( x2apic_enabled )
         return apic_rdmsr(reg);

xen/include/asm-x86/msr.h +17 ~~-22~~

diff -r ab385be9e2ef -r 70357840696c xen/include/asm-x86/msr.h
@@ -9,29 +9,24 @@
 #include <xen/percpu.h>
 #include <xen/errno.h>
 
-#define rdmsr(msr,val1,val2) \
-     __asm__ __volatile__("rdmsr" \
-			  : "=a" (val1), "=d" (val2) \
-			  : "c" (msr))
+static inline uint64_t rdmsr(unsigned int msr)
+{
+	unsigned long a__, b__;
 
-#define rdmsrl(msr,val) do { unsigned long a__,b__; \
-       __asm__ __volatile__("rdmsr" \
-			    : "=a" (a__), "=d" (b__) \
-			    : "c" (msr)); \
-       val = a__ | ((u64)b__<<32); \
-} while(0);
+	__asm__ __volatile__("rdmsr"
+			  : "=a" (a__), "=d" (b__)
+			  : "c" (msr));
+	return a__ | ((uint64_t)b__<<32);
+}
 
-#define wrmsr(msr,val1,val2) \
-     __asm__ __volatile__("wrmsr" \
+static inline void wrmsr(unsigned int msr, uint64_t val)
+{
+        uint32_t lo, hi;
+        lo = (uint32_t)val;
+        hi = (uint32_t)(val >> 32);
+	__asm__ __volatile__("wrmsr" \
 			  : /* no outputs */ \
-			  : "c" (msr), "a" (val1), "d" (val2))
-
-static inline void wrmsrl(unsigned int msr, __u64 val)
-{
-        __u32 lo, hi;
-        lo = (__u32)val;
-        hi = (__u32)(val >> 32);
-        wrmsr(msr, lo, hi);
+			  : "c" (msr), "a" (lo), "d" (hi));
 }
 
 /* rdmsr with exception handling */

@@ -91,9 +86,9 @@ static inline int wrmsr_safe(unsigned in
 } while(0)
 #endif
 
-#define write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
+#define write_tsc(val) wrmsr(MSR_IA32_TSC, val)
 
-#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
+#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val))
 
 #define rdpmc(counter,low,high) \
      __asm__ __volatile__("rdpmc" \

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