intel_mid: Add Mrst & Mfld DMA Drivers

From: Vinod Koul <[email protected]>

This patch add DMA drivers for DMA controllers in Langwell chipset of Intel(R) Moorestown platform and DMA controllers in Penwell of Intel(R) Medfield platfrom

This patch adds support for Moorestown DMAC1 and DMAC2 controllers. It also add support for Medfiled GP DMA and DMAC1 controllers. These controllers supports memory to peripheral and peripheral to memory transfers
It support only single block transfers
This driver is based on Kernel DMA engine
Anyone who wishes to use this controller should use DMA engine APIs

This controller exposes DMA_SLAVE capabilities and notifies the client drivers of DMA transaction completion

Signed-off-by Vinod Koul <[email protected]>

Signed-off-by Alan Cox <[email protected]>

---

++ *    midc_do_start           begin a transaction
++ *    @midc: channel
++ *    @first: first descriptor of series

++ *
++ * Load a transaction into the engine. This must be called with dwc->lock
++ * held and bh disabled.
++ */
+static void midc_dostart(struct intel_mid_dma_chan *midc, struct intel_mid_dma_desc

drivers/dma/intel_mid_dma.c new file +8 -0

+/*check desc, mark as complete when tx is complete*/
+static void
+midc_scan_descriptors(struct middma_device *mid, struct intel_mid_dma_chan *midc)
+{
+       struct intel_mid_dma_desc *desc = NULL, *_desc = NULL;
+/*     u32 status_xfer; */
+
+       dma_dbg("called \n");

+               if (desc->status == DMA_IN_PROGRESS)  {
+                       desc->status = DMA_SUCCESS;
+                       midc_descriptor_complete(midc, desc);
+               }
+       }
+       return;

(quoted diff) +2 -0

+}
+

+struct intel_mid_dma_slave {
+       enum dma_data_direction         dirn;
+       enum intel_mid_dma_width        src_width; /*width of DMA src txn*/
+       enum intel_mid_dma_width        dst_width; /*width of DMA dst txn*/
+       enum intel_mid_dma_hs_mode      hs_mode;  /*handshaking*/
+       enum intel_mid_dma_mode         cfg_mode; /*mode configuration*/
+       enum intel_mid_dma_msize        src_msize; /*size if src burst*/
+       enum intel_mid_dma_msize        dst_msize; /*size of dst burst*/
+       dma_async_tx_callback           callback; /*callback function*/
+       void                            *callback_param; /*param for callback*/

[..]

Quoted 8 lines

++ *    midc_do_start           begin a transaction
++ *    @midc: channel
++ *    @first: first descriptor of series

++ *
++ * Load a transaction into the engine. This must be called with dwc->lock
++ * held and bh disabled.
++ */
+static void midc_dostart(struct intel_mid_dma_chan *midc, struct

intel_mid_dma_desc

(nit) The function name does not match the kernel doc, and I don't know if those extra "+" characters will throw off the kernel-doc scripts. They also show up on midc_put_desc, but not midc_scan_descriptors.

Quoted 4 lines

+       /*tx is complete*/
+       list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
+               if (desc == NULL)
+                       continue;

How do we ever get desc == NULL at this point?

[..]

drivers/dma/intel_mid_dma_regs.h line 257

Quoted 8 lines

drivers/dma/intel_mid_dma_regs.h new file +8 -0

+#define _dma_printk(level, format, arg...)  \
+       printk(level "LNW_DMA: %s %d " format, __func__, __LINE__, ## arg)
+
+#ifdef CONFIG_LNW_DMA_DEBUG
+#define dma_dbg(format, arg...) _dma_printk(KERN_DEBUG, "DBG " format , ## arg)
+#else
+#define dma_dbg(format, arg...) do {} while (0);
+#endif

This makes us lose compile coverage of the debug statements so they bitrot until someone needs to debug a problem.

Any advantage to having a default callback in the slave configuration?
Why not let the client specify the callback on each operation, is it
a callback that the client does not know about?