x86 cpufreq: use rdmsrl/wrmsrl
PATCH 1/1 x86 cpufreq: use rdmsrl/wrmsrl
Hi!
Attached patch makes x86 cpufreq code using rdmsrl/wrmsrl and cleans up surrounding code.
Signed-off-by Christoph Egger <[email protected]>
Signature · 6 lines
---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632
xen/arch/x86/acpi/cpufreq/cpufreq.c +8 -8
@@ -137,13 +137,12 @@ struct drv_cmd {static void do_drv_read (void *drvcmd) {struct drv_cmd *cmd; -u32 h; cmd = (struct drv_cmd *)drvcmd;switch (cmd->type) {case SYSTEM_INTEL_MSR_CAPABLE : -rdmsr (cmd->addr.msr.reg, cmd->val, h); +rdmsrl (cmd->addr.msr.reg, cmd->val);break ;case SYSTEM_IO_CAPABLE : acpi_os_read_port((acpi_io_address)cmd->addr.io.port,
@@ -157,15 +156,16 @@ static void do_drv_read(void *drvcmd)static void do_drv_write (void *drvcmd) {struct drv_cmd *cmd; -u32 lo, hi; +uint64_t msr_content; cmd = (struct drv_cmd *)drvcmd;switch (cmd->type) {case SYSTEM_INTEL_MSR_CAPABLE : -rdmsr (cmd->addr.msr.reg, lo, hi); - lo = (lo & ~INTEL_MSR_RANGE ) | (cmd->val &INTEL_MSR_RANGE ); -wrmsr (cmd->addr.msr.reg, lo, hi); +rdmsrl (cmd->addr.msr.reg, msr_content); + msr_content = (msr_content & ~INTEL_MSR_RANGE ) + | (cmd->val &INTEL_MSR_RANGE ); +wrmsrl (cmd->addr.msr.reg, msr_content);break ;case SYSTEM_IO_CAPABLE : acpi_os_write_port((acpi_io_address)cmd->addr.io.port,
@@ -252,8 +252,8 @@ static void read_measured_perf_ctrs(void {struct perf_pair *readin = _readin; -rdmsr (MSR_IA32_APERF , readin->aperf.split.lo, readin->aperf.split.hi); -rdmsr (MSR_IA32_MPERF , readin->mperf.split.lo, readin->mperf.split.hi); +rdmsrl (MSR_IA32_APERF , readin->aperf.whole); +rdmsrl (MSR_IA32_MPERF , readin->mperf.whole); }/*
xen/arch/x86/acpi/cpufreq/powernow.c +11 -10
@@ -44,7 +44,7 @@#define USE_HW_PSTATE 0x00000080#define HW_PSTATE_MASK 0x00000007#define HW_PSTATE_VALID_MASK 0x80000000 -#define HW_PSTATE_MAX_MASK 0x000000f0 +#define HW_PSTATE_MAX_MASK 0x000000f000000000ULL#define HW_PSTATE_MAX_SHIFT 4#define MSR_PSTATE_DEF_BASE 0xc0010064/* base of Pstate MSRs */ #define MSR_PSTATE_STATUS 0xc0010063/* Pstate Status MSR */
@@ -77,15 +77,15 @@ static void transition_pstate(void *drvc cmd = (struct drv_cmd *) drvcmd;if (cmd->turbo !=CPUFREQ_TURBO_UNSUPPORTED ) { -u32 lo, hi; -rdmsr (MSR_K8_HWCR , lo, hi); +uint64_t msr_content; +rdmsrl (MSR_K8_HWCR , msr_content);if (cmd->turbo ==CPUFREQ_TURBO_ENABLED ) - lo &= ~MSR_HWCR_CPBDIS_MASK ; + msr_content &= ~MSR_HWCR_CPBDIS_MASK ;else - lo |=MSR_HWCR_CPBDIS_MASK ; -wrmsr (MSR_K8_HWCR , lo, hi); + msr_content |=MSR_HWCR_CPBDIS_MASK ; +wrmsrl (MSR_K8_HWCR , msr_content); } -wrmsr (MSR_PSTATE_CTRL , cmd->val,0 ); +wrmsrl (MSR_PSTATE_CTRL , cmd->val); } static int powernow_cpufreq_target(struct cpufreq_policy *policy,
@@ -194,7 +194,8 @@ static int powernow_cpufreq_cpu_init(strstruct powernow_cpufreq_data *data;unsigned int result =0 ;struct processor_performance *perf; -u32 max_hw_pstate, hi =0 , lo =0 ; +u32 max_hw_pstate; +uint64_t msr_content;struct cpuinfo_x86 *c = &cpu_data[policy->cpu]; data = xmalloc(struct powernow_cpufreq_data);
@@ -226,8 +227,8 @@ static int powernow_cpufreq_cpu_init(str result = -ENODEV ; goto err_unreg; } -rdmsr (MSR_PSTATE_CUR_LIMIT , hi, lo); - max_hw_pstate = (hi &HW_PSTATE_MAX_MASK ) >>HW_PSTATE_MAX_SHIFT ; +rdmsrl (MSR_PSTATE_CUR_LIMIT , msr_content); + max_hw_pstate = (msr_content &HW_PSTATE_MAX_MASK ) >>HW_PSTATE_MAX_SHIFT ;if (perf->control_register.space_id != perf->status_register.space_id) { result = -ENODEV ;
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