MIPS: MTX-1: fix PCI on the MeshCube and related boards
PATCH 1/2 MIPS: MTX-1: fix PCI on the MeshCube and related boards
This patch fixes a regression introduced by commit "MIPS: Alchemy: MTX-1: Use linux gpio api." (bb706b28bbd647c2fd7f22d6bf03a18b9552be05) which broke PCI bus operation. The problem is caused by alchemy_gpio2_enable() which resets the GPIO2 block. Two PCI signals (PCI_SERR and PCI_RST) are connected to GPIO2 and they obviously do not to like the reset. Since GPIO2 is correctly initialized by the boot monitor (YAMON) it is not necessary to call this function, so just remove it.
Also replace gpio_set_value() with alchemy_gpio_set_value() to avoid problems in case gpiolib gets initialized after PCI. And since alchemy gpio_set_value() calls au_sync() we don't have to au_sync() again later.
--- arch/mips/alchemy/mtx-1/board_setup.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-)
arch/mips/alchemy/mtx-1/board_setup.c +3 -5
@@ -67,8 +67,6 @@ static void mtx1_power_off(void)void __init board_setup (void ) { -alchemy_gpio2_enable (); -#if defined(CONFIG_USB_OHCI_HCD ) || defined(CONFIG_USB_OHCI_HCD_MODULE )/* Enable USB power switch */ alchemy_gpio_direction_output (204 ,0 );
@@ -117,11 +115,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert)if (assert && devsel !=0 )/* Suppress signal to Cardbus */ -gpio_set_value (1 ,0 );/* set EXT_IO3 OFF */ +alchemy_gpio_set_value (1 ,0 );/* set EXT_IO3 OFF */ else -gpio_set_value (1 ,1 );/* set EXT_IO3 ON */ +alchemy_gpio_set_value (1 ,1 );/* set EXT_IO3 ON */ -au_sync_udelay (1 ); +udelay (1 );return 1 ; }
PATCH 2/2 MIPS: MTX-1: cleanup and comments
Add some comments about mtx1_pci_idsel() and remove a dead block of old code.
--- arch/mips/alchemy/mtx-1/board_setup.c | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-)
arch/mips/alchemy/mtx-1/board_setup.c +4 -8
@@ -105,14 +105,10 @@ void __init board_setup(void)int mtx1_pci_idsel (unsigned int devsel,int assert) { -#define MTX_IDSEL_ONLY_0_AND_3 0 -#if MTX_IDSEL_ONLY_0_AND_3 -if (devsel !=0 && devsel !=3 ) { -printk (KERN_ERR "*** not 0 or 3\n" ); -return 0 ; - } -#endif - +/* This function is only necessary to support a proprietary Cardbus +* adapter on the mtx-1 "singleboard" variant. It triggers a custom +* logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. +*/ if (assert && devsel !=0 )/* Suppress signal to Cardbus */ alchemy_gpio_set_value (1 ,0 );/* set EXT_IO3 OFF */
Re: [PATCH 2/2] MIPS: MTX-1: cleanup and comments
Quoted 4 lines · Bruno Randolf
Add some comments about
mtx1_pci_idsel()and remove a dead block of old code.Signed-off-by Bruno Randolf <[email protected]>
Quoted 27 lines
--- arch/mips/alchemy/mtx-1/board_setup.c | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-)(quoted diff) +0
-0
b/arch/mips/alchemy/mtx-1/board_setup.cindex 52d883d..3cf2fa2 100644arch/mips/alchemy/mtx-1/board_setup.c +4
-8@@ -105,14 +105,10 @@ void __init board_setup(void)int mtx1_pci_idsel (unsigned int devsel,int assert) { -#define MTX_IDSEL_ONLY_0_AND_3 0 -#if MTX_IDSEL_ONLY_0_AND_3 -if (devsel !=0 && devsel !=3 ) { -printk (KERN_ERR "*** not 0 or 3\n" ); -return 0 ; - } -#endif - +/* This function is only necessary to support a proprietary Cardbus +* adapter on the mtx-1 "singleboard" variant. It triggers a custom +* logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals. +*/ if (assert && devsel !=0 )/* Suppress signal to Cardbus */ alchemy_gpio_set_value (1 ,0 );/* set EXT_IO3 OFF */
Re: [PATCH 2/2] MIPS: MTX-1: cleanup and comments
In reply to Bruno RandolfThanks, queued for 2.6.36.
Ralf
Quoted 8 lines · Bruno Randolf
This patch fixes a regression introduced by commit "MIPS: Alchemy: MTX-1:
Use linux gpio api." (bb706b28bbd647c2fd7f22d6bf03a18b9552be05) which broke PCI bus operation. The problem is caused byalchemy_gpio2_enable()which resets the GPIO2 block. Two PCI signals (PCI_SERRandPCI_RST) are connected to GPIO2 and they obviously do not to like the reset. Since GPIO2 is correctly initialized by the boot monitor (YAMON) it is not necessary to call this function, so just remove it.
Quoted 6 lines
Also replace
gpio_set_value()withalchemy_gpio_set_value()to avoid problems in case gpiolib gets initialized after PCI. And since alchemygpio_set_value()callsau_sync()we don't have toau_sync()again later.Signed-off-by Bruno Randolf <[email protected]>
Quoted 31 lines
--- arch/mips/alchemy/mtx-1/board_setup.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-)(quoted diff) +0
-0
b/arch/mips/alchemy/mtx-1/board_setup.cindex a9f0336..52d883d 100644arch/mips/alchemy/mtx-1/board_setup.c +3
-5@@ -67,8 +67,6 @@ static void mtx1_power_off(void)void __init board_setup (void ) { -alchemy_gpio2_enable (); -#if defined(CONFIG_USB_OHCI_HCD ) || defined(CONFIG_USB_OHCI_HCD_MODULE )/* Enable USB power switch */ alchemy_gpio_direction_output (204 ,0 );@@ -117,11 +115,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert)if (assert && devsel !=0 )/* Suppress signal to Cardbus */ -gpio_set_value (1 ,0 );/* set EXT_IO3 OFF */ +alchemy_gpio_set_value (1 ,0 );/* set EXT_IO3 OFF */ else -gpio_set_value (1 ,1 );/* set EXT_IO3 ON */ +alchemy_gpio_set_value (1 ,1 );/* set EXT_IO3 ON */ -au_sync_udelay (1 ); +udelay (1 );return 1 ; }
Ralf Baechle
AppliedQuoted 1 line · Bruno Randolf
Thanks, applied - but stable wasn't on the Cc: list!
Ralf