e1000: allow option to limit number of descriptors down to 48 per ring
Subsystems (2)
PATCH 1/1 e1000: allow option to limit number of descriptors down to 48 per ring
From: Alexander Duyck <[email protected]>
This change makes it possible to limit the number of descriptors down to 48 per ring. The reason for this change is to address a variation on hardware errata 10 for 82546GB in which descriptors will be lost if more than 32 descriptors are fetched and the PCI-X MRBC is 512.
---
drivers/net/e1000/e1000.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
drivers/net/e1000/e1000.h +2 -2
@@ -86,12 +86,12 @@ struct e1000_adapter;/* TX/RX descriptor defines */ #define E1000_DEFAULT_TXD 256#define E1000_MAX_TXD 256 -#define E1000_MIN_TXD 80 +#define E1000_MIN_TXD 48#define E1000_MAX_82544_TXD 4096#define E1000_DEFAULT_RXD 256#define E1000_MAX_RXD 256 -#define E1000_MIN_RXD 80 +#define E1000_MIN_RXD 48#define E1000_MAX_82544_RXD 4096#define E1000_MIN_ITR_USECS 10/* 100000 irq/sec */
From: Jeff Kirsher <[email protected]>
Date: Mon, 19 Jul 2010 16:43:47 -0700
Quoted 10 lines
From: Alexander Duyck <[email protected]>
This change makes it possible to limit the number of descriptors down to 48 per ring. The reason for this change is to address a variation on hardware errata 10 for 82546GB in which descriptors will be lost if more than 32 descriptors are fetched and the PCI-X MRBC is 512.
Signed-off-by Alexander Duyck <[email protected]>Tested-by Emil Tantilov <[email protected]>Signed-off-by Jeff Kirsher <[email protected]>
Applied.
Quoted 25 lines · Jeff Kirsher
From: Alexander Duyck <[email protected]>
This change makes it possible to limit the number of descriptors down to 48 per ring. The reason for this change is to address a variation on hardware errata 10 for 82546GB in which descriptors will be lost if more than 32 descriptors are fetched and the PCI-X MRBC is 512.
Signed-off-by Alexander Duyck <[email protected]>Tested-by Emil Tantilov <[email protected]>Signed-off-by Jeff Kirsher <[email protected]>---
drivers/net/e1000/e1000.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)drivers/net/e1000/e1000.h +0
-1@@ -86,12 +86,12 @@ struct e1000_adapter;/* TX/RX descriptor defines */ #define E1000_DEFAULT_TXD 256#define E1000_MAX_TXD 256 -#define E1000_MIN_TXD 80
drivers/net/e1000/e1000.h struct e1000_adapter; · line 97
Quoted 10 lines
drivers/net/e1000/e1000.h +2
-1+#define E1000_MIN_TXD 48#define E1000_MAX_82544_TXD 4096#define E1000_DEFAULT_RXD 256#define E1000_MAX_RXD 256 -#define E1000_MIN_RXD 80 +#define E1000_MIN_RXD 48#define E1000_MAX_82544_RXD 4096#define E1000_MIN_ITR_USECS 10/* 100000 irq/sec */
So this limit is a pure software one ?
Why not let an admin chose a lower limit if he wants to ?
I am asking because big ring sizes can be a latency source in some workloads.
Thanks
Quoted 11 lines · Eric Dumazet
Quoted 10 lines · Jeff Kirsher
From: Alexander Duyck <[email protected]>
This change makes it possible to limit the number of descriptors down to 48 per ring. The reason for this change is to address a variation on hardware errata 10 for 82546GB in which descriptors will be lost if more than 32 descriptors are fetched and the PCI-X MRBC is 512.
drivers/net/e1000/e1000.h +1
-1-#define E1000_MIN_TXD 80 +#define E1000_MIN_TXD 48#define E1000_MAX_82544_TXD 4096
Quoted 7 lines
drivers/net/e1000/e1000.h struct e1000_adapter; · line 95
Quoted 5 lines
#define
E1000_DEFAULT_RXD256
#defineE1000_MAX_RXD256drivers/net/e1000/e1000.h +1
-1-#define E1000_MIN_RXD 80 +#define E1000_MIN_RXD 48#define E1000_MAX_82544_RXD 4096So this limit is a pure software one ?
Yes, the hardware will work fine (with the exception of some limits when certain performance registers are configured like [TR]XDCTL) all the way down to 1 descriptor, that said, the practical limit is probably more like 8 for RX descriptors, and is 2 * (MAX_SKB_FRAGS + 1) for transmit if TSO is enabled.
if all offloads are disabled you could run with only 8 tx descriptors, and I believe it would work fine.
Quoted 1 line
Why not let an admin chose a lower limit if he wants to ?
I think in this case just to prevent odd interaction bugs with low values (there would have to be several driver changes and the testing work would increase to support very low values)
Quoted 2 lines
I am asking because big ring sizes can be a latency source in some workloads.
yes, if you are trying to pace traffic in software. That said, at least on transmit, most frames exit immediately from the hardware unless some external event like flow control is slowing down transmit.
Jesse