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arm: versatile: enable PCI I/O space

RFC Superseded Arnd Bergmann 3 participants 6 messages Jul 20, 2010 – Jul 21, 2010

Subsystems (5)
Arm (32-bit) Arm sub-architectures Arm/versatile express platform Arm/nomadik/Ux500 architectures +1 more subsystems
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Arnd Bergmann

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#0 lore raw

RFC 1/1 arm: versatile: enable PCI I/O space

I believe I have found out what is actually going on with PCI I/O space mapping on the versatile platform, thanks to Catalin pointing me in the right direction.

It seems that I/O space handling on the versatile platform is currently broken in multiple ways. Most importantly, the ports do not get mapped into the virtual address space at all.

Also, there is some amount of confusion between PCI I/O space and other statically mapped MMIO registers in the platform code:

* The __io_address() macro that is used to access the platform register maps to the same __io macro that gets used for I/O space.

* The IO_SPACE_LIMIT is set to a value that is much larger than the total available space.

* The I/O resource of the PCI bus is set to the physical address of the mapping, which is way outside of the actual I/O space limit as well as the address range that gets decoded by traditional PCI cards.

* No attempt is made to stay outside of the ISA port range that some device drivers try access.

* No resource gets requested as a child of ioport_resource, but an IORESOURCE_IO type mapping gets requested as a child of iomem_resource.

This patch attempts to correct all of the above. This makes it possible to use virtio-pci based virtual devices as well as actual PCI cards including those with legacy ISA port ranges like VGA.

Some of the issues seem to be duplicated on other platforms and if I got it right, we should probably do similar changes there.

Signed-off-by Arnd Bergmann <[email protected]>
arch/arm/mach-versatile/core.c +1 -14
index 3dff864..27051a3 100644
@@ -200,26 +200,13 @@ static struct map_desc versatile_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 		.length		= VERSATILE_PCI_CFG_BASE_SIZE,
 		.type		= MT_DEVICE
-	},
-#if 0
- 	{
+	}, {
 		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE0,
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 		.length		= SZ_16M,
 		.type		= MT_DEVICE
-	}, {
-		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE1,
-		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
-		.length		= SZ_16M,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE2,
-		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
-		.length		= SZ_16M,
-		.type		= MT_DEVICE
 	},
 #endif
-#endif
 };
 
 void __init versatile_map_io(void)
arch/arm/mach-versatile/include/mach/hardware.h +4 -13
index 4f8f99a..9b080ee 100644
@@ -29,25 +29,16 @@
  */
 #define VERSATILE_PCI_VIRT_BASE		(void __iomem *)0xe8000000ul
 #define VERSATILE_PCI_CFG_VIRT_BASE	(void __iomem *)0xe9000000ul
+#define VERSATILE_PCI_VIRT_MEM_BASE0	(void __iomem *)0xeb000000ul
 
-#if 0
-#define VERSATILE_PCI_VIRT_MEM_BASE0	0xf4000000
-#define VERSATILE_PCI_VIRT_MEM_BASE1	0xf5000000
-#define VERSATILE_PCI_VIRT_MEM_BASE2	0xf6000000
-
-#define PCIO_BASE			VERSATILE_PCI_VIRT_MEM_BASE0
-#define PCIMEM_BASE			VERSATILE_PCI_VIRT_MEM_BASE1
-#endif
-
-/* CIK guesswork */
-#define PCIBIOS_MIN_IO			0x44000000
+#define PCIBIOS_MIN_IO			0x00001000
 #define PCIBIOS_MIN_MEM			0x50000000
 
 #define pcibios_assign_all_busses()     1
 
-/* macro to get at IO space when running virtually */
+/* macro to get at MMIO space when running virtually */
 #define IO_ADDRESS(x)		(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
 
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)		__typesafe_io(IO_ADDRESS(n))
 
 #endif
arch/arm/mach-versatile/include/mach/io.h +5 -2
index f067c14..a276171 100644
@@ -20,9 +20,12 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+#include <mach/hardware.h>
+#include <mach/platform.h>
 
-#define __io(a)		__typesafe_io(a)
+#define IO_SPACE_LIMIT (VERSATILE_PCI_MEM_BASE0_SIZE - 1)
+
+#define __io(a)		(a + VERSATILE_PCI_VIRT_MEM_BASE0)
 #define __mem_pci(a)	(a)
 
 #endif
arch/arm/mach-versatile/pci.c +16 -2
index 334f0df..4630ff1 100644
@@ -170,11 +170,18 @@ static struct pci_ops pci_versatile_ops = {
 	.write	= versatile_write_config,
 };
 
+static struct resource io_port = {
+	.name	= "PCI",
+	.start	= 0,
+	.end	= IO_SPACE_LIMIT,
+	.flags	= IORESOURCE_IO,
+};
+
 static struct resource io_mem = {
 	.name	= "PCI I/O space",
 	.start	= VERSATILE_PCI_MEM_BASE0,
 	.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
-	.flags	= IORESOURCE_IO,
+	.flags	= IORESOURCE_MEM,
 };
 
 static struct resource non_mem = {

@@ -201,6 +208,12 @@ static int __init pci_versatile_setup_resources(struct resource **resource)
 		       "memory region (%d)\n", ret);
 		goto out;
 	}
+	ret = request_resource(&ioport_resource, &io_port);
+	if (ret) {
+		printk(KERN_ERR "PCI: unable to allocate I/O "
+		       "port region (%d)\n", ret);
+		goto out;
+	}
 	ret = request_resource(&iomem_resource, &non_mem);
 	if (ret) {
 		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "

@@ -219,7 +232,7 @@ static int __init pci_versatile_setup_resources(struct resource **resource)
 	 * bus->resource[1] is the mem resource for this bus
 	 * bus->resource[2] is the prefetch mem resource for this bus
 	 */
-	resource[0] = &io_mem;
+	resource[0] = &io_port;
 	resource[1] = &non_mem;
 	resource[2] = &pre_mem;
 

@@ -250,6 +263,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 
 	if (nr == 0) {
 		sys->mem_offset = 0;
+		sys->io_offset = 0;
 		ret = pci_versatile_setup_resources(sys->resource);
 		if (ret < 0) {
 			printk("pci_versatile_setup: resources... oops?\n");
#1 lore raw
Quoted 7 lines

-----Original Message-----
From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm- kernel-bounces at lists.infradead.org] On Behalf Of Arnd Bergmann

I believe I have found out what is actually going on with PCI I/O space mapping on the versatile platform, thanks to Catalin pointing me in the right direction.

These changes might also be applicable to PB1176 and EB which are built from the mach-realview sub-tree.

Note however that the pcix.c source file in that sub-tree is for the NEC Northbridge based boards (PB11MPCore, PBA8 and PBX). I'm not sure if the pci.c source file even exists in mach-realview.

Colin

--
Colin Tuckley - ARM Ltd.
110 Fulbourn Rd
Cambridge, CB1 9NJ
Tel: +44 1223 400536

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

#2 lore raw
In reply to Arnd Bergmann

arch/arm/mach-versatile/include/mach/hardware.h line 42

Quoted 6 lines · Arnd Bergmann
arch/arm/mach-versatile/include/mach/hardware.h +2 -2
-/* macro to get at IO space when running virtually */
+/* macro to get at MMIO space when running virtually */
 #define IO_ADDRESS(x)		(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
 
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)		__typesafe_io(IO_ADDRESS(n))

Hmm, that's not a scenario that I forsaw __typesafe_io() being used - I'd prefer it to be restricted to only aliasing __io() to if it's appropriate. Either add an IOMEM() definition or open-code the cast here.

Quoted 6 lines
arch/arm/mach-versatile/include/mach/io.h +0 -0
index f067c14..a276171 100644
@@ -20,9 +20,12 @@
 #ifndef __ASM_ARM_ARCH_IO_H

arch/arm/mach-versatile/include/mach/io.h line 28

Quoted 10 lines
arch/arm/mach-versatile/include/mach/io.h +5 -2
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+#include <mach/hardware.h>
+#include <mach/platform.h>
 
-#define __io(a)		__typesafe_io(a)
+#define IO_SPACE_LIMIT (VERSATILE_PCI_MEM_BASE0_SIZE - 1)
+
+#define __io(a)		(a + VERSATILE_PCI_VIRT_MEM_BASE0)

Not quite. Have a look at arch/arm/mach-footbridge/include/mach/io.h to see how __io is defined there.

author
#3 lore raw
Quoted 5 lines · Russell King - ARM Linux
Quoted 4 lines · Arnd Bergmann
arch/arm/mach-versatile/include/mach/hardware.h +1 -1
-/* macro to get at IO space when running virtually */
+/* macro to get at MMIO space when running virtually */
 #define IO_ADDRESS(x)		(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
Quoted 7 lines

arch/arm/mach-versatile/include/mach/hardware.h line 42

Quoted 2 lines
arch/arm/mach-versatile/include/mach/hardware.h +1 -1
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)		__typesafe_io(IO_ADDRESS(n))

Hmm, that's not a scenario that I forsaw __typesafe_io() being used - I'd prefer it to be restricted to only aliasing __io() to if it's appropriate. Either add an IOMEM() definition or open-code the cast here.

Yes, that's what I thought, but I didn't want to change too much. Thanks for the confirmation. The same pattern is also present in other platforms, I'll follow up with a patch to fix them all.

Quoted 12 lines
Quoted 12 lines
arch/arm/mach-versatile/include/mach/io.h +2 -1
index f067c14..a276171 100644
@@ -20,9 +20,12 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+#include <mach/hardware.h>
+#include <mach/platform.h>
Quoted 7 lines

arch/arm/mach-versatile/include/mach/io.h line 28

Quoted 4 lines
arch/arm/mach-versatile/include/mach/io.h +3 -1
-#define __io(a)		__typesafe_io(a)
+#define IO_SPACE_LIMIT (VERSATILE_PCI_MEM_BASE0_SIZE - 1)
+
+#define __io(a)		(a + VERSATILE_PCI_VIRT_MEM_BASE0)

Not quite. Have a look at arch/arm/mach-footbridge/include/mach/io.h to see how __io is defined there.

The result is basically the same. My idea was to only define VERSATILE_PCI_VIRT_MEM_BASE0 in one place and use it in both the place where it get mapped and in the place where it gets used.

If I use the same definition as footbridge (which looks sensible,
#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) ),
should I do

a)
mach-versatile/include/mach/io.h:
#define PCIO_BASE ((unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0)
mach-versatile/include/mach/hardware.h:
#define VERSATILE_PCI_VIRT_MEM_BASE0 ((void __iomem *)0xeb000000ul)

or b)
mach-versatile/include/mach/io.h:
#define PCIO_BASE 0xeb000000ul
mach-versatile/include/mach/hardware.h:
#define VERSATILE_PCI_VIRT_MEM_BASE0 ((void __iomem *)PCIO_BASE)

Thanks for the review!

Arnd

author
#4 lore raw

PATCH v2 1/1 arm: versatile: enable PCI I/O space

I/O space handling on the versatile platform is currently broken in multiple ways. Most importantly, the ports do not get mapped into the virtual address space at all.

Also, there is some amount of confusion between PCI I/O space and other statically mapped MMIO registers in the platform code:

* The __io_address() macro that is used to access the platform register maps to the same __io macro that gets used for I/O space.

* The IO_SPACE_LIMIT is set to a value that is much larger than the total available space.

* The I/O resource of the PCI bus is set to the physical address of the mapping, which is way outside of the actual I/O space limit as well as the address range that gets decoded by traditional PCI cards.

* No attempt is made to stay outside of the ISA port range that some device drivers try access.

* No resource gets requested as a child of ioport_resource, but an IORESOURCE_IO type mapping gets requested as a child of iomem_resource.

This patch attempts to correct all of the above. This makes it possible to use virtio-pci based virtual devices as well as actual PCI cards including those with legacy ISA port ranges like VGA.

Some of the issues seem to be duplicated on other platforms.

Signed-off-by Arnd Bergmann <[email protected]>

---

Version 2 of this patch adds improvements suggested by Russell. I chose to define PCIO_BASE directly and to derive the static mapping from that, because it will allow us to eventually move to a fixed PCIO_BASE in the virtual mapping of multiplatform kernels.

Tested in qemu with a small patch to enable PCI I/O space for versatile. Catalin mentioned that I/O space mappings possibly never worked on the real versatile board, but applying this patch should still fix real problems, e.g. you no longer crash the kernel by writing to /dev/port and it makes it possible to use qemu virtio devices.

Arnd

 arch/arm/mach-versatile/core.c                  |   19 +++----------------
 arch/arm/mach-versatile/include/mach/hardware.h |   17 ++++-------------
 arch/arm/mach-versatile/include/mach/io.h       |    6 ++++--
 arch/arm/mach-versatile/pci.c                   |   18 ++++++++++++++++--
 4 files changed, 27 insertions(+), 33 deletions(-)
arch/arm/mach-versatile/core.c +3 -16
index 3dff864..4b9ad2c 100644
@@ -200,26 +200,13 @@ static struct map_desc versatile_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 		.length		= VERSATILE_PCI_CFG_BASE_SIZE,
 		.type		= MT_DEVICE
-	},
-#if 0
- 	{
-		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE0,
-		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
-		.length		= SZ_16M,
-		.type		= MT_DEVICE
 	}, {
-		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE1,
-		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
-		.length		= SZ_16M,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE2,
-		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
-		.length		= SZ_16M,
+		.virtual	=  (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0,
+		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
+		.length		= IO_SPACE_LIMIT,
 		.type		= MT_DEVICE
 	},
 #endif
-#endif
 };
 
 void __init versatile_map_io(void)
arch/arm/mach-versatile/include/mach/hardware.h +4 -13
index 4f8f99a..b4ae7cf 100644
@@ -29,25 +29,16 @@
  */
 #define VERSATILE_PCI_VIRT_BASE		(void __iomem *)0xe8000000ul
 #define VERSATILE_PCI_CFG_VIRT_BASE	(void __iomem *)0xe9000000ul
+#define VERSATILE_PCI_VIRT_MEM_BASE0	(void __iomem *)PCIO_BASE
 
-#if 0
-#define VERSATILE_PCI_VIRT_MEM_BASE0	0xf4000000
-#define VERSATILE_PCI_VIRT_MEM_BASE1	0xf5000000
-#define VERSATILE_PCI_VIRT_MEM_BASE2	0xf6000000
-
-#define PCIO_BASE			VERSATILE_PCI_VIRT_MEM_BASE0
-#define PCIMEM_BASE			VERSATILE_PCI_VIRT_MEM_BASE1
-#endif
-
-/* CIK guesswork */
-#define PCIBIOS_MIN_IO			0x44000000
+#define PCIBIOS_MIN_IO			0x00001000
 #define PCIBIOS_MIN_MEM			0x50000000
 
 #define pcibios_assign_all_busses()     1
 
-/* macro to get at IO space when running virtually */
+/* macro to get at MMIO space when running virtually */
 #define IO_ADDRESS(x)		(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
 
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)			((void __iomem *)IO_ADDRESS(n))
 
 #endif
arch/arm/mach-versatile/include/mach/io.h +4 -2
index f067c14..83ef5b6 100644
@@ -20,9 +20,11 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+#define PCIO_BASE	0xeb000000ul
+#define PCIO_SIZE	0x00100000ul
+#define IO_SPACE_LIMIT  (PCIO_SIZE - 1)
 
-#define __io(a)		__typesafe_io(a)
+#define __io(a)		(a + PCIO_BASE)
 #define __mem_pci(a)	(a)
 
 #endif
arch/arm/mach-versatile/pci.c +16 -2
index 334f0df..4630ff1 100644
@@ -170,11 +170,18 @@ static struct pci_ops pci_versatile_ops = {
 	.write	= versatile_write_config,
 };
 
+static struct resource io_port = {
+	.name	= "PCI",
+	.start	= 0,
+	.end	= IO_SPACE_LIMIT,
+	.flags	= IORESOURCE_IO,
+};
+
 static struct resource io_mem = {
 	.name	= "PCI I/O space",
 	.start	= VERSATILE_PCI_MEM_BASE0,
 	.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
-	.flags	= IORESOURCE_IO,
+	.flags	= IORESOURCE_MEM,
 };
 
 static struct resource non_mem = {

@@ -201,6 +208,12 @@ static int __init pci_versatile_setup_resources(struct resource **resource)
 		       "memory region (%d)\n", ret);
 		goto out;
 	}
+	ret = request_resource(&ioport_resource, &io_port);
+	if (ret) {
+		printk(KERN_ERR "PCI: unable to allocate I/O "
+		       "port region (%d)\n", ret);
+		goto out;
+	}
 	ret = request_resource(&iomem_resource, &non_mem);
 	if (ret) {
 		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "

@@ -219,7 +232,7 @@ static int __init pci_versatile_setup_resources(struct resource **resource)
 	 * bus->resource[1] is the mem resource for this bus
 	 * bus->resource[2] is the prefetch mem resource for this bus
 	 */
-	resource[0] = &io_mem;
+	resource[0] = &io_port;
 	resource[1] = &non_mem;
 	resource[2] = &pre_mem;
 

@@ -250,6 +263,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 
 	if (nr == 0) {
 		sys->mem_offset = 0;
+		sys->io_offset = 0;
 		ret = pci_versatile_setup_resources(sys->resource);
 		if (ret < 0) {
 			printk("pci_versatile_setup: resources... oops?\n");
Signature · 1 line
1.7.1
author
#5 lore raw

PATCH 1/1 arm: remove __io() abuses

The __io macros are used for PCI and ISA I/O space accesses, which are not present on most of the platforms in ARM.

However, some of the platforms use the same macro for mapping random virtial addresses for MMIO register from integer to __iomem pointers. This makes the use of __io more consistent by removing all uses that are unrelated to I/O space.

Signed-off-by Arnd Bergmann <[email protected]>
arch/arm/mach-cns3xxx/core.c +4 -4
@@ -73,14 +73,14 @@ void __iomem *gic_cpu_base_addr;
 
 void __init cns3xxx_init_irq(void)
 {
-	gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
-	gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
+	gic_cpu_base_addr = (void __iomem *)CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT;
+	gic_dist_init(0, (void __iomem *)CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, 29);
 	gic_cpu_init(0, gic_cpu_base_addr);
 }
 
 void cns3xxx_power_off(void)
 {
-	u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
+	u32 __iomem *pm_base = (void __iomem *)CNS3XXX_PM_BASE_VIRT;
 	u32 clkctrl;
 
 	printk(KERN_INFO "powering system down...\n");

@@ -239,7 +239,7 @@ static void __init __cns3xxx_timer_init(unsigned int timer_irq)
 
 static void __init cns3xxx_timer_init(void)
 {
-	cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
+	cns3xxx_tmr1 = (void __iomem *)CNS3XXX_TIMER1_2_3_BASE_VIRT;
 
 	__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
 }
arch/arm/mach-netx/generic.c +1 -1
index 43da8bb..fee2ea3 100644
@@ -168,7 +168,7 @@ void __init netx_init_irq(void)
 {
 	int irq;
 
-	vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
+	vic_init((void __iomem *)io_p2v(NETX_PA_VIC), 0, ~0, 0);
 
 	for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
 		set_irq_chip(irq, &netx_hif_chip);
arch/arm/mach-netx/include/mach/hardware.h +1 -1
index 517a2bd..f196a16 100644
@@ -20,7 +20,7 @@
 #define __ASM_ARCH_HARDWARE_H
 
 #define NETX_IO_PHYS	0x00100000
-#define NETX_IO_VIRT	0xe0000000
+#define NETX_IO_VIRT	(void __iomem *)0xe0000000
 #define NETX_IO_SIZE	0x00100000
 
 #define SRAM_INTERNAL_PHYS_0 0x00000
arch/arm/mach-netx/include/mach/netx-regs.h +8 -8
index 5a03e7c..ebeb8a4 100644
@@ -115,7 +115,7 @@
  *********************************/
 
 /* Registers */
-#define NETX_SYSTEM_REG(ofs)            __io(NETX_VA_SYSTEM + (ofs))
+#define NETX_SYSTEM_REG(ofs)        (NETX_VA_SYSTEM + (ofs))
 #define NETX_SYSTEM_BOO_SR          NETX_SYSTEM_REG(0x00)
 #define NETX_SYSTEM_IOC_CR          NETX_SYSTEM_REG(0x04)
 #define NETX_SYSTEM_IOC_MR          NETX_SYSTEM_REG(0x08)

@@ -185,7 +185,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_GPIO_REG(ofs)                     __io(NETX_VA_GPIO + (ofs))
+#define NETX_GPIO_REG(ofs)                 (NETX_VA_GPIO + (ofs))
 #define NETX_GPIO_CFG(gpio)                NETX_GPIO_REG(0x0  + ((gpio)<<2))
 #define NETX_GPIO_THRESHOLD_CAPTURE(gpio)  NETX_GPIO_REG(0x40 + ((gpio)<<2))
 #define NETX_GPIO_COUNTER_CTRL(counter)    NETX_GPIO_REG(0x80 + ((counter)<<2))

@@ -230,7 +230,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_PIO_REG(ofs)        __io(NETX_VA_PIO + (ofs))
+#define NETX_PIO_REG(ofs)        (NETX_VA_PIO + (ofs))
 #define NETX_PIO_INPIO       NETX_PIO_REG(0x0)
 #define NETX_PIO_OUTPIO      NETX_PIO_REG(0x4)
 #define NETX_PIO_OEPIO       NETX_PIO_REG(0x8)

@@ -240,7 +240,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_MIIMU           __io(NETX_VA_MIIMU)
+#define NETX_MIIMU           (NETX_VA_MIIMU)
 
 /* Bits */
 #define MIIMU_SNRDY        (1<<0)

@@ -317,7 +317,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_PFIFO_REG(ofs)               __io(NETX_VA_PFIFO + (ofs))
+#define NETX_PFIFO_REG(ofs)           (NETX_VA_PFIFO + (ofs))
 #define NETX_PFIFO_BASE(pfifo)        NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
 #define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
 #define NETX_PFIFO_RESET              NETX_PFIFO_REG(0x100)

@@ -334,7 +334,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_MEMCR_REG(ofs)               __io(NETX_VA_MEMCR + (ofs))
+#define NETX_MEMCR_REG(ofs)           (NETX_VA_MEMCR + (ofs))
 #define NETX_MEMCR_SRAM_CTRL(cs)      NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
 #define NETX_MEMCR_SDRAM_CFG_CTRL     NETX_MEMCR_REG(0x40)
 #define NETX_MEMCR_SDRAM_TIMING_CTRL  NETX_MEMCR_REG(0x44)

@@ -355,7 +355,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_DPMAS_REG(ofs)               __io(NETX_VA_DPMAS + (ofs))
+#define NETX_DPMAS_REG(ofs)           (NETX_VA_DPMAS + (ofs))
 #define NETX_DPMAS_SYS_STAT           NETX_DPMAS_REG(0x4d8)
 #define NETX_DPMAS_INT_STAT           NETX_DPMAS_REG(0x4e0)
 #define NETX_DPMAS_INT_EN             NETX_DPMAS_REG(0x4f0)

@@ -425,7 +425,7 @@
 /*******************************
  * I2C                         *
  *******************************/
-#define NETX_I2C_REG(ofs)	__io(NETX_VA_I2C, (ofs))
+#define NETX_I2C_REG(ofs) (NETX_VA_I2C, (ofs))
 #define NETX_I2C_CTRL	NETX_I2C_REG(0x0)
 #define NETX_I2C_DATA	NETX_I2C_REG(0x4)
arch/arm/mach-realview/include/mach/hardware.h +1 -1
index 8a638d1..873f721 100644
@@ -37,6 +37,6 @@
 #else
 #define IO_ADDRESS(x)		(x)
 #endif
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)		((void __iomem *)(IO_ADDRESS(n)))
 
 #endif
arch/arm/mach-ux500/include/mach/hardware.h +1 -1
index 8656379..719140d 100644
@@ -22,7 +22,7 @@
 	(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
 
 /* typesafe io address */
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)		(void __iomem *)(IO_ADDRESS(n))
 /* used by some plat-nomadik code */
 #define io_p2v(n)		__io_address(n)