tegra: Additional core support for Tegra2 SOCs

From: Colin Cross <[email protected]>

This patch set adds support for more of the Tegra 2 core systems. After review, some of these changes will be merged down with the core support that is already in the tegra for-next branch.

Colin Cross (8):
[ARM] tegra: update iomap
[ARM] tegra: Add legacy irq support
[ARM] tegra: pinmux: add safe values, move tegra2, add suspend [ARM] tegra: gpio: Add suspend and wake support [ARM] tegra: Add support for reading fuses
[ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups [ARM] tegra: common: Update common clock init table [ARM] tegra: Add cpufreq support

Gary King (1):
[ARM] tegra: add suspend and mirror irqs to legacy controller

 arch/arm/Kconfig                              |    1 +
 arch/arm/mach-tegra/Makefile                  |    6 +-
 arch/arm/mach-tegra/clock.c                   |  267 ++++++++-
 arch/arm/mach-tegra/clock.h                   |   58 ++-
 arch/arm/mach-tegra/common.c                  |    6 +-
 arch/arm/mach-tegra/cpu-tegra.c               |  185 ++++++
 arch/arm/mach-tegra/fuse.c                    |   84 +++
 arch/arm/mach-tegra/fuse.h                    |   24 +
 arch/arm/mach-tegra/gpio.c                    |  104 +++-
 arch/arm/mach-tegra/include/mach/clk.h        |    5 +
 arch/arm/mach-tegra/include/mach/gpio.h       |    4 +-
 arch/arm/mach-tegra/include/mach/io.h         |    6 +
 arch/arm/mach-tegra/include/mach/iomap.h      |   33 +-
 arch/arm/mach-tegra/include/mach/irqs.h       |    2 +
 arch/arm/mach-tegra/include/mach/legacy_irq.h |   31 +
 arch/arm/mach-tegra/include/mach/pinmux-t2.h  |  174 ++++++
 arch/arm/mach-tegra/include/mach/pinmux.h     |  210 ++-----
 arch/arm/mach-tegra/io.c                      |    6 +
 arch/arm/mach-tegra/irq.c                     |  137 +++++
 arch/arm/mach-tegra/legacy_irq.c              |  114 ++++
 arch/arm/mach-tegra/pinmux-t2-tables.c        |  260 +++++++++
 arch/arm/mach-tegra/pinmux.c                  |  354 ++++--------
 arch/arm/mach-tegra/tegra2_clocks.c           |  778 +++++++++++++++++++------
 arch/arm/mach-tegra/tegra2_dvfs.c             |   86 +++
 arch/arm/mach-tegra/tegra2_dvfs.h             |   20 +
 25 files changed, 2327 insertions(+), 628 deletions(-)
 create mode 100644 arch/arm/mach-tegra/cpu-tegra.c
 create mode 100644 arch/arm/mach-tegra/fuse.c
 create mode 100644 arch/arm/mach-tegra/fuse.h
 create mode 100644 arch/arm/mach-tegra/include/mach/legacy_irq.h
 create mode 100644 arch/arm/mach-tegra/include/mach/pinmux-t2.h
 create mode 100644 arch/arm/mach-tegra/legacy_irq.c
 create mode 100644 arch/arm/mach-tegra/pinmux-t2-tables.c
 create mode 100644 arch/arm/mach-tegra/tegra2_dvfs.c
 create mode 100644 arch/arm/mach-tegra/tegra2_dvfs.h

From: Colin Cross <[email protected]>

Add missing io address map entries from datasheet. Add the IRAM area to the statically mapped io regions. Correct the onewire, USB, and statmon addresses

---
 arch/arm/mach-tegra/include/mach/io.h    |    6 +++++
 arch/arm/mach-tegra/include/mach/iomap.h |   33 ++++++++++++++++++++++++-----
 arch/arm/mach-tegra/io.c                 |    6 +++++
 3 files changed, 39 insertions(+), 6 deletions(-)

index 35edfc3..16f1618 100644
@@ -33,6 +33,10 @@
  *
  */
 
+#define IO_IRAM_PHYS	0x40000000
+#define IO_IRAM_VIRT	0xFE400000
+#define IO_IRAM_SIZE	SZ_256K
+
 #define IO_CPU_PHYS     0x50040000
 #define IO_CPU_VIRT     0xFE000000
 #define IO_CPU_SIZE	SZ_16K

@@ -55,6 +59,8 @@
 		IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :	\
 	IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?		\
 		IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :	\
+	IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :	\
 	0)
 
 #ifndef __ASSEMBLER__

index 1741f7d..44a4f4b 100644
@@ -23,9 +23,15 @@
 
 #include <asm/sizes.h>
 
+#define TEGRA_IRAM_BASE			0x40000000
+#define TEGRA_IRAM_SIZE			SZ_256K
+
 #define TEGRA_ARM_PERIF_BASE		0x50040000
 #define TEGRA_ARM_PERIF_SIZE		SZ_8K
 
+#define TEGRA_ARM_PL310_BASE		0x50043000
+#define TEGRA_ARM_PL310_SIZE		SZ_4K
+
 #define TEGRA_ARM_INT_DIST_BASE		0x50041000
 #define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
 

@@ -68,7 +74,22 @@
 #define TEGRA_FLOW_CTRL_BASE		0x60007000
 #define TEGRA_FLOW_CTRL_SIZE		20
 
-#define TEGRA_STATMON_BASE		0x6000C4000
+#define TEGRA_AHB_DMA_BASE		0x60008000
+#define TEGRA_AHB_DMA_SIZE		SZ_4K
+
+#define TEGRA_AHB_DMA_CH0_BASE		0x60009000
+#define TEGRA_AHB_DMA_CH0_SIZE		32
+
+#define TEGRA_APB_DMA_BASE		0x6000A000
+#define TEGRA_APB_DMA_SIZE		SZ_4K
+
+#define TEGRA_APB_DMA_CH0_BASE		0x6000B000
+#define TEGRA_APB_DMA_CH0_SIZE		32
+
+#define TEGRA_AHB_GIZMO_BASE		0x6000C004
+#define TEGRA_AHB_GIZMO_SIZE		0x10C
+
+#define TEGRA_STATMON_BASE		0x6000C400
 #define TEGRA_STATMON_SIZE		SZ_1K
 
 #define TEGRA_GPIO_BASE			0x6000D000

@@ -137,7 +158,7 @@
 #define TEGRA_I2C3_BASE			0x7000C500
 #define TEGRA_I2C3_SIZE			SZ_256
 
-#define TEGRA_OWR_BASE			0x7000D000
+#define TEGRA_OWR_BASE			0x7000C600
 #define TEGRA_OWR_SIZE			80
 
 #define TEGRA_DVC_BASE			0x7000D000

@@ -182,12 +203,12 @@
 #define TEGRA_USB_BASE			0xC5000000
 #define TEGRA_USB_SIZE			SZ_16K
 
-#define TEGRA_USB1_BASE			0xC5004000
-#define TEGRA_USB1_SIZE			SZ_16K
-
-#define TEGRA_USB2_BASE			0xC5008000
+#define TEGRA_USB2_BASE			0xC5004000
 #define TEGRA_USB2_SIZE			SZ_16K
 
+#define TEGRA_USB3_BASE			0xC5008000
+#define TEGRA_USB3_SIZE			SZ_16K
+
 #define TEGRA_SDMMC1_BASE		0xC8000000
 #define TEGRA_SDMMC1_SIZE		SZ_512
 

index 9fe2c5c..31848a9 100644
@@ -49,6 +49,12 @@ static struct map_desc tegra_io_desc[] __initdata = {
 		.length = IO_CPU_SIZE,
 		.type = MT_DEVICE,
 	},
+	{
+		.virtual = IO_IRAM_VIRT,
+		.pfn = __phys_to_pfn(IO_IRAM_PHYS),
+		.length = IO_IRAM_SIZE,
+		.type = MT_DEVICE,
+	},
 };
 
 void __init tegra_map_common_io(void)

1.7.1

From: Colin Cross <[email protected]>

The "legacy irq controller" duplicates the functionality of the GIC, but remains powered during the cpu suspend and idle modes that power down the CPU and the GIC.

---
 arch/arm/mach-tegra/Makefile                  |    2 +-
 arch/arm/mach-tegra/include/mach/legacy_irq.h |   31 +++++++
 arch/arm/mach-tegra/legacy_irq.c              |  114 +++++++++++++++++++++++++
 3 files changed, 146 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/legacy_irq.h
 create mode 100644 arch/arm/mach-tegra/legacy_irq.c

index 51e9370..0a975b5 100644
@@ -1,6 +1,6 @@
 obj-y                                   += common.o
 obj-y                                   += io.o
-obj-y                                   += irq.o
+obj-y                                   += irq.o legacy_irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o

new file mode 100644
index 0000000..db1eb3d
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-tegra/include/mach/legacy_irq.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Colin Cross <[email protected]>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
+#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
+
+void tegra_legacy_mask_irq(unsigned int irq);
+void tegra_legacy_unmask_irq(unsigned int irq);
+void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
+void tegra_legacy_force_irq_set(unsigned int irq);
+void tegra_legacy_force_irq_clr(unsigned int irq);
+int tegra_legacy_force_irq_status(unsigned int irq);
+void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
+unsigned long tegra_legacy_vfiq(int nr);
+unsigned long tegra_legacy_class(int nr);
+
+#endif

1.7.1

From: Gary King <[email protected]>

mirror IRQ enable and disable operations on the legacy PPI system interrupt controller, since the legacy controller is responsible for responding to wakeup interrupts when the CPU is in LP2 idle mode

save the irq controller state on suspend and restore on resume

---
 arch/arm/mach-tegra/include/mach/irqs.h |    2 +
 arch/arm/mach-tegra/irq.c               |  137 +++++++++++++++++++++++++++++++
 2 files changed, 139 insertions(+), 0 deletions(-)

index 20f640e..71bbf34 100644
@@ -25,6 +25,7 @@
 
 #define IRQ_LOCALTIMER                  29
 
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 /* Primary Interrupt Controller */
 #define INT_PRI_BASE			(INT_GIC_BASE + 32)
 #define INT_TMR1			(INT_PRI_BASE + 0)

@@ -169,5 +170,6 @@
 #define INT_GPIO_NR			(28 * 8)
 
 #define NR_IRQS				(INT_GPIO_BASE + INT_GPIO_NR)
+#endif
 
 #endif

1.7.1

From: Colin Cross <[email protected]>

- the reset values for some pin groups in the tegra pin mux can result in functional errors due to conflicting with actively-configured pin groups muxing from the same controller. this change adds a known safe, non- conflicting mux for every pin group, which can be used on platforms where the pin group is not routed to any peripheral

- also add each pin group's I/O voltage rail, to enable platform code to map from the pin groups used by each interface to the regulators used for dynamic voltage control

- add routines to individually configure the tristate, pin mux and pull- ups for a pingroup_config array, so that it is possible to program individual values at run-time without modifying other values. this allows driver power-management code to reprogram individual interfaces into lower power states during idle / suspend, or to reprogram the pin mux to support multiple physical busses per internal controller (e.g., sharing a single I2C or SPI controller across multiple pin groups)

- move chip-specific data like pingroups and drive-pingroups out of the common code and into chip-specific code

- fix debug output for group with no pullups

- add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE will automatically select a mux setting that is guaranteed not to conflict with any of the hardware blocks.

---
 arch/arm/mach-tegra/Makefile                 |    1 +
 arch/arm/mach-tegra/include/mach/pinmux-t2.h |  174 +++++++++++++
 arch/arm/mach-tegra/include/mach/pinmux.h    |  210 ++++------------
 arch/arm/mach-tegra/pinmux-t2-tables.c       |  260 +++++++++++++++++++
 arch/arm/mach-tegra/pinmux.c                 |  354 +++++++++-----------------
 5 files changed, 603 insertions(+), 396 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/pinmux-t2.h
 create mode 100644 arch/arm/mach-tegra/pinmux-t2-tables.c

index 0a975b5..87d065e 100644
@@ -7,6 +7,7 @@ obj-y                                   += gpio.o
 obj-y                                   += pinmux.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-t2-tables.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 

1.7.1

From: Colin Cross <[email protected]>

Includes checkpatch fixes and TEGRA_NR_GPIOS changes from Mike Rapoport <[email protected]>

---
 arch/arm/mach-tegra/gpio.c              |  104 +++++++++++++++++++++++++++---
 arch/arm/mach-tegra/include/mach/gpio.h |    4 +-
 2 files changed, 95 insertions(+), 13 deletions(-)

index fe78fba..0775265 100644
@@ -19,6 +19,7 @@
 
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/interrupt.h>
 
 #include <linux/io.h>
 #include <linux/gpio.h>

@@ -60,6 +61,13 @@ struct tegra_gpio_bank {
 	int bank;
 	int irq;
 	spinlock_t lvl_lock[4];
+#ifdef CONFIG_PM
+	u32 cnf[4];
+	u32 out[4];
+	u32 oe[4];
+	u32 int_enb[4];
+	u32 int_lvl[4];
+#endif
 };
 
 

@@ -131,7 +139,7 @@ static struct gpio_chip tegra_gpio_chip = {
 	.direction_output	= tegra_gpio_direction_output,
 	.set			= tegra_gpio_set,
 	.base			= 0,
-	.ngpio			= ARCH_NR_GPIOS,
+	.ngpio			= TEGRA_NR_GPIOS,
 };
 
 static void tegra_gpio_irq_ack(unsigned int irq)

@@ -244,6 +252,76 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 }
 
+#ifdef CONFIG_PM
+void tegra_gpio_resume(void)
+{
+	unsigned long flags;
+	int b, p, i;
+
+	local_irq_save(flags);
+
+	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
+		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
+
+		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
+			unsigned int gpio = (b<<5) | (p<<3);
+			__raw_writel(bank->cnf[p], GPIO_CNF(gpio));
+			__raw_writel(bank->out[p], GPIO_OUT(gpio));
+			__raw_writel(bank->oe[p], GPIO_OE(gpio));
+			__raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
+			__raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
+		}
+	}
+
+	local_irq_restore(flags);
+
+	for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
+		struct irq_desc *desc = irq_to_desc(i);
+		if (!desc || (desc->status & IRQ_WAKEUP))
+			continue;
+		enable_irq(i);
+	}
+}
+
+void tegra_gpio_suspend(void)
+{
+	unsigned long flags;
+	int b, p, i;
+
+	for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
+		struct irq_desc *desc = irq_to_desc(i);
+		if (!desc)
+			continue;
+		if (desc->status & IRQ_WAKEUP) {
+			int gpio = i - INT_GPIO_BASE;
+			pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7);
+			continue;
+		}
+		disable_irq(i);
+	}
+
+	local_irq_save(flags);
+	for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
+		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
+
+		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
+			unsigned int gpio = (b<<5) | (p<<3);
+			bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
+			bank->out[p] = __raw_readl(GPIO_OUT(gpio));
+			bank->oe[p] = __raw_readl(GPIO_OE(gpio));
+			bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
+			bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
+		}
+	}
+	local_irq_restore(flags);
+}
+
+static int tegra_gpio_wake_enable(unsigned int irq, unsigned int enable)
+{
+	struct tegra_gpio_bank *bank = get_irq_chip_data(irq);
+	return set_irq_wake(bank->irq, enable);
+}
+#endif
 
 static struct irq_chip tegra_gpio_irq_chip = {
 	.name		= "GPIO",

@@ -251,6 +329,9 @@ static struct irq_chip tegra_gpio_irq_chip = {
 	.mask		= tegra_gpio_irq_mask,
 	.unmask		= tegra_gpio_irq_unmask,
 	.set_type	= tegra_gpio_irq_set_type,
+#ifdef CONFIG_PM
+	.set_wake	= tegra_gpio_wake_enable,
+#endif
 };
 
 

@@ -274,7 +355,7 @@ static int __init tegra_gpio_init(void)
 
 	gpiochip_add(&tegra_gpio_chip);
 
-	for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + ARCH_NR_GPIOS); i++) {
+	for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
 		bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
 
 		lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class);

@@ -312,15 +393,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 	for (i = 0; i < 7; i++) {
 		for (j = 0; j < 4; j++) {
 			int gpio = tegra_gpio_compose(i, j, 0);
-			seq_printf(s, "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
-			       i, j,
-			       __raw_readl(GPIO_CNF(gpio)),
-			       __raw_readl(GPIO_OE(gpio)),
-			       __raw_readl(GPIO_OUT(gpio)),
-			       __raw_readl(GPIO_IN(gpio)),
-			       __raw_readl(GPIO_INT_STA(gpio)),
-			       __raw_readl(GPIO_INT_ENB(gpio)),
-			       __raw_readl(GPIO_INT_LVL(gpio)));
+			seq_printf(s,
+				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
+				i, j,
+				__raw_readl(GPIO_CNF(gpio)),
+				__raw_readl(GPIO_OE(gpio)),
+				__raw_readl(GPIO_OUT(gpio)),
+				__raw_readl(GPIO_IN(gpio)),
+				__raw_readl(GPIO_INT_STA(gpio)),
+				__raw_readl(GPIO_INT_ENB(gpio)),
+				__raw_readl(GPIO_INT_LVL(gpio)));
 		}
 	}
 	return 0;

index 540e822..e31f486 100644
@@ -22,7 +22,7 @@
 
 #include <mach/irqs.h>
 
-#define ARCH_NR_GPIOS		INT_GPIO_NR
+#define TEGRA_NR_GPIOS		INT_GPIO_NR
 
 #include <asm-generic/gpio.h>
 

@@ -35,7 +35,7 @@
 
 static inline int gpio_to_irq(unsigned int gpio)
 {
-	if (gpio < ARCH_NR_GPIOS)
+	if (gpio < TEGRA_NR_GPIOS)
 		return INT_GPIO_BASE + gpio;
 	return -EINVAL;
 }

1.7.1

From: Colin Cross <[email protected]>

The Tegra SOC contains fuses to identify the CPU type and bin, and a unique id. The CPU info is required to determine the correct voltages for each cpu and core frequency.

---
 arch/arm/mach-tegra/Makefile |    1 +
 arch/arm/mach-tegra/common.c |    2 +
 arch/arm/mach-tegra/fuse.c   |   84 ++++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/fuse.h   |   24 ++++++++++++
 4 files changed, 111 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/fuse.c
 create mode 100644 arch/arm/mach-tegra/fuse.h

index 87d065e..6203475 100644
@@ -5,6 +5,7 @@ obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o
 obj-y                                   += pinmux.o
+obj-y					+= fuse.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-t2-tables.o

index 039a514..9aedaf7 100644
@@ -26,6 +26,7 @@
 
 #include "board.h"
 #include "clock.h"
+#include "fuse.h"
 
 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	/* name		parent		rate		enabled */

@@ -55,6 +56,7 @@ void __init tegra_init_cache(void)
 
 void __init tegra_common_init(void)
 {
+	tegra_init_fuse();
 	tegra_init_clock();
 	tegra_clk_init_from_table(common_clk_init_table);
 	tegra_init_cache();

new file mode 100644
index 0000000..584b2e2
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-tegra/fuse.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <[email protected]>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+unsigned long long tegra_chip_uid(void);
+int tegra_sku_id(void);
+int tegra_cpu_process_id(void);
+int tegra_core_process_id(void);
+void tegra_init_fuse(void);

1.7.1

From: Colin Cross <[email protected]>

- Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops

---
 arch/arm/mach-tegra/Makefile           |    1 +
 arch/arm/mach-tegra/clock.c            |  267 ++++++++++-
 arch/arm/mach-tegra/clock.h            |   58 ++-
 arch/arm/mach-tegra/include/mach/clk.h |    5 +
 arch/arm/mach-tegra/tegra2_clocks.c    |  778 +++++++++++++++++++++++++-------
 arch/arm/mach-tegra/tegra2_dvfs.c      |   86 ++++
 arch/arm/mach-tegra/tegra2_dvfs.h      |   20 +
 7 files changed, 1005 insertions(+), 210 deletions(-)
 create mode 100644 arch/arm/mach-tegra/tegra2_dvfs.c
 create mode 100644 arch/arm/mach-tegra/tegra2_dvfs.h

index 6203475..3642e58 100644
@@ -8,6 +8,7 @@ obj-y                                   += pinmux.o
 obj-y					+= fuse.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_dvfs.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-t2-tables.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o

index 2896f25..d772395 100644
@@ -23,4 +23,9 @@
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
+int clk_enable_cansleep(struct clk *clk);
+void clk_disable_cansleep(struct clk *clk);
+int clk_set_rate_cansleep(struct clk *clk, unsigned long rate);
+int clk_set_parent_cansleep(struct clk *clk, struct clk *parent);
+
 #endif

new file mode 100644
index 0000000..f8c1adb
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-tegra/tegra2_dvfs.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <[email protected]>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+extern struct dvfs tegra_dvfs_virtual_cpu_dvfs;

1.7.1

From: Colin Cross <[email protected]>

Renames clocks in the clock init table to match the datasheet names

---
 arch/arm/mach-tegra/common.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

index 9aedaf7..445104a 100644
@@ -36,8 +36,8 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	{ "pll_p_out2",	"pll_p",	48000000,	true },
 	{ "pll_p_out3",	"pll_p",	72000000,	true },
 	{ "pll_p_out4",	"pll_p",	108000000,	true },
-	{ "sys",	"pll_p_out4",	108000000,	true },
-	{ "hclk",	"sys",		108000000,	true },
+	{ "sclk",	"pll_p_out4",	108000000,	true },
+	{ "hclk",	"sclk",		108000000,	true },
 	{ "pclk",	"hclk",		54000000,	true },
 	{ NULL,		NULL,		0,		0},
 };

1.7.1

From: Colin Cross <[email protected]>

Implement cpufreq support for the Tegra SOC. DVFS is handled by the core virtual cpu clock. The frequencies of the two cores are tied together, the highest frequency requested by either core determines the actual frequency.

---
 arch/arm/Kconfig                |    1 +
 arch/arm/mach-tegra/Makefile    |    1 +
 arch/arm/mach-tegra/cpu-tegra.c |  185 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 187 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/cpu-tegra.c

index 1341628..1ccf0d3 100644
@@ -569,6 +569,7 @@ config ARCH_TEGRA
 	select HAVE_CLK
 	select COMMON_CLKDEV
 	select ARCH_HAS_BARRIERS if CACHE_L2X0
+	select ARCH_HAS_CPUFREQ
 	help
 	  This enables support for NVIDIA Tegra based systems (Tegra APX,
 	  Tegra 6xx and Tegra 2 series).

index 3642e58..2a37621 100644
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_dvfs.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-t2-tables.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 
 obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
 obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o

1.7.1

Hey,

just a few minor comments:

static int

static unsined int

Done

Done

Adjusting the CPU clock may require changing the voltage through the regulator api, which locks a mutex, and eventually through I2C, which sleeps on I2C completion.

...although in some systems the I2C cost will be replaced with updating a GPIO which is very much cheaper.

Yes, but even on a GPIO regulator, the regulator api will lock a mutex and possibly schedule.

Yup, the schedule will depend on how long it takes to charge the cap on the output in the case of the GPIO regulator. The point being that the delay you'll encounter is wildly variable depending on hardware setup.

Any comments on the below patches? If not I'm going to push them to our for-next tree.

These changes have been pushed to

git://android.kernel.org/kernel/tegra.git for-next

Colin Cross (10):
[ARM] tegra: update iomap
[ARM] tegra: Add legacy irq support
[ARM] tegra: pinmux: add safe values, move tegra2, add suspend [ARM] tegra: gpio: Add suspend and wake support [ARM] tegra: Add support for reading fuses
[ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups [ARM] tegra: common: Update common clock init table [ARM] tegra: Add cpufreq support
[ARM] tegra: Add tegra_defconfig
[ARM] tegra: Add APB DMA support

Gary King (1):
[ARM] tegra: add suspend and mirror irqs to legacy controller

 arch/arm/Kconfig                              |    1 +
 arch/arm/configs/tegra_defconfig              | 1095 +++++++++++++++++++++++++
 arch/arm/mach-tegra/Kconfig                   |    7 +
 arch/arm/mach-tegra/Makefile                  |    7 +-
 arch/arm/mach-tegra/clock.c                   |  267 ++++++-
 arch/arm/mach-tegra/clock.h                   |   58 +-
 arch/arm/mach-tegra/common.c                  |   13 +-
 arch/arm/mach-tegra/cpu-tegra.c               |  185 +++++
 arch/arm/mach-tegra/dma.c                     |  752 +++++++++++++++++
 arch/arm/mach-tegra/fuse.c                    |   84 ++
 arch/arm/mach-tegra/fuse.h                    |   24 +
 arch/arm/mach-tegra/gpio.c                    |  104 +++-
 arch/arm/mach-tegra/include/mach/clk.h        |    5 +
 arch/arm/mach-tegra/include/mach/dma.h        |  155 ++++
 arch/arm/mach-tegra/include/mach/gpio.h       |    4 +-
 arch/arm/mach-tegra/include/mach/io.h         |    6 +
 arch/arm/mach-tegra/include/mach/iomap.h      |   33 +-
 arch/arm/mach-tegra/include/mach/irqs.h       |    2 +
 arch/arm/mach-tegra/include/mach/legacy_irq.h |   31 +
 arch/arm/mach-tegra/include/mach/pinmux-t2.h  |  174 ++++
 arch/arm/mach-tegra/include/mach/pinmux.h     |  210 ++----
 arch/arm/mach-tegra/io.c                      |    6 +
 arch/arm/mach-tegra/irq.c                     |  137 +++
 arch/arm/mach-tegra/legacy_irq.c              |  114 +++
 arch/arm/mach-tegra/pinmux-t2-tables.c        |  260 ++++++
 arch/arm/mach-tegra/pinmux.c                  |  354 +++------
 arch/arm/mach-tegra/tegra2_clocks.c           |  778 ++++++++++++++----
 arch/arm/mach-tegra/tegra2_dvfs.c             |   86 ++
 arch/arm/mach-tegra/tegra2_dvfs.h             |   20 +
 29 files changed, 4344 insertions(+), 628 deletions(-)
 create mode 100644 arch/arm/configs/tegra_defconfig
 create mode 100644 arch/arm/mach-tegra/cpu-tegra.c
 create mode 100644 arch/arm/mach-tegra/dma.c
 create mode 100644 arch/arm/mach-tegra/fuse.c
 create mode 100644 arch/arm/mach-tegra/fuse.h
 create mode 100644 arch/arm/mach-tegra/include/mach/dma.h
 create mode 100644 arch/arm/mach-tegra/include/mach/legacy_irq.h
 create mode 100644 arch/arm/mach-tegra/include/mach/pinmux-t2.h
 create mode 100644 arch/arm/mach-tegra/legacy_irq.c
 create mode 100644 arch/arm/mach-tegra/pinmux-t2-tables.c
 create mode 100644 arch/arm/mach-tegra/tegra2_dvfs.c
 create mode 100644 arch/arm/mach-tegra/tegra2_dvfs.h

Where are the patches? I don't see them on the mailing list. We don't review code sitting in git trees - only patches on mailing lists.

Sorry for the confusion. These patches were posted by Colin Cross on July 29th (http://www.spinics.net/lists/arm-kernel/msg94637.html) and pinged again by me on August 25th
(http://www.spinics.net/lists/arm-kernel/msg96657.html).

Cheers,
Erik