ARMV7: Enhance support for OMAP4

index 5bf7173..2e80d1f 100644
@@ -88,3 +88,14 @@ int checkboard(void)
 	return 0;
 }
 
+/*
+* This function is called by start_armboot. You can reliably use static
+* data. Any boot-time function that require static data should be
+* called from here
+*/
+int arch_cpu_init(void)
+{
+	set_muxconf_regs();
+	return 0;
+}
+

344 lines not on this page · raw message

index 5243ea8..79ff22c 100644
@@ -44,6 +44,8 @@
 
 /* CONTROL */
 #define CTRL_BASE		(OMAP44XX_L4_CORE_BASE + 0x2000)
+#define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
+#define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)

index c6fab00..ad0c640 100644
@@ -32,6 +32,7 @@ void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
 void invalidate_dcache(u32);
+void set_muxconf_regs(void);
 
 extern const struct omap_sysinfo sysinfo;
 

index 917bbec..1b8153b 100644
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 
+#include "panda.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 const struct omap_sysinfo sysinfo = {

@@ -61,3 +63,27 @@ int misc_init_r(void)
 {
 	return 0;
 }
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the board.
+ */
+void set_muxconf_regs(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
+		   sizeof(core_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
+		   sizeof(wkup_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+}

265 lines not on this page · raw message

index 8ed7873..7039bd5 100644
@@ -25,6 +25,8 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 
+#include "sdp.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 const struct omap_sysinfo sysinfo = {

@@ -62,3 +64,27 @@ int misc_init_r(void)
 {
 	return 0;
 }
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the board.
+ */
+void set_muxconf_regs(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
+		   sizeof(core_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
+		   sizeof(wkup_padconf_array) /
+		   sizeof(struct pad_conf_entry));
+}

265 lines not on this page · raw message

index b1e40a3..0c5ef7b 100644
@@ -35,6 +35,7 @@
 #define CONFIG_OMAP44XX		1	/* which is a 44XX */
 #define CONFIG_OMAP4430		1	/* which is in a 4430 */
 #define CONFIG_PANDA		1	/* working with Panda */
+#define CONFIG_ARCH_CPU_INIT
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>

index 8121554..ede7691 100644
@@ -36,6 +36,7 @@
 #define CONFIG_OMAP44XX		1	/* which is a 44XX */
 #define CONFIG_OMAP4430		1	/* which is in a 4430 */
 #define CONFIG_4430SDP		1	/* working with SDP */
+#define CONFIG_ARCH_CPU_INIT
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>

index 69e285f..6b8cf7b 100644
@@ -41,12 +41,8 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 
 /*
  * Nothing really to do with interrupts, just starts up a counter.
- * We run the counter with 13MHz, divided by 8, resulting in timer
- * frequency of 1.625MHz. With 32bit counter register, counter
- * overflows in ~44min
  */
 
-/* 13MHz / 8 = 1.625MHz */
 #define TIMER_CLOCK	(V_SCLK / (2 << CONFIG_SYS_PTV))
 #define TIMER_LOAD_VAL	0xffffffff
 

@@ -84,11 +80,6 @@ void set_timer(ulong t)
 /* delay x useconds */
 void __udelay(unsigned long usec)
 {
-#if defined(CONFIG_OMAP44XX)
-	/* TODO temporary hack until OMAP4 clock setup routines are present */
-	if (usec > 1000)
-		usec = usec/1000;
-#endif
 	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
 	unsigned long now, last = readl(&timer_base->tcrr);
 

index 0c5ef7b..0fb1ad3 100644
@@ -196,7 +196,7 @@
 #define CONFIG_SYS_LOAD_ADDR		0x80000000
 
 /* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT1_BASE
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 #define CONFIG_SYS_HZ			1000
 

index ede7691..ef5272b 100644
@@ -197,7 +197,7 @@
 #define CONFIG_SYS_LOAD_ADDR		0x80000000
 
 /* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE		GPT1_BASE
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 #define CONFIG_SYS_HZ			1000
 

index 7a4a73a..d2e7488 100644
@@ -34,7 +34,9 @@ struct i2c {
 	unsigned short stat;	/* 0x08 */
 	unsigned short res3;
 	unsigned short iv;	/* 0x0C */
-	unsigned short res4[3];
+	unsigned short res4;
+	unsigned short syss;	/* 0x10 */
+	unsigned short res4a;
 	unsigned short buf;	/* 0x14 */
 	unsigned short res5;
 	unsigned short cnt;	/* 0x18 */

index 3256133..7c98f15 100644
@@ -27,6 +27,8 @@
 
 #include "omap24xx_i2c.h"
 
+#define I2C_TIMEOUT	10
+
 static void wait_for_bb (void);
 static u16 wait_for_pin (void);
 static void flush_fifo(void);

@@ -41,6 +43,7 @@ void i2c_init (int speed, int slaveadd)
 	int psc, fsscll, fssclh;
 	int hsscll = 0, hssclh = 0;
 	u32 scll, sclh;
+	int timeout = I2C_TIMEOUT;
 
 	/* Only handle standard, fast and high speeds */
 	if ((speed != OMAP_I2C_STANDARD) &&

@@ -102,15 +105,24 @@ void i2c_init (int speed, int slaveadd)
 		sclh = (unsigned int)fssclh;
 	}
 
-	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
-	udelay(1000);
-	writew(0x0, &i2c_base->sysc); /* will probably self clear but */
-
 	if (readw (&i2c_base->con) & I2C_CON_EN) {
 		writew (0, &i2c_base->con);
 		udelay (50000);
 	}
 
+	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
+	udelay(1000);
+
+	writew(I2C_CON_EN, &i2c_base->con);
+	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
+		if (timeout <= 0) {
+			printf("ERROR: Timeout in soft-reset\n");
+			return;
+		}
+		udelay(1000);
+	}
+
+	writew(0, &i2c_base->con);
 	writew(psc, &i2c_base->psc);
 	writew(scll, &i2c_base->scll);
 	writew(sclh, &i2c_base->sclh);

@@ -159,15 +171,14 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 	}
 
 	if (!i2c_error) {
-		/* free bus, otherwise we can't use a combined transction */
-		writew (0, &i2c_base->con);
-		while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) {
+		writew (I2C_CON_EN, &i2c_base->con);
+		while (readw(&i2c_base->stat) &
+			(I2C_STAT_XRDY | I2C_STAT_ARDY)) {
 			udelay (10000);
 			/* Have to clear pending interrupt to clear I2C_STAT */
 			writew (0xFFFF, &i2c_base->stat);
 		}
 
-		wait_for_bb ();
 		/* set slave address */
 		writew (devaddr, &i2c_base->sa);
 		/* read one byte from slave */

@@ -191,8 +202,8 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 
 		if (!i2c_error) {
 			writew (I2C_CON_EN, &i2c_base->con);
-			while (readw (&i2c_base->stat)
-			       || (readw (&i2c_base->con) & I2C_CON_MST)) {
+			while (readw (&i2c_base->stat) &
+				(I2C_STAT_RRDY | I2C_STAT_ARDY)) {
 				udelay (10000);
 				writew (0xFFFF, &i2c_base->stat);
 			}

index 92a3416..650e33a 100644
@@ -85,6 +85,10 @@
 #define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
 #define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
 
+/* I2C System Status Register (I2C_SYSS): */
+
+#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
+
 #define I2C_SCLL_SCLL		0
 #define I2C_SCLL_SCLL_M		0xFF
 #define I2C_SCLL_HSSCLL		8

77 lines not on this page · raw message

index 0fb1ad3..4bec00b 100644
@@ -103,6 +103,9 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 #define CONFIG_I2C_MULTI_BUS		1
 
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER		1
+
 /* MMC */
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1

index ef5272b..c18e71a 100644
@@ -104,6 +104,9 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 #define CONFIG_I2C_MULTI_BUS		1
 
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER		1
+
 /* MMC */
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1

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78 lines not on this page · raw message

index 0fb1ad3..4bec00b 100644
@@ -103,6 +103,9 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 #define CONFIG_I2C_MULTI_BUS		1
 
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER		1
+
 /* MMC */
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1

index ef5272b..c18e71a 100644
@@ -104,6 +104,9 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 #define CONFIG_I2C_MULTI_BUS		1
 
+/* TWL6030 */
+#define CONFIG_TWL6030_POWER		1
+
 /* MMC */
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1

91 lines not on this page · raw message

index c072c27..390b007 100644
@@ -483,4 +483,7 @@ struct pm {
 #define I2C_BASE2		(OMAP34XX_CORE_L4_IO_BASE + 0x72000)
 #define I2C_BASE3		(OMAP34XX_CORE_L4_IO_BASE + 0x60000)
 
+/* MUSB base */
+#define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
+
 #endif /* _CPU_H */

index c056b95..7d5748a 100644
@@ -139,4 +139,7 @@ struct watchdog {
 #define I2C_BASE2		(OMAP44XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3		(OMAP44XX_L4_PER_BASE + 0x60000)
 
+/* MUSB base */
+#define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
+
 #endif /* _CPU_H */

index a983552..c7876ed 100644
@@ -31,6 +31,7 @@
  */
 
 #include <twl4030.h>
+#include <twl6030.h>
 #include "omap3.h"
 
 static int platform_needs_initialization = 1;

@@ -65,7 +66,12 @@ static struct omap3_otg_regs *otg;
 
 #define OMAP3_OTG_SYSSTATUS_RESETDONE			0x0001
 
+/* OMAP4430 has an internal PHY, use it */
+#ifdef CONFIG_OMAP4430
+#define OMAP3_OTG_INTERFSEL_OMAP			0x0000
+#else
 #define OMAP3_OTG_INTERFSEL_OMAP			0x0001
+#endif
 
 #define OMAP3_OTG_FORCESTDBY_STANDBY			0x0001
 

@@ -105,6 +111,11 @@ int musb_platform_init(void)
 			goto end;
 		}
 #endif
+
+#ifdef CONFIG_TWL6030_POWER
+		twl6030_usb_device_settings();
+#endif
+
 		otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE;
 
 		/* Set OTG to always be on */

@@ -122,6 +133,11 @@ int musb_platform_init(void)
 #ifdef CONFIG_OMAP3_EVM
 		musb_cfg.extvbus = omap3_evm_need_extvbus();
 #endif
+
+#ifdef CONFIG_OMAP4430
+		u32 *usbotghs_control = (u32 *)(CTRL_BASE + 0x33C);
+		*usbotghs_control = 0x15;
+#endif
 		platform_needs_initialization = 0;
 	}
 

index c934e0c..ea00fed 100644
@@ -31,10 +31,11 @@
 #ifndef _MUSB_OMAP3_H_
 #define _MUSB_OMAP3_H_
 
+#include <asm/arch/cpu.h>
 #include "musb_core.h"
 
 /* Base address of MUSB registers */
-#define MENTOR_USB0_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
+#define MENTOR_USB0_BASE MUSB_BASE
 
 /* Base address of OTG registers */
 #define OMAP3_OTG_BASE (MENTOR_USB0_BASE + 0x400)

index c18e71a..e9909f9 100644
@@ -113,6 +113,20 @@
 #define CONFIG_SYS_MMC_SET_DEV		1
 #define CONFIG_DOS_PARTITION		1
 
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"SDP4430"
+
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
 

@@ -146,6 +160,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
+	"usbtty=cdc_acm\0" \
 	"mmcdev=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \

index 4bec00b..1d76467 100644
@@ -112,6 +112,20 @@
 #define CONFIG_SYS_MMC_SET_DEV		1
 #define CONFIG_DOS_PARTITION		1
 
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"OMAP4 Panda"
+
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
 

@@ -145,6 +159,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
+	"usbtty=cdc_acm\0" \
 	"mmcdev=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \

index 1d76467..a0d27a4 100644
@@ -153,6 +153,8 @@
  * Environment setup
  */
 
+#define CONFIG_BOOTDELAY	3
+
 /* allow overwriting serial config and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 

@@ -160,10 +162,12 @@
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
 	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
 	"mmcdev=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \
 	"mmcargs=setenv bootargs console=${console} " \
+		"vram=${vram} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \

@@ -181,7 +185,6 @@
 		"else " \
 			"if run loaduimage; then " \
 				"run mmcboot; " \
-			"else run nandboot; " \
 			"fi; " \
 		"fi; " \
 	"fi"

index e9909f9..d5439f9 100644
@@ -154,6 +154,8 @@
  * Environment setup
  */
 
+#define CONFIG_BOOTDELAY	3
+
 /* allow overwriting serial config and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 

@@ -161,10 +163,12 @@
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
 	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
 	"mmcdev=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \
 	"mmcargs=setenv bootargs console=${console} " \
+		"vram=${vram} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \

@@ -182,7 +186,6 @@
 		"else " \
 			"if run loaduimage; then " \
 				"run mmcboot; " \
-			"else run nandboot; " \
 			"fi; " \
 		"fi; " \
 	"fi"