dmaengine: assorted patches and Freescale SDMA support

1/3

---
 drivers/dma/dmaengine.c   |    2 ++
 include/linux/dmaengine.h |    6 +++++-
 2 files changed, 7 insertions(+), 1 deletions(-)
index 9d31d5e..e5e79ce 100644
@@ -692,6 +692,8 @@ int dma_async_device_register(struct dma_device *device)
 		!device->device_prep_dma_interrupt);
 	BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
 		!device->device_prep_slave_sg);
+	BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
+		!device->device_prep_dma_cyclic);
 	BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
 		!device->device_control);
 

index c61d4ca..0df7864 100644
@@ -67,10 +67,11 @@ enum dma_transaction_type {
 	DMA_PRIVATE,
 	DMA_ASYNC_TX,
 	DMA_SLAVE,
+	DMA_CYCLIC,
 };
 
 /* last transaction type for creation of the capabilities mask */
-#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
+#define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
 
 
 /**

@@ -478,6 +479,9 @@ struct dma_device {
 		struct dma_chan *chan, struct scatterlist *sgl,
 		unsigned int sg_len, enum dma_data_direction direction,
 		unsigned long flags);
+	struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_data_direction direction);
 	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		unsigned long arg);
 

1.7.1
---
 drivers/dma/dmaengine.c   |    2 ++
 include/linux/dmaengine.h |    6 +++++-
 2 files changed, 7 insertions(+), 1 deletions(-)
index 9d31d5e..e5e79ce 100644
@@ -692,6 +692,8 @@ int dma_async_device_register(struct dma_device *device)
 		!device->device_prep_dma_interrupt);
 	BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
 		!device->device_prep_slave_sg);
+	BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
+		!device->device_prep_dma_cyclic);
 	BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
 		!device->device_control);
 

index c61d4ca..0df7864 100644
@@ -67,10 +67,11 @@ enum dma_transaction_type {
 	DMA_PRIVATE,
 	DMA_ASYNC_TX,
 	DMA_SLAVE,
+	DMA_CYCLIC,
 };
 
 /* last transaction type for creation of the capabilities mask */
-#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
+#define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
 
 
 /**

@@ -478,6 +479,9 @@ struct dma_device {
 		struct dma_chan *chan, struct scatterlist *sgl,
 		unsigned int sg_len, enum dma_data_direction direction,
 		unsigned long flags);
+	struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_data_direction direction);
 	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		unsigned long arg);
 

1.7.1
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
---
 drivers/dma/dmaengine.c   |    2 ++
 include/linux/dmaengine.h |    6 +++++-
 2 files changed, 7 insertions(+), 1 deletions(-)
index 9d31d5e..e5e79ce 100644
@@ -692,6 +692,8 @@ int dma_async_device_register(struct dma_device *device)
 		!device->device_prep_dma_interrupt);
 	BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
 		!device->device_prep_slave_sg);
+	BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
+		!device->device_prep_dma_cyclic);
 	BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
 		!device->device_control);
 

index c61d4ca..0df7864 100644
@@ -67,10 +67,11 @@ enum dma_transaction_type {
 	DMA_PRIVATE,
 	DMA_ASYNC_TX,
 	DMA_SLAVE,
+	DMA_CYCLIC,
 };
 
 /* last transaction type for creation of the capabilities mask */
-#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
+#define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
 
 
 /**

@@ -478,6 +479,9 @@ struct dma_device {
 		struct dma_chan *chan, struct scatterlist *sgl,
 		unsigned int sg_len, enum dma_data_direction direction,
 		unsigned long flags);
+	struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_data_direction direction);
 	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		unsigned long arg);
 

1.7.1
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
---
 drivers/dma/dmaengine.c   |    2 ++
 include/linux/dmaengine.h |    6 +++++-
 2 files changed, 7 insertions(+), 1 deletions(-)
index 9d31d5e..e5e79ce 100644
@@ -692,6 +692,8 @@ int dma_async_device_register(struct dma_device *device)
 		!device->device_prep_dma_interrupt);
 	BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
 		!device->device_prep_slave_sg);
+	BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
+		!device->device_prep_dma_cyclic);
 	BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
 		!device->device_control);
 

index c61d4ca..0df7864 100644
@@ -67,10 +67,11 @@ enum dma_transaction_type {
 	DMA_PRIVATE,
 	DMA_ASYNC_TX,
 	DMA_SLAVE,
+	DMA_CYCLIC,
 };
 
 /* last transaction type for creation of the capabilities mask */
-#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
+#define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
 
 
 /**

@@ -478,6 +479,9 @@ struct dma_device {
 		struct dma_chan *chan, struct scatterlist *sgl,
 		unsigned int sg_len, enum dma_data_direction direction,
 		unsigned long flags);
+	struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_data_direction direction);
 	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		unsigned long arg);
 

1.7.1
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
---
 include/linux/dmaengine.h |   41 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+), 0 deletions(-)
index 0df7864..635c60b 100644
@@ -491,6 +491,47 @@ struct dma_device {
 	void (*device_issue_pending)(struct dma_chan *chan);
 };
 
+static inline int dmaengine_device_control(struct dma_chan *chan,
+					   enum dma_ctrl_cmd cmd,
+					   unsigned long arg)
+{
+	return chan->device->device_control(chan, cmd, arg);
+}
+
+static inline int dmaengine_slave_config(struct dma_chan *chan,
+					  struct dma_slave_config *config)
+{
+	return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
+			(unsigned long)config);
+}
+
+static inline int dmaengine_terminate_all(struct dma_chan *chan)
+{
+	return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_data_direction direction,
+		unsigned long flags)
+{
+	return chan->device->device_prep_slave_sg(chan, sgl, sg_len, direction,
+			flags);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_cyclic(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_data_direction direction)
+{
+	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
+			period_len, direction);
+}
+
+static inline int dmaengine_tx_submit(struct dma_async_tx_descriptor *desc)
+{
+	return desc->tx_submit(desc);
+}
+
 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
 {
 	size_t mask;

1.7.1
---
 include/linux/dmaengine.h |   41 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+), 0 deletions(-)
index 0df7864..635c60b 100644
@@ -491,6 +491,47 @@ struct dma_device {
 	void (*device_issue_pending)(struct dma_chan *chan);
 };
 
+static inline int dmaengine_device_control(struct dma_chan *chan,
+					   enum dma_ctrl_cmd cmd,
+					   unsigned long arg)
+{
+	return chan->device->device_control(chan, cmd, arg);
+}
+
+static inline int dmaengine_slave_config(struct dma_chan *chan,
+					  struct dma_slave_config *config)
+{
+	return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
+			(unsigned long)config);
+}
+
+static inline int dmaengine_terminate_all(struct dma_chan *chan)
+{
+	return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_data_direction direction,
+		unsigned long flags)
+{
+	return chan->device->device_prep_slave_sg(chan, sgl, sg_len, direction,
+			flags);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_cyclic(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_data_direction direction)
+{
+	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
+			period_len, direction);
+}
+
+static inline int dmaengine_tx_submit(struct dma_async_tx_descriptor *desc)
+{
+	return desc->tx_submit(desc);
+}
+
 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
 {
 	size_t mask;

1.7.1


_______________________________________________
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Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
---
 include/linux/dmaengine.h |   41 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+), 0 deletions(-)
index 0df7864..635c60b 100644
@@ -491,6 +491,47 @@ struct dma_device {
 	void (*device_issue_pending)(struct dma_chan *chan);
 };
 
+static inline int dmaengine_device_control(struct dma_chan *chan,
+					   enum dma_ctrl_cmd cmd,
+					   unsigned long arg)
+{
+	return chan->device->device_control(chan, cmd, arg);
+}
+
+static inline int dmaengine_slave_config(struct dma_chan *chan,
+					  struct dma_slave_config *config)
+{
+	return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
+			(unsigned long)config);
+}
+
+static inline int dmaengine_terminate_all(struct dma_chan *chan)
+{
+	return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_data_direction direction,
+		unsigned long flags)
+{
+	return chan->device->device_prep_slave_sg(chan, sgl, sg_len, direction,
+			flags);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_cyclic(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_data_direction direction)
+{
+	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
+			period_len, direction);
+}
+
+static inline int dmaengine_tx_submit(struct dma_async_tx_descriptor *desc)
+{
+	return desc->tx_submit(desc);
+}
+
 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
 {
 	size_t mask;

1.7.1
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
index 0df7864..635c60b 100644
@@ -491,6 +491,47 @@ struct dma_device {
 ? ? ? ?void (*device_issue_pending)(struct dma_chan *chan);
 ?};
 
+static inline int dmaengine_device_control(struct dma_chan *chan,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?enum dma_ctrl_cmd cmd,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long arg)
+{
+ ? ? ? return chan->device->device_control(chan, cmd, arg);
+}
+
+static inline int dmaengine_slave_config(struct dma_chan *chan,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_slave_config *config)
+{
+ ? ? ? return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
+ ? ? ? ? ? ? ? ? ? ? ? (unsigned long)config);
+}
+
+static inline int dmaengine_terminate_all(struct dma_chan *chan)
+{
+ ? ? ? return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
+ ? ? ? ? ? ? ? struct dma_chan *chan, struct scatterlist *sgl,
+ ? ? ? ? ? ? ? unsigned int sg_len, enum dma_data_direction direction,
+ ? ? ? ? ? ? ? unsigned long flags)
+{
+ ? ? ? return chan->device->device_prep_slave_sg(chan, sgl, sg_len, direction,
+ ? ? ? ? ? ? ? ? ? ? ? flags);

+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_cyclic(
+ ? ? ? ? ? ? ? struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ ? ? ? ? ? ? ? size_t period_len, enum dma_data_direction direction)
+{
+ ? ? ? return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
+ ? ? ? ? ? ? ? ? ? ? ? period_len, direction);
+}
+

+static inline int dmaengine_tx_submit(struct dma_async_tx_descriptor *desc)
+{
+ ? ? ? return desc->tx_submit(desc);
+}

index 0df7864..635c60b 100644
@@ -491,6 +491,47 @@ struct dma_device {
 ? ? ? ?void (*device_issue_pending)(struct dma_chan *chan);
 ?};
 
+static inline int dmaengine_device_control(struct dma_chan *chan,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?enum dma_ctrl_cmd cmd,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long arg)
+{
+ ? ? ? return chan->device->device_control(chan, cmd, arg);
+}
+
+static inline int dmaengine_slave_config(struct dma_chan *chan,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_slave_config *config)
+{
+ ? ? ? return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
+ ? ? ? ? ? ? ? ? ? ? ? (unsigned long)config);
+}
+
+static inline int dmaengine_terminate_all(struct dma_chan *chan)
+{
+ ? ? ? return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
+ ? ? ? ? ? ? ? struct dma_chan *chan, struct scatterlist *sgl,
+ ? ? ? ? ? ? ? unsigned int sg_len, enum dma_data_direction direction,
+ ? ? ? ? ? ? ? unsigned long flags)
+{
+ ? ? ? return chan->device->device_prep_slave_sg(chan, sgl, sg_len, direction,
+ ? ? ? ? ? ? ? ? ? ? ? flags);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_cyclic(
+ ? ? ? ? ? ? ? struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ ? ? ? ? ? ? ? size_t period_len, enum dma_data_direction direction)

+{
+ ? ? ? return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
+ ? ? ? ? ? ? ? ? ? ? ? period_len, direction);
+}
+

+static inline int dmaengine_tx_submit(struct dma_async_tx_descriptor *desc)
+{
+ ? ? ? return desc->tx_submit(desc);
+}

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
index 0df7864..635c60b 100644
@@ -491,6 +491,47 @@ struct dma_device {
 ? ? ? ?void (*device_issue_pending)(struct dma_chan *chan);
 ?};
 
+static inline int dmaengine_device_control(struct dma_chan *chan,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?enum dma_ctrl_cmd cmd,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long arg)
+{
+ ? ? ? return chan->device->device_control(chan, cmd, arg);
+}
+
+static inline int dmaengine_slave_config(struct dma_chan *chan,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_slave_config *config)
+{
+ ? ? ? return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
+ ? ? ? ? ? ? ? ? ? ? ? (unsigned long)config);
+}
+
+static inline int dmaengine_terminate_all(struct dma_chan *chan)
+{
+ ? ? ? return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
+ ? ? ? ? ? ? ? struct dma_chan *chan, struct scatterlist *sgl,
+ ? ? ? ? ? ? ? unsigned int sg_len, enum dma_data_direction direction,
+ ? ? ? ? ? ? ? unsigned long flags)
+{
+ ? ? ? return chan->device->device_prep_slave_sg(chan, sgl, sg_len, direction,
+ ? ? ? ? ? ? ? ? ? ? ? flags);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_cyclic(
+ ? ? ? ? ? ? ? struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+ ? ? ? ? ? ? ? size_t period_len, enum dma_data_direction direction)

+{
+ ? ? ? return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
+ ? ? ? ? ? ? ? ? ? ? ? period_len, direction);
+}
+

+static inline int dmaengine_tx_submit(struct dma_async_tx_descriptor *desc)
+{
+ ? ? ? return desc->tx_submit(desc);
+}

---
 arch/arm/mach-imx/include/mach/dma-v1.h |    8 +-
 arch/arm/mach-mx3/Kconfig               |    2 +
 arch/arm/plat-mxc/Kconfig               |   10 +
 arch/arm/plat-mxc/include/mach/dma.h    |   64 ++
 arch/arm/plat-mxc/include/mach/sdma.h   |    8 +
 drivers/dma/Kconfig                     |    8 +
 drivers/dma/Makefile                    |    1 +
 drivers/dma/imx-sdma.c                  | 1383 +++++++++++++++++++++++++++++++
 8 files changed, 1478 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/dma.h
 create mode 100644 arch/arm/plat-mxc/include/mach/sdma.h
 create mode 100644 drivers/dma/imx-sdma.c
index 287431c..ac6fd71 100644
@@ -27,6 +27,8 @@
 
 #define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 
+#include <mach/dma.h>
+
 #define IMX_DMA_CHANNELS  16
 
 #define DMA_MODE_READ		0

@@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name);
 
 void imx_dma_free(int channel);
 
-enum imx_dma_prio {
-	DMA_PRIO_HIGH = 0,
-	DMA_PRIO_MEDIUM = 1,
-	DMA_PRIO_LOW = 2
-};
-
 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 
 #endif	/* __MACH_DMA_V1_H__ */

index 85beece..301375c 100644
@@ -3,12 +3,14 @@ if ARCH_MX3
 config ARCH_MX31
 	select ARCH_HAS_RNGA
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 	bool
 
 config ARCH_MX35
 	bool
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 
 comment "MX3 platforms:"
 

index 0527e65..6741625 100644
@@ -109,4 +109,14 @@ config ARCH_MXC_AUDMUX_V1
 config ARCH_MXC_AUDMUX_V2
 	bool
 
+config IMX_HAVE_SDMA
+	bool
+
+config IMX_SDMA
+	depends on IMX_HAVE_SDMA
+	tristate "Enable SDMA support"
+	help
+	  Include support for the SDMA engine. The SDMA engine needs additional
+	  firmware support. SDMA can be compiled as a module to support loading
+	  the firmware when a rootfs is present.
 endif

new file mode 100644
index 0000000..5d542b8
@@ -0,0 +1,8 @@
+#ifndef __MACH_MXC_SDMA_H__
+#define __MACH_MXC_SDMA_H__
+
+struct sdma_platform_data {
+	int sdma_version;
+};
+
+#endif /* __MACH_MXC_SDMA_H__ */

index 9520cf0..f76bda9 100644
@@ -195,6 +195,14 @@ config PCH_DMA
 	help
 	  Enable support for the Topcliff PCH DMA engine.
 
+config IMX_SDMA
+	tristate "Atmel AHB DMA support"
+	depends on ARCH_MXC
+	select DMA_ENGINE
+	help
+	  Support the i.MX SDMA engine. This engine is integrated into
+	  Freescale i.MX25/31/35/51 chips.
+
 config DMA_ENGINE
 	bool
 

index 72bd703..14d7a1b 100644
@@ -25,3 +25,4 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
 obj-$(CONFIG_PCH_DMA) += pch_dma.o
+obj-$(CONFIG_IMX_SDMA) += imx-sdma.o

1.7.1
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */

+
+#ifndef __ASM_ARCH_MXC_DMA_H__
+#define __ASM_ARCH_MXC_DMA_H__
+
+#include <linux/scatterlist.h>
+
+/*
+ * This enumerates peripheral types. Used for SDMA.
+ */
+typedef enum {

+ ? ? ? IMX_DMATYPE_SSI, ? ? ? ?/* MCU domain SSI */
+ ? ? ? IMX_DMATYPE_SSI_SP, ? ? /* Shared SSI */
+ ? ? ? IMX_DMATYPE_MMC, ? ? ? ?/* MMC */
+ ? ? ? IMX_DMATYPE_SDHC, ? ? ? /* SDHC */
+ ? ? ? IMX_DMATYPE_UART, ? ? ? /* MCU domain UART */
+ ? ? ? IMX_DMATYPE_UART_SP, ? ?/* Shared UART */
+ ? ? ? IMX_DMATYPE_FIRI, ? ? ? /* FIRI */
+ ? ? ? IMX_DMATYPE_CSPI, ? ? ? /* MCU domain CSPI */
+ ? ? ? IMX_DMATYPE_CSPI_SP, ? ?/* Shared CSPI */
+ ? ? ? IMX_DMATYPE_SIM, ? ? ? ?/* SIM */
+ ? ? ? IMX_DMATYPE_ATA, ? ? ? ?/* ATA */
+ ? ? ? IMX_DMATYPE_CCM, ? ? ? ?/* CCM */
+ ? ? ? IMX_DMATYPE_EXT, ? ? ? ?/* External peripheral */
+ ? ? ? IMX_DMATYPE_MSHC, ? ? ? /* Memory Stick Host Controller */
+ ? ? ? IMX_DMATYPE_MSHC_SP, ? ?/* Shared Memory Stick Host Controller */
+ ? ? ? IMX_DMATYPE_DSP, ? ? ? ?/* DSP */
+ ? ? ? IMX_DMATYPE_MEMORY, ? ? /* Memory */
+ ? ? ? IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
+ ? ? ? IMX_DMATYPE_SPDIF, ? ? ?/* SPDIF */
+ ? ? ? IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
+ ? ? ? IMX_DMATYPE_ASRC, ? ? ? /* ASRC */
+ ? ? ? IMX_DMATYPE_ESAI, ? ? ? /* ESAI */

+} sdma_peripheral_type;
+
+enum imx_dma_prio {
+ ? ? ? DMA_PRIO_HIGH = 0,
+ ? ? ? DMA_PRIO_MEDIUM = 1,
+ ? ? ? DMA_PRIO_LOW = 2
+};
+
+struct imx_dma_data {
+ ? ? ? int dma_request; /* DMA request line */

+ ? ? ? sdma_peripheral_type peripheral_type;
+ ? ? ? int priority;

+};
+
+static inline int imx_dma_is_ipu(struct dma_chan *chan)
+{
+ ? ? ? return !strcmp(dev_name(chan->device->dev), "ipu-core");
+}
+
+static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
+{
+ ? ? ? return !strcmp(dev_name(chan->device->dev), "imx-sdma");
+}
+
+#endif

new file mode 100644
index 0000000..5d542b8

@@ -0,0 +1,8 @@
+#ifndef __MACH_MXC_SDMA_H__
+#define __MACH_MXC_SDMA_H__
+
+struct sdma_platform_data {
+ ? ? ? int sdma_version;

+};
+
+#endif /* __MACH_MXC_SDMA_H__ */

index 9520cf0..f76bda9 100644
@@ -195,6 +195,14 @@ config PCH_DMA

+config IMX_SDMA
+ ? ? ? tristate "Atmel AHB DMA support"
+ ? ? ? depends on ARCH_MXC
+ ? ? ? select DMA_ENGINE
+ ? ? ? help
+ ? ? ? ? Support the i.MX SDMA engine. This engine is integrated into
+ ? ? ? ? Freescale i.MX25/31/35/51 chips.
+

index 72bd703..14d7a1b 100644
@@ -25,3 +25,4 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o

+obj-$(CONFIG_IMX_SDMA) += imx-sdma.o

new file mode 100644
index 0000000..3ba7905
@@ -0,0 +1,1383 @@
+/*
+ * drivers/dma/imx-sdma.c
+ *
+ * This file contains a driver for the Freescale Smart DMA engine
+ *
+ * Copyright 2010 Sascha Hauer, Pengutronix <[email protected]>
+ *
+ * Based on code from Freescale:
+ *
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/semaphore.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/dmaengine.h>
+
+#include <asm/irq.h>
+#include <mach/sdma.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
+
+/* SDMA registers */
+#define SDMA_H_C0PTR ? ? ? ? ? (sdma_base + 0x000)
+#define SDMA_H_INTR ? ? ? ? ? ?(sdma_base + 0x004)
+#define SDMA_H_STATSTOP ? ? ? ? ? ? ? ?(sdma_base + 0x008)
+#define SDMA_H_START ? ? ? ? ? (sdma_base + 0x00c)
+#define SDMA_H_EVTOVR ? ? ? ? ?(sdma_base + 0x010)
+#define SDMA_H_DSPOVR ? ? ? ? ?(sdma_base + 0x014)
+#define SDMA_H_HOSTOVR ? ? ? ? (sdma_base + 0x018)
+#define SDMA_H_EVTPEND ? ? ? ? (sdma_base + 0x01c)
+#define SDMA_H_DSPENBL ? ? ? ? (sdma_base + 0x020)
+#define SDMA_H_RESET ? ? ? ? ? (sdma_base + 0x024)
+#define SDMA_H_EVTERR ? ? ? ? ?(sdma_base + 0x028)
+#define SDMA_H_INTRMSK ? ? ? ? (sdma_base + 0x02c)
+#define SDMA_H_PSW ? ? ? ? ? ? (sdma_base + 0x030)
+#define SDMA_H_EVTERRDBG ? ? ? (sdma_base + 0x034)
+#define SDMA_H_CONFIG ? ? ? ? ?(sdma_base + 0x038)
+#define SDMA_ONCE_ENB ? ? ? ? ?(sdma_base + 0x040)
+#define SDMA_ONCE_DATA ? ? ? ? (sdma_base + 0x044)
+#define SDMA_ONCE_INSTR ? ? ? ? ? ? ? ?(sdma_base + 0x048)

+#define SDMA_ONCE_STAT ? ? ? ? (sdma_base + 0x04c)
+#define SDMA_ONCE_CMD ? ? ? ? ?(sdma_base + 0x050)
+#define SDMA_EVT_MIRROR ? ? ? ? ? ? ? ?(sdma_base + 0x054)
+#define SDMA_ILLINSTADDR ? ? ? (sdma_base + 0x058)
+#define SDMA_CHN0ADDR ? ? ? ? ?(sdma_base + 0x05c)
+#define SDMA_ONCE_RTB ? ? ? ? ?(sdma_base + 0x060)
+#define SDMA_XTRIG_CONF1 ? ? ? (sdma_base + 0x070)
+#define SDMA_XTRIG_CONF2 ? ? ? (sdma_base + 0x074)
+#define SDMA_CHNENBL_0 ? ? ? ? (sdma_base + (sdma_version == 2 ? 0x200 : 0x80))
+#define SDMA_CHNPRI_0 ? ? ? ? ?(sdma_base + 0x100)

+
+/*
+ * Buffer descriptor status values.
+ */
+#define BD_DONE ?0x01
+#define BD_WRAP ?0x02
+#define BD_CONT ?0x04
+#define BD_INTR ?0x08
+#define BD_RROR ?0x10
+#define BD_LAST ?0x20
+#define BD_EXTD ?0x80
+
+/*
+ * Data Node descriptor status values.
+ */
+#define DND_END_OF_FRAME ?0x80
+#define DND_END_OF_XFER ? 0x40
+#define DND_DONE ? ? ? ? ?0x20
+#define DND_UNUSED ? ? ? ?0x01
+
+/*
+ * IPCV2 descriptor status values.
+ */
+#define BD_IPCV2_END_OF_FRAME ?0x40
+
+#define IPCV2_MAX_NODES ? ? ? ?50
+/*
+ * Error bit set in the CCB status field by the SDMA,
+ * in setbd routine, in case of a transfer error
+ */
+#define DATA_ERROR ?0x10000000
+
+/*
+ * Buffer descriptor commands.
+ */
+#define C0_ADDR ? ? ? ? ? ? 0x01
+#define C0_LOAD ? ? ? ? ? ? 0x02
+#define C0_DUMP ? ? ? ? ? ? 0x03
+#define C0_SETCTX ? ? ? ? ? 0x07
+#define C0_GETCTX ? ? ? ? ? 0x03
+#define C0_SETDM ? ? ? ? ? ?0x01
+#define C0_SETPM ? ? ? ? ? ?0x04
+#define C0_GETDM ? ? ? ? ? ?0x02
+#define C0_GETPM ? ? ? ? ? ?0x08
+/*

+ * Change endianness indicator in the BD command field
+ */
+#define CHANGE_ENDIANNESS ? 0x80
+
+/*
+ * Mode/Count of data node descriptors - IPCv2
+ */
+#ifdef __BIG_ENDIAN
+struct sdma_mode_count {
+ ? ? ? u32 command : ?8; /* command mostlky used for channel 0 */

+ ? ? ? u32 status ?: ?8; /* E,R,I,C,W,D status bits stored here */
+ ? ? ? u32 count ? : 16; /* size of the buffer pointed by this BD */
+};
+#else
+struct sdma_mode_count {
+ ? ? ? u32 count ? : 16; /* size of the buffer pointed by this BD */
+ ? ? ? u32 status ?: ?8; /* E,R,I,C,W,D status bits stored here */
+ ? ? ? u32 command : ?8; /* command mostlky used for channel 0 */
+};
+#endif

+
+/*
+ * Buffer descriptor
+ */
+struct sdma_buffer_descriptor {
+ ? ? ? struct sdma_mode_count ?mode;
+ ? ? ? u32 buffer_addr; ? ?/* address of the buffer described */
+ ? ? ? u32 ext_buffer_addr; /* extended buffer address */

+};
+
+/*
+ * Channel control Block
+ */
+struct sdma_channel_control {
+ ? ? ? u32 current_bd_ptr; /* current buffer descriptor processed */
+ ? ? ? u32 base_bd_ptr; ? ?/* first element of buffer descriptor array */
+ ? ? ? void *unused;
+ ? ? ? void *unused1;

+};
+
+/**
+ * Context structure.
+ */
+#ifdef __BIG_ENDIAN
+struct sdma_state_registers {
+ ? ? ? u32 sf ? ? : 1; /* source fault while loading data */
+ ? ? ? u32 unused0: 1;
+ ? ? ? u32 rpc ? ?:14; /* return program counter */
+ ? ? ? u32 t ? ? ?: 1; /* test bit:status of arithmetic & test instruction*/
+ ? ? ? u32 unused1: 1;
+ ? ? ? u32 pc ? ? :14; /* program counter */
+ ? ? ? u32 lm ? ? : 2; /* loop mode */
+ ? ? ? u32 epc ? ?:14; /* loop end program counter */
+ ? ? ? u32 df ? ? : 1; /* destination fault while storing data */
+ ? ? ? u32 unused2: 1;
+ ? ? ? u32 spc ? ?:14; /* loop start program counter */
+};
+#else
+struct sdma_state_registers {
+ ? ? ? u32 pc ? ? :14; /* program counter */
+ ? ? ? u32 unused1: 1;
+ ? ? ? u32 t ? ? ?: 1; /* test bit: status of arithmetic & test instruction*/

+ ? ? ? u32 rpc ? ?:14; /* return program counter */
+ ? ? ? u32 unused0: 1;
+ ? ? ? u32 sf ? ? : 1; /* source fault while loading data */
+ ? ? ? u32 spc ? ?:14; /* loop start program counter */
+ ? ? ? u32 unused2: 1;
+ ? ? ? u32 df ? ? : 1; /* destination fault while storing data */
+ ? ? ? u32 epc ? ?:14; /* loop end program counter */
+ ? ? ? u32 lm ? ? : 2; /* loop mode */
+};
+#endif

+
+struct sdma_context_data {
+ ? ? ? struct sdma_state_registers ?channel_state; /* channel state bits */
+ ? ? ? u32 ?gReg[8]; /* general registers */
+ ? ? ? u32 ?mda; /* burst dma destination address register */
+ ? ? ? u32 ?msa; /* burst dma source address register */
+ ? ? ? u32 ?ms; ?/* burst dma status ?register */
+ ? ? ? u32 ?md; ?/* burst dma data ? ?register */
+ ? ? ? u32 ?pda; /* peripheral dma destination address register */
+ ? ? ? u32 ?psa; /* peripheral dma source address register */
+ ? ? ? u32 ?ps; ?/* peripheral dma ?status ?register */
+ ? ? ? u32 ?pd; ?/* peripheral dma ?data ? ?register */
+ ? ? ? u32 ?ca; ?/* CRC polynomial ?register */
+ ? ? ? u32 ?cs; ?/* CRC accumulator register */
+ ? ? ? u32 ?dda; /* dedicated core destination address register */
+ ? ? ? u32 ?dsa; /* dedicated core source address register */
+ ? ? ? u32 ?ds; ?/* dedicated core status ?register */
+ ? ? ? u32 ?dd; ?/* dedicated core data ? ?register */
+ ? ? ? u32 ?scratch0;
+ ? ? ? u32 ?scratch1;
+ ? ? ? u32 ?scratch2;

+ ? ? ? u32 ?scratch3;
+ ? ? ? u32 ?scratch4;
+ ? ? ? u32 ?scratch5;
+ ? ? ? u32 ?scratch6;
+ ? ? ? u32 ?scratch7;
+};
+
+struct sdma_channel {
+ ? ? ? /* Channel number */
+ ? ? ? int channel;

+ ? ? ? /* Transfer type. Needed for setting SDMA script */
+ ? ? ? enum dma_data_direction direction;
+ ? ? ? /* Peripheral type. Needed for setting SDMA script */
+ ? ? ? sdma_peripheral_type peripheral_type;
+ ? ? ? /* Peripheral event id */
+ ? ? ? int event_id;

+ ? ? ? /* Peripheral event id2 (for channels that use 2 events) */
+ ? ? ? int event_id2;

+ ? ? ? /* SDMA data access word size */
+ ? ? ? unsigned long word_size;

+
+ ? ? ? /* ID of the buffer that was processed */
+ ? ? ? unsigned int buf_tail;
+
+ ? ? ? wait_queue_head_t waitq; ? ? ? ?/* channel completion waitqeue */
+
+ ? ? ? int num_bd;

+
+ ? ? ? struct sdma_buffer_descriptor *bd;
+ ? ? ? dma_addr_t ? ? ?bd_phys;
+
+ ? ? ? int pc_from_device, pc_to_device;

+
+ ? ? ? unsigned long flags;

+ ? ? ? dma_addr_t per_address;
+
+ ? ? ? uint32_t event_mask1, event_mask2;
+ ? ? ? uint32_t watermark_level;
+ ? ? ? uint32_t shp_addr, per_addr;
+
+ ? ? ? /* DMA-Engine Channel */
+ ? ? ? struct dma_chan chan;
+
+ ? ? ? spinlock_t ? ? ? ? ? ? ?lock;
+ ? ? ? struct dma_async_tx_descriptor desc;
+ ? ? ? dma_cookie_t ? ? ? ? ? ?last_completed;
+ ? ? ? int busy;

+};
+
+#define IMX_DMA_SG_LOOP ? ? ? ? ? ? ? ?(1 << 0)
+
+#define MAX_DMA_CHANNELS 32
+#define MXC_SDMA_DEFAULT_PRIORITY 1
+#define MXC_SDMA_MIN_PRIORITY 1
+#define MXC_SDMA_MAX_PRIORITY 7
+
+/*
+ * This enumerates transfer types
+ */
+typedef enum {

+ ? ? ? emi_2_per = 0, ? ? ? ? ?/* EMI memory to peripheral */
+ ? ? ? emi_2_int, ? ? ? ? ? ? ?/* EMI memory to internal RAM */
+ ? ? ? emi_2_emi, ? ? ? ? ? ? ?/* EMI memory to EMI memory */
+ ? ? ? emi_2_dsp, ? ? ? ? ? ? ?/* EMI memory to DSP memory */
+ ? ? ? per_2_int, ? ? ? ? ? ? ?/* Peripheral to internal RAM */
+ ? ? ? per_2_emi, ? ? ? ? ? ? ?/* Peripheral to internal EMI memory */
+ ? ? ? per_2_dsp, ? ? ? ? ? ? ?/* Peripheral to DSP memory */
+ ? ? ? per_2_per, ? ? ? ? ? ? ?/* Peripheral to Peripheral */
+ ? ? ? int_2_per, ? ? ? ? ? ? ?/* Internal RAM to peripheral */
+ ? ? ? int_2_int, ? ? ? ? ? ? ?/* Internal RAM to Internal RAM */
+ ? ? ? int_2_emi, ? ? ? ? ? ? ?/* Internal RAM to EMI memory */
+ ? ? ? int_2_dsp, ? ? ? ? ? ? ?/* Internal RAM to DSP memory */
+ ? ? ? dsp_2_per, ? ? ? ? ? ? ?/* DSP memory to peripheral */
+ ? ? ? dsp_2_int, ? ? ? ? ? ? ?/* DSP memory to internal RAM */
+ ? ? ? dsp_2_emi, ? ? ? ? ? ? ?/* DSP memory to EMI memory */
+ ? ? ? dsp_2_dsp, ? ? ? ? ? ? ?/* DSP memory to DSP memory */
+ ? ? ? emi_2_dsp_loop, ? ? ? ? /* EMI memory to DSP memory loopback */
+ ? ? ? dsp_2_emi_loop, ? ? ? ? /* DSP memory to EMI memory loopback */
+ ? ? ? dvfs_pll, ? ? ? ? ? ? ? /* DVFS script with PLL change ? ? ? */
+ ? ? ? dvfs_pdr ? ? ? ? ? ? ? ?/* DVFS script without PLL change ? ?*/
+} sdma_transfer_type;
+
+/*
+ * Structure containing sdma request ?parameters.
+ */
+struct sdma_script_start_addrs {
+ ? ? ? int ap_2_ap_addr;
+ ? ? ? int ap_2_bp_addr;
+ ? ? ? int ap_2_ap_fixed_addr;
+ ? ? ? int bp_2_ap_addr;
+ ? ? ? int loopback_on_dsp_side_addr;
+ ? ? ? int mcu_interrupt_only_addr;
+
+ ? ? ? int firi_2_per_addr;
+ ? ? ? int firi_2_mcu_addr;
+ ? ? ? int per_2_firi_addr;
+ ? ? ? int mcu_2_firi_addr;
+
+ ? ? ? int uart_2_per_addr;
+ ? ? ? int uart_2_mcu_addr;
+ ? ? ? int per_2_app_addr;
+ ? ? ? int mcu_2_app_addr;
+ ? ? ? int per_2_per_addr;
+
+ ? ? ? int uartsh_2_per_addr;
+ ? ? ? int uartsh_2_mcu_addr;
+ ? ? ? int per_2_shp_addr;
+ ? ? ? int mcu_2_shp_addr;
+
+ ? ? ? int ata_2_mcu_addr;
+ ? ? ? int mcu_2_ata_addr;
+
+ ? ? ? int app_2_per_addr;
+ ? ? ? int app_2_mcu_addr;
+ ? ? ? int shp_2_per_addr;
+ ? ? ? int shp_2_mcu_addr;
+
+ ? ? ? int mshc_2_mcu_addr;
+ ? ? ? int mcu_2_mshc_addr;
+
+ ? ? ? int spdif_2_mcu_addr;
+ ? ? ? int mcu_2_spdif_addr;
+
+ ? ? ? int asrc_2_mcu_addr;

+
+ ? ? ? int ext_mem_2_ipu_addr;
+
+ ? ? ? int descrambler_addr;
+
+ ? ? ? int dptc_dvfs_addr;
+
+ ? ? ? int utra_addr;
+
+ ? ? ? int ram_code_start_addr;

+};
+
+#define SDMA_FIRMWARE_MAGIC 0x414d4453
+
+struct sdma_firmware_header {
+ ? ? ? uint32_t ? ? ? ?magic; /* "SDMA" */
+ ? ? ? uint32_t ? ? ? ?version_major; ?/* increased whenever layout of struct sdma_script_start_addrs changes */
+ ? ? ? uint32_t ? ? ? ?version_minor; ?/* firmware version */
+ ? ? ? uint32_t ? ? ? ?script_addrs_start; /* offset of struct sdma_script_start_addrs in this image */
+ ? ? ? uint32_t ? ? ? ?num_script_addrs; /* Number of script addresses in this image */
+ ? ? ? uint32_t ? ? ? ?ram_code_start; /* offset of SDMA ram image in this firmware image */
+ ? ? ? uint32_t ? ? ? ?ram_code_size; /* size of SDMA ram image */

+};
+
+static struct sdma_channel sdma_data[MAX_DMA_CHANNELS];
+static struct sdma_channel_control *channel_control;
+static void __iomem *sdma_base;
+static int sdma_version;

+static int sdma_num_events;

+static struct sdma_context_data *sdma_context;
+dma_addr_t sdma_context_phys;
+static struct dma_device __sdma_dma_device;
+static struct dma_device *sdma_dma_device = &__sdma_dma_device;

+
+#define SDMA_H_CONFIG_DSPDMA ? (1 << 12) /* indicates if the DSPDMA is used */
+#define SDMA_H_CONFIG_RTD_PINS (1 << 11) /* indicates if Real-Time Debug pins are enabled */
+#define SDMA_H_CONFIG_ACR ? ? ?(1 << 4) ?/* indicates if AHB freq /core freq = 2 or 1 */
+#define SDMA_H_CONFIG_CSM ? ? ?(3) ? ? ? /* indicates which context switch mode is selected*/
+
+static int sdma_config_ownership(int channel, int event_override,
+ ? ? ? ? ? ? ? ? ?int mcu_verride, int dsp_override)
+{
+ ? ? ? u32 evt, mcu, dsp;
+
+ ? ? ? if (event_override && mcu_verride && dsp_override)
+ ? ? ? ? ? ? ? return -EINVAL;
+
+ ? ? ? evt = readl(SDMA_H_EVTOVR);
+ ? ? ? mcu = readl(SDMA_H_HOSTOVR);
+ ? ? ? dsp = readl(SDMA_H_DSPOVR);
+
+ ? ? ? if (dsp_override)
+ ? ? ? ? ? ? ? dsp &= ~(1 << channel);
+ ? ? ? else
+ ? ? ? ? ? ? ? dsp |= (1 << channel);
+
+ ? ? ? if (event_override)
+ ? ? ? ? ? ? ? evt &= ~(1 << channel);
+ ? ? ? else
+ ? ? ? ? ? ? ? evt |= (1 << channel);
+
+ ? ? ? if (mcu_verride)
+ ? ? ? ? ? ? ? mcu &= ~(1 << channel);
+ ? ? ? else
+ ? ? ? ? ? ? ? mcu |= (1 << channel);
+
+ ? ? ? writel(evt, SDMA_H_EVTOVR);
+ ? ? ? writel(mcu, SDMA_H_HOSTOVR);
+ ? ? ? writel(dsp, SDMA_H_DSPOVR);
+
+ ? ? ? return 0;
+}
+
+/*
+ * sdma_run_channel - run a channel and wait till it's done

+ */
+static int sdma_run_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? int ret;
+
+ ? ? ? writel(1 << channel, SDMA_H_START);
+
+ ? ? ? ret = wait_event_interruptible(sdma->waitq,
+ ? ? ? ? ? ? ? ? ? ? ? !(readl(SDMA_H_STATSTOP) & (1 << channel)));

+ ? ? ? return ret;
+}
+
+static int sdma_load_script(void *buf, int size, u32 address)
+{
+ ? ? ? struct sdma_buffer_descriptor *bd0 = sdma_data[0].bd;
+ ? ? ? void *buf_virt;
+ ? ? ? dma_addr_t buf_phys;
+ ? ? ? int ret;
+
+ ? ? ? buf_virt = dma_alloc_coherent(NULL,
+ ? ? ? ? ? ? ? ? ? ? ? size,
+ ? ? ? ? ? ? ? ? ? ? ? &buf_phys, GFP_KERNEL);
+ ? ? ? if (!buf_virt)
+ ? ? ? ? ? ? ? return -ENOMEM;
+
+ ? ? ? bd0->mode.command = C0_SETPM;
+ ? ? ? bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+ ? ? ? bd0->mode.count = size / 2;
+ ? ? ? bd0->buffer_addr = buf_phys;
+ ? ? ? bd0->ext_buffer_addr = address;
+
+ ? ? ? memcpy(buf_virt, buf, size);
+
+ ? ? ? ret = sdma_run_channel(0);
+

+ ? ? ? dma_free_coherent(NULL, size, buf_virt, buf_phys);
+
+ ? ? ? return ret;
+}
+
+static void sdma_event_enable(int channel, int event)
+{
+ ? ? ? u32 val;
+
+ ? ? ? val = readl(SDMA_CHNENBL_0 + event * 4);

+ ? ? ? val |= (1 << channel);
+ ? ? ? writel(val, SDMA_CHNENBL_0 + event * 4);
+}
+
+static void sdma_event_disable(int channel, int event)
+{
+ ? ? ? u32 val;
+
+ ? ? ? val = readl(SDMA_CHNENBL_0 + event * 4);
+ ? ? ? val &= ~(1 << channel);
+ ? ? ? writel(val, SDMA_CHNENBL_0 + event * 4);

+}
+
+static void mxc_sdma_handle_channel_loop(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];

+ ? ? ? struct sdma_buffer_descriptor *bd;
+ ? ? ? int error = 0;

+
+ ? ? ? /*
+ ? ? ? ?* loop mode. Iterate over descriptors, re-setup them and
+ ? ? ? ?* call callback function.
+ ? ? ? ?*/
+ ? ? ? while (1) {
+ ? ? ? ? ? ? ? bd = &sdma->bd[sdma->buf_tail];
+
+ ? ? ? ? ? ? ? if (bd->mode.status & BD_DONE)
+ ? ? ? ? ? ? ? ? ? ? ? break;
+
+ ? ? ? ? ? ? ? if (bd->mode.status & BD_RROR)
+ ? ? ? ? ? ? ? ? ? ? ? error = -EIO;
+
+ ? ? ? ? ? ? ? bd->mode.status |= BD_DONE;
+ ? ? ? ? ? ? ? sdma->buf_tail++;
+ ? ? ? ? ? ? ? sdma->buf_tail %= sdma->num_bd;
+
+ ? ? ? ? ? ? ? if (sdma->desc.callback)
+ ? ? ? ? ? ? ? ? ? ? ? sdma->desc.callback(sdma->desc.callback_param);
+ ? ? ? }
+}
+
+static void mxc_sdma_handle_channel_normal(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? struct sdma_buffer_descriptor *bd;
+ ? ? ? int i, error = 0;
+
+ ? ? ? /*
+ ? ? ? ?* non loop mode. Iterate over all descriptors, collect
+ ? ? ? ?* errors and call callback function
+ ? ? ? ?*/
+ ? ? ? for (i = 0; i < sdma->num_bd; i++) {
+ ? ? ? ? ? ? ? bd = &sdma->bd[i];

+
+ ? ? ? ? ? ? ? ?if (bd->mode.status & (BD_DONE | BD_RROR))
+ ? ? ? ? ? ? ? ? ? ? ? error = -EIO;
+ ? ? ? }
+
+ ? ? ? if (sdma->desc.callback)
+ ? ? ? ? ? ? ? sdma->desc.callback(sdma->desc.callback_param);
+ ? ? ? sdma->last_completed = sdma->desc.cookie;
+
+ ? ? ? sdma->busy = 0;

+}
+
+static void mxc_sdma_handle_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+
+ ? ? ? wake_up_interruptible(&sdma->waitq);
+
+ ? ? ? /* not interested in channel 0 interrupts */
+ ? ? ? if (!channel)
+ ? ? ? ? ? ? ? return;
+
+ ? ? ? if (sdma->flags & IMX_DMA_SG_LOOP)
+ ? ? ? ? ? ? ? mxc_sdma_handle_channel_loop(channel);
+ ? ? ? else
+ ? ? ? ? ? ? ? mxc_sdma_handle_channel_normal(channel);
+}
+
+static irqreturn_t sdma_int_handler(int irq, void *dev_id)
+{
+ ? ? ? u32 stat;
+
+ ? ? ? stat = readl(SDMA_H_INTR);
+ ? ? ? writel(stat, SDMA_H_INTR);
+
+ ? ? ? while (stat) {
+ ? ? ? ? ? ? ? int channel = fls(stat) - 1;
+
+ ? ? ? ? ? ? ? mxc_sdma_handle_channel(channel);
+
+ ? ? ? ? ? ? ? stat &= ~(1 << channel);
+ ? ? ? }
+
+ ? ? ? return IRQ_HANDLED;
+}
+
+static struct clk *sdma_clk;
+
+/*
+ * Stores the start address of the SDMA scripts
+ */
+static struct sdma_script_start_addrs __sdma_script_addrs;
+static struct sdma_script_start_addrs *sdma_script_addrs = &__sdma_script_addrs;
+
+/*
+ * sets the pc of SDMA script according to the peripheral type
+ */

+static void sdma_get_pc(struct sdma_channel *sdma,
+ ? ? ? ? ? ? ? sdma_peripheral_type peripheral_type)
+{
+ ? ? ? int res = 0;
+ ? ? ? int per_2_emi = 0, emi_2_per = 0;
+ ? ? ? int per_2_int = 0, int_2_per = 0;
+ ? ? ? int per_2_per = 0, emi_2_emi = 0;
+
+ ? ? ? sdma->pc_from_device = 0;
+ ? ? ? sdma->pc_to_device = 0;

+
+ ? ? ? switch (peripheral_type) {
+ ? ? ? case IMX_DMATYPE_MEMORY:
+ ? ? ? ? ? ? ? emi_2_emi = sdma_script_addrs->ap_2_ap_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_DSP:
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->bp_2_ap_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->ap_2_bp_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_FIRI:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->firi_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->firi_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_firi_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_firi_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_UART:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->uart_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->uart_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_app_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_app_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_UART_SP:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->uartsh_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->uartsh_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_shp_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_shp_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_ATA:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->ata_2_mcu_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_ata_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_CSPI:
+ ? ? ? case IMX_DMATYPE_EXT:
+ ? ? ? case IMX_DMATYPE_SSI:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->app_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->app_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_app_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_app_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_SSI_SP:
+ ? ? ? case IMX_DMATYPE_MMC:
+ ? ? ? case IMX_DMATYPE_SDHC:
+ ? ? ? case IMX_DMATYPE_CSPI_SP:
+ ? ? ? case IMX_DMATYPE_ESAI:
+ ? ? ? case IMX_DMATYPE_MSHC_SP:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->shp_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->shp_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_shp_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_shp_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_ASRC:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->asrc_2_mcu_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->asrc_2_mcu_addr;
+ ? ? ? ? ? ? ? per_2_per = sdma_script_addrs->per_2_per_addr;

+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_MSHC:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->mshc_2_mcu_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_mshc_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_CCM:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->dptc_dvfs_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_FIFO_MEMORY:
+ ? ? ? ? ? ? ? res = sdma_script_addrs->ap_2_ap_fixed_addr;

+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_SPDIF:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->spdif_2_mcu_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_spdif_addr;

+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_IPU_MEMORY:
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->ext_mem_2_ipu_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? default:
+ ? ? ? ? ? ? ? break;
+ ? ? ? }
+
+ ? ? ? sdma->pc_from_device = per_2_emi;
+ ? ? ? sdma->pc_to_device = emi_2_per;

+}
+
+static int sdma_load_context(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? int load_address;
+ ? ? ? struct sdma_buffer_descriptor *bd0 = sdma_data[0].bd;
+ ? ? ? int ret;
+
+ ? ? ? if (sdma->direction == DMA_FROM_DEVICE) {
+ ? ? ? ? ? ? ? load_address = sdma->pc_from_device;
+ ? ? ? } else {
+ ? ? ? ? ? ? ? load_address = sdma->pc_to_device;
+ ? ? ? }

+
+ ? ? ? if (load_address < 0)
+ ? ? ? ? ? ? ? return load_address;
+
+ ? ? ? pr_debug("%s: load_address = %d\n", __func__, load_address);
+ ? ? ? pr_debug("%s: wml = 0x%08x\n", __func__, sdma->watermark_level);
+ ? ? ? pr_debug("%s: shp_addr = 0x%08x\n", __func__, sdma->shp_addr);
+ ? ? ? pr_debug("%s: per_addr = 0x%08x\n", __func__, sdma->per_addr);
+ ? ? ? pr_debug("%s: event_mask1 = 0x%08x\n", __func__, sdma->event_mask1);
+ ? ? ? pr_debug("%s: event_mask2 = 0x%08x\n", __func__, sdma->event_mask2);

+
+ ? ? ? memset(sdma_context, 0, sizeof(*sdma_context));
+ ? ? ? sdma_context->channel_state.pc = load_address;
+
+ ? ? ? /* Send by context the event mask,base address for peripheral
+ ? ? ? ?* and watermark level
+ ? ? ? ?*/
+ ? ? ? sdma_context->gReg[0] = sdma->event_mask2;
+ ? ? ? sdma_context->gReg[1] = sdma->event_mask1;
+ ? ? ? sdma_context->gReg[2] = sdma->per_addr;
+ ? ? ? sdma_context->gReg[6] = sdma->shp_addr;
+ ? ? ? sdma_context->gReg[7] = sdma->watermark_level;
+
+ ? ? ? bd0->mode.command = C0_SETDM;
+ ? ? ? bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+ ? ? ? bd0->mode.count = sizeof(*sdma_context) / 4;
+ ? ? ? bd0->buffer_addr = sdma_context_phys;
+ ? ? ? bd0->ext_buffer_addr = 2048 + (sizeof(*sdma_context) / 4) * channel;
+
+ ? ? ? ret = sdma_run_channel(0);
+
+ ? ? ? return ret;
+}
+
+static void sdma_disable_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+
+ ? ? ? writel(1 << channel, SDMA_H_STATSTOP);
+ ? ? ? sdma->busy = 0;
+}
+
+static int sdma_config_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? int ret;
+
+ ? ? ? sdma_disable_channel(channel);
+
+ ? ? ? sdma->event_mask1 = 0;

+ ? ? ? sdma->event_mask2 = 0;
+ ? ? ? sdma->shp_addr = 0;
+ ? ? ? sdma->per_addr = 0;
+
+ ? ? ? if (sdma->event_id)
+ ? ? ? ? ? ? ? sdma_event_enable(channel, sdma->event_id);
+
+ ? ? ? switch (sdma->peripheral_type) {
+ ? ? ? case IMX_DMATYPE_DSP:
+ ? ? ? ? ? ? ? sdma_config_ownership(channel, 0, 1, 1);

+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_MEMORY:
+ ? ? ? ? ? ? ? sdma_config_ownership(channel, 0, 1, 0);
+ ? ? ? ? ? ? ? break;
+ ? ? ? default:
+ ? ? ? ? ? ? ? sdma_config_ownership(channel, 1, 1, 0);
+ ? ? ? ? ? ? ? break;
+ ? ? ? }
+
+ ? ? ? sdma_get_pc(sdma, sdma->peripheral_type);
+
+ ? ? ? if ((sdma->peripheral_type != IMX_DMATYPE_MEMORY) &&
+ ? ? ? ? ? ? ? ? ? ? ? (sdma->peripheral_type != IMX_DMATYPE_DSP)) {
+ ? ? ? ? ? ? ? /* Handle multiple event channels differently */
+ ? ? ? ? ? ? ? if (sdma->event_id2) {
+ ? ? ? ? ? ? ? ? ? ? ? sdma->event_mask2 = 1 << (sdma->event_id2 % 32);
+ ? ? ? ? ? ? ? ? ? ? ? if (sdma->event_id2 > 31)
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sdma->watermark_level |= 1 << 31;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->event_mask1 = 1 << (sdma->event_id % 32);
+ ? ? ? ? ? ? ? ? ? ? ? if (sdma->event_id > 31)
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sdma->watermark_level |= 1 << 30;
+ ? ? ? ? ? ? ? } else {
+ ? ? ? ? ? ? ? ? ? ? ? sdma->event_mask1 = 1 << sdma->event_id;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->event_mask2 = 1 << (sdma->event_id - 32);
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? /* Watermark Level */
+ ? ? ? ? ? ? ? sdma->watermark_level |= sdma->watermark_level;
+ ? ? ? ? ? ? ? /* Address */
+ ? ? ? ? ? ? ? sdma->shp_addr = sdma->per_address;
+ ? ? ? } else {
+ ? ? ? ? ? ? ? sdma->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
+ ? ? ? }
+
+ ? ? ? ret = sdma_load_context(channel);
+
+ ? ? ? return ret;
+}
+
+static int sdma_set_channel_priority(unsigned int channel, unsigned int priority)
+{
+ ? ? ? if (priority < MXC_SDMA_MIN_PRIORITY
+ ? ? ? ? ? || priority > MXC_SDMA_MAX_PRIORITY) {
+ ? ? ? ? ? ? ? return -EINVAL;
+ ? ? ? }
+
+ ? ? ? writel(priority, SDMA_CHNPRI_0 + 4 * channel);
+
+ ? ? ? return 0;
+}
+
+static int sdma_request_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? int ret = -EBUSY;
+
+ ? ? ? sdma->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdma->bd_phys, GFP_KERNEL);
+ ? ? ? if (!sdma->bd) {

+ ? ? ? ? ? ? ? ret = -ENOMEM;
+ ? ? ? ? ? ? ? goto out;
+ ? ? ? }
+
+ ? ? ? memset(sdma->bd, 0, PAGE_SIZE);
+
+ ? ? ? channel_control[channel].base_bd_ptr = sdma->bd_phys;
+ ? ? ? channel_control[channel].current_bd_ptr = sdma->bd_phys;
+
+ ? ? ? clk_enable(sdma_clk);

+
+ ? ? ? sdma_set_channel_priority(channel, MXC_SDMA_DEFAULT_PRIORITY);
+
+ ? ? ? init_waitqueue_head(&sdma->waitq);
+
+ ? ? ? sdma->buf_tail = 0;
+
+ ? ? ? return 0;
+out:
+
+ ? ? ? return ret;
+}
+
+static void sdma_enable_channel(int channel)
+{
+ ? ? ? writel(1 << channel, SDMA_H_START);
+}
+
+static int __init sdma_init(unsigned long phys_base, int irq, int version,
+ ? ? ? ? ? ? ? void *ram_code,
+ ? ? ? ? ? ? ? int ram_code_size)
+{
+ ? ? ? int i, ret;
+ ? ? ? int channel;
+ ? ? ? dma_addr_t ccb_phys;
+
+ ? ? ? sdma_version = version;
+ ? ? ? switch (sdma_version) {
+ ? ? ? case 1:
+ ? ? ? ? ? ? ? sdma_num_events = 32;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case 2:

+ ? ? ? ? ? ? ? sdma_num_events = 48;
+ ? ? ? ? ? ? ? break;
+ ? ? ? default:
+ ? ? ? ? ? ? ? pr_err("SDMA: Unknown version %d. aborting\n", sdma_version);
+ ? ? ? ? ? ? ? return -ENODEV;
+ ? ? ? }
+
+ ? ? ? clk_enable(sdma_clk);
+
+ ? ? ? sdma_base = ioremap(phys_base, 4096);

+ ? ? ? if (!sdma_base) {
+ ? ? ? ? ? ? ? ret = -ENOMEM;
+ ? ? ? ? ? ? ? goto err_ioremap;
+ ? ? ? }
+
+ ? ? ? /* Initialize SDMA private data */
+ ? ? ? memset(sdma_data, 0, sizeof(struct sdma_channel) * MAX_DMA_CHANNELS);
+
+ ? ? ? for (channel = 0; channel < MAX_DMA_CHANNELS; channel++)
+ ? ? ? ? ? ? ? sdma_data[channel].channel = channel;
+
+ ? ? ? ret = request_irq(irq, sdma_int_handler, 0, "sdma", NULL);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_request_irq;
+
+ ? ? ? /* Be sure SDMA has not started yet */
+ ? ? ? writel(0, SDMA_H_C0PTR);
+
+ ? ? ? channel_control = dma_alloc_coherent(NULL,
+ ? ? ? ? ? ? ? ? ? ? ? MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
+ ? ? ? ? ? ? ? ? ? ? ? sizeof(struct sdma_context_data),
+ ? ? ? ? ? ? ? ? ? ? ? &ccb_phys, GFP_KERNEL);
+
+ ? ? ? if (!channel_control) {
+ ? ? ? ? ? ? ? ret = -ENOMEM;
+ ? ? ? ? ? ? ? goto err_dma_alloc;
+ ? ? ? }
+
+ ? ? ? sdma_context = (void *)channel_control +
+ ? ? ? ? ? ? ? MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
+ ? ? ? sdma_context_phys = ccb_phys +
+ ? ? ? ? ? ? ? MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
+
+ ? ? ? /* Zero-out the CCB structures array just allocated */
+ ? ? ? memset(channel_control, 0,
+ ? ? ? ? ? ? ? ? ? ? ? MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
+
+ ? ? ? /* disable all channels */
+ ? ? ? for (i = 0; i < sdma_num_events; i++)
+ ? ? ? ? ? ? ? writel(0, SDMA_CHNENBL_0 + i * 4);
+
+ ? ? ? /* All channels have priority 0 */
+ ? ? ? for (i = 0; i < MAX_DMA_CHANNELS; i++)
+ ? ? ? ? ? ? ? writel(0, SDMA_CHNPRI_0 + i * 4);
+
+ ? ? ? ret = sdma_request_channel(0);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_dma_alloc;
+
+ ? ? ? sdma_config_ownership(0, 0, 1, 0);
+
+ ? ? ? /* Set Command Channel (Channel Zero) */
+ ? ? ? writel(0x4050, SDMA_CHN0ADDR);
+
+ ? ? ? /* Set bits of CONFIG register but with static context switching */
+ ? ? ? /* FIXME: Check whether to set ACR bit depending on clock ratios */
+ ? ? ? writel(0, SDMA_H_CONFIG);
+
+ ? ? ? writel(ccb_phys, SDMA_H_C0PTR);
+
+ ? ? ? /* download the RAM image for SDMA */
+ ? ? ? sdma_load_script(ram_code,
+ ? ? ? ? ? ? ? ? ? ? ? ram_code_size,
+ ? ? ? ? ? ? ? ? ? ? ? sdma_script_addrs->ram_code_start_addr);
+
+ ? ? ? /* Set bits of CONFIG register with given context switching mode */
+ ? ? ? writel(SDMA_H_CONFIG_CSM, SDMA_H_CONFIG);
+
+ ? ? ? /* Initializes channel's priorities */
+ ? ? ? sdma_set_channel_priority(0, 7);
+
+ ? ? ? clk_disable(sdma_clk);
+
+ ? ? ? return 0;
+
+err_dma_alloc:
+ ? ? ? free_irq(irq, NULL);
+err_request_irq:
+ ? ? ? iounmap(sdma_base);
+err_ioremap:
+ ? ? ? clk_disable(sdma_clk);
+ ? ? ? pr_err("%s failed with %d\n", __func__, ret);
+ ? ? ? return ret;
+}
+
+static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdma)
+{
+ ? ? ? dma_cookie_t cookie = sdma->chan.cookie;
+
+ ? ? ? if (++cookie < 0)
+ ? ? ? ? ? ? ? cookie = 1;
+
+ ? ? ? sdma->chan.cookie = cookie;
+ ? ? ? sdma->desc.cookie = cookie;
+
+ ? ? ? return cookie;
+}
+
+static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
+{
+ ? ? ? return container_of(chan, struct sdma_channel, chan);
+}
+
+static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(tx->chan);
+ ? ? ? dma_cookie_t cookie;
+
+ ? ? ? spin_lock_irq(&sdma->lock);
+
+ ? ? ? cookie = sdma_assign_cookie(sdma);
+
+ ? ? ? sdma_enable_channel(tx->chan->chan_id);
+
+ ? ? ? spin_unlock_irq(&sdma->lock);
+
+ ? ? ? return cookie;
+}
+
+static int sdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? struct imx_dma_data *data = chan->private;
+ ? ? ? int prio, ret;
+

+ ? ? ? /* No need to execute this for internal channel 0 */
+ ? ? ? if (!chan->chan_id)
+ ? ? ? ? ? ? ? return 0;
+
+ ? ? ? if (!data)
+ ? ? ? ? ? ? ? return -EINVAL;
+
+ ? ? ? switch (data->priority) {
+ ? ? ? case DMA_PRIO_HIGH:
+ ? ? ? ? ? ? ? prio = 3;

+ ? ? ? ? ? ? ? break;
+ ? ? ? case DMA_PRIO_MEDIUM:
+ ? ? ? ? ? ? ? prio = 2;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case DMA_PRIO_LOW:
+ ? ? ? default:
+ ? ? ? ? ? ? ? prio = 1;
+ ? ? ? ? ? ? ? break;
+ ? ? ? }
+
+ ? ? ? sdma->peripheral_type = data->peripheral_type;
+ ? ? ? sdma->event_id = data->dma_request;
+ ? ? ? ret = sdma_set_channel_priority(chan->chan_id, prio);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? return ret;
+
+ ? ? ? if (chan->chan_id) {
+ ? ? ? ? ? ? ? ret = sdma_request_channel(chan->chan_id);
+ ? ? ? ? ? ? ? if (ret)
+ ? ? ? ? ? ? ? ? ? ? ? return ret;
+ ? ? ? }
+
+ ? ? ? dma_async_tx_descriptor_init(&sdma->desc, chan);
+ ? ? ? sdma->desc.tx_submit = sdma_tx_submit;
+ ? ? ? /* txd.flags will be overwritten in prep funcs */
+ ? ? ? sdma->desc.flags = DMA_CTRL_ACK;
+
+ ? ? ? return 0;
+}
+
+static void sdma_free_chan_resources(struct dma_chan *chan)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? int channel = chan->chan_id;
+
+ ? ? ? sdma_disable_channel(channel);
+
+ ? ? ? if (sdma->event_id)
+ ? ? ? ? ? ? ? sdma_event_disable(channel, sdma->event_id);
+ ? ? ? if (sdma->event_id2)
+ ? ? ? ? ? ? ? sdma_event_disable(channel, sdma->event_id2);
+
+ ? ? ? sdma->event_id = 0;
+ ? ? ? sdma->event_id2 = 0;
+
+ ? ? ? sdma_set_channel_priority(channel, 0);
+
+ ? ? ? dma_free_coherent(NULL, PAGE_SIZE, sdma->bd, sdma->bd_phys);
+
+ ? ? ? clk_disable(sdma_clk);
+}
+
+#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
+
+static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
+ ? ? ? ? ? ? ? struct dma_chan *chan, struct scatterlist *sgl,
+ ? ? ? ? ? ? ? unsigned int sg_len, enum dma_data_direction direction,
+ ? ? ? ? ? ? ? unsigned long flags)
+{

+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? int ret, i, count;
+ ? ? ? int channel = chan->chan_id;
+ ? ? ? struct scatterlist *sg;
+
+ ? ? ? if (sdma->busy)
+ ? ? ? ? ? ? ? return NULL;
+ ? ? ? sdma->busy = 1;
+
+ ? ? ? sdma->flags = 0;

+
+ ? ? ? pr_debug("SDMA: setting up %d entries for channel %d.\n",
+ ? ? ? ? ? ? ? ? ? ? ? sg_len, channel);
+
+ ? ? ? sdma->direction = direction;
+ ? ? ? ret = sdma_load_context(channel);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_out;
+
+ ? ? ? if (sg_len > NUM_BD) {
+ ? ? ? ? ? ? ? pr_err("SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? channel, sg_len, NUM_BD);
+ ? ? ? ? ? ? ? ret = -EINVAL;
+ ? ? ? ? ? ? ? goto err_out;
+ ? ? ? }
+
+ ? ? ? for_each_sg(sgl, sg, sg_len, i) {
+ ? ? ? ? ? ? ? struct sdma_buffer_descriptor *bd = &sdma->bd[i];
+ ? ? ? ? ? ? ? int param;
+
+ ? ? ? ? ? ? ? bd->buffer_addr = sgl->dma_address;
+
+ ? ? ? ? ? ? ? count = sg->length;
+
+ ? ? ? ? ? ? ? if (count > 0xffff) {
+ ? ? ? ? ? ? ? ? ? ? ? pr_err("SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? channel, count, 0xffff);
+ ? ? ? ? ? ? ? ? ? ? ? ret = -EINVAL;
+ ? ? ? ? ? ? ? ? ? ? ? goto err_out;
+ ? ? ? ? ? ? ? }
+
+ ? ? ? ? ? ? ? bd->mode.count = count;
+
+ ? ? ? ? ? ? ? if (sdma->word_size > 4) {
+ ? ? ? ? ? ? ? ? ? ? ? ret = ?-EINVAL;
+ ? ? ? ? ? ? ? ? ? ? ? goto err_out;
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? if (sdma->word_size == 4)
+ ? ? ? ? ? ? ? ? ? ? ? bd->mode.command = 0;
+ ? ? ? ? ? ? ? else
+ ? ? ? ? ? ? ? ? ? ? ? bd->mode.command = sdma->word_size;
+
+ ? ? ? ? ? ? ? param = BD_DONE | BD_EXTD | BD_CONT;
+
+ ? ? ? ? ? ? ? if (sdma->flags & IMX_DMA_SG_LOOP) {
+ ? ? ? ? ? ? ? ? ? ? ? param |= BD_INTR;
+ ? ? ? ? ? ? ? ? ? ? ? if (i + 1 == sg_len)
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param |= BD_WRAP;
+ ? ? ? ? ? ? ? }
+
+ ? ? ? ? ? ? ? if (i + 1 == sg_len)
+ ? ? ? ? ? ? ? ? ? ? ? param |= BD_INTR;
+
+ ? ? ? ? ? ? ? pr_debug("entry %d: count: %d dma: 0x%08x %s%s\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i, count, sg->dma_address,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param & BD_WRAP ? "wrap" : "",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param & BD_INTR ? " intr" : "");
+
+ ? ? ? ? ? ? ? bd->mode.status = param;
+ ? ? ? }
+
+ ? ? ? sdma->num_bd = sg_len;
+ ? ? ? channel_control[channel].current_bd_ptr = sdma->bd_phys;
+
+ ? ? ? return &sdma->desc;
+err_out:
+ ? ? ? return NULL;
+}
+

+static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
+ ? ? ? ? ? ? ? struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
+ ? ? ? ? ? ? ? size_t period_len, enum dma_data_direction direction)
+{
+ ? ? ? int num_periods = buf_len / period_len;
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? int channel = chan->chan_id;
+ ? ? ? int ret, i = 0, buf = 0;
+
+ ? ? ? pr_debug("%s channel: %d\n", __func__, channel);

+
+ ? ? ? if (sdma->busy)
+ ? ? ? ? ? ? ? return NULL;
+
+ ? ? ? sdma->busy = 1;
+
+ ? ? ? sdma->flags |= IMX_DMA_SG_LOOP;
+ ? ? ? sdma->direction = direction;
+ ? ? ? ret = sdma_load_context(channel);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_out;
+
+ ? ? ? if (num_periods > NUM_BD) {
+ ? ? ? ? ? ? ? pr_err("SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? channel, num_periods, NUM_BD);
+ ? ? ? ? ? ? ? goto err_out;
+ ? ? ? }
+
+ ? ? ? if (period_len > 0xffff) {
+ ? ? ? ? ? ? ? pr_err("SDMA channel %d: maximum period size exceeded: %d > %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? channel, period_len, 0xffff);
+ ? ? ? ? ? ? ? goto err_out;
+ ? ? ? }
+
+ ? ? ? while (buf < buf_len) {
+ ? ? ? ? ? ? ? struct sdma_buffer_descriptor *bd = &sdma->bd[i];
+ ? ? ? ? ? ? ? int param;
+
+ ? ? ? ? ? ? ? bd->buffer_addr = dma_addr;
+
+ ? ? ? ? ? ? ? bd->mode.count = period_len;
+
+ ? ? ? ? ? ? ? if (sdma->word_size > 4)
+ ? ? ? ? ? ? ? ? ? ? ? goto err_out;
+ ? ? ? ? ? ? ? if (sdma->word_size == 4)
+ ? ? ? ? ? ? ? ? ? ? ? bd->mode.command = 0;
+ ? ? ? ? ? ? ? else
+ ? ? ? ? ? ? ? ? ? ? ? bd->mode.command = sdma->word_size;
+
+ ? ? ? ? ? ? ? param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
+ ? ? ? ? ? ? ? if (i + 1 == num_periods)
+ ? ? ? ? ? ? ? ? ? ? ? param |= BD_WRAP;
+
+ ? ? ? ? ? ? ? pr_debug("entry %d: count: %d dma: 0x%08x %s%s\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i, period_len, dma_addr,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param & BD_WRAP ? "wrap" : "",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param & BD_INTR ? " intr" : "");
+
+ ? ? ? ? ? ? ? bd->mode.status = param;
+
+ ? ? ? ? ? ? ? dma_addr += period_len;
+ ? ? ? ? ? ? ? buf += period_len;
+
+ ? ? ? ? ? ? ? i++;
+ ? ? ? }
+
+ ? ? ? sdma->num_bd = num_periods;
+ ? ? ? channel_control[channel].current_bd_ptr = sdma->bd_phys;
+
+ ? ? ? return &sdma->desc;
+err_out:
+ ? ? ? sdma->busy = 0;
+ ? ? ? return NULL;
+}
+
+static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ ? ? ? ? ? ? ? unsigned long arg)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? struct dma_slave_config *dmaengine_cfg = (void *)arg;
+
+ ? ? ? switch (cmd) {
+ ? ? ? case DMA_TERMINATE_ALL:
+ ? ? ? ? ? ? ? sdma_disable_channel(chan->chan_id);
+ ? ? ? ? ? ? ? return 0;
+ ? ? ? case DMA_SLAVE_CONFIG:
+ ? ? ? ? ? ? ? if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
+ ? ? ? ? ? ? ? ? ? ? ? sdma->per_address = dmaengine_cfg->src_addr;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->watermark_level = dmaengine_cfg->src_maxburst;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->word_size = dmaengine_cfg->src_addr_width;
+ ? ? ? ? ? ? ? } else {
+ ? ? ? ? ? ? ? ? ? ? ? sdma->per_address = dmaengine_cfg->dst_addr;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->watermark_level = dmaengine_cfg->dst_maxburst;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->word_size = dmaengine_cfg->dst_addr_width;
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? return sdma_config_channel(chan->chan_id);
+ ? ? ? default:
+ ? ? ? ? ? ? ? return -ENOSYS;
+ ? ? ? }
+
+ ? ? ? return -EINVAL;
+}
+
+static enum dma_status sdma_tx_status(struct dma_chan *chan,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_cookie_t cookie,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_tx_state *txstate)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? dma_cookie_t last_used;
+ ? ? ? enum dma_status ret;
+
+ ? ? ? last_used = chan->cookie;
+
+ ? ? ? ret = dma_async_is_complete(cookie, sdma->last_completed, last_used);
+ ? ? ? dma_set_tx_state(txstate, sdma->last_completed, last_used, 0);
+
+ ? ? ? return ret;
+}
+
+static void sdma_issue_pending(struct dma_chan *chan)
+{
+ ? ? ? /*
+ ? ? ? ?* Nothing to do. We only have a single descriptor
+ ? ? ? ?*/
+}
+
+static int __devinit sdma_probe(struct platform_device *pdev)
+{
+ ? ? ? int ret;
+ ? ? ? const struct firmware *fw;
+ ? ? ? const struct sdma_firmware_header *header;
+ ? ? ? const struct sdma_script_start_addrs *addr;
+ ? ? ? int irq;
+ ? ? ? unsigned short *ram_code;
+ ? ? ? struct resource *iores;
+ ? ? ? struct sdma_platform_data *pdata = pdev->dev.platform_data;
+ ? ? ? int version;
+ ? ? ? char *cpustr, *fwname;
+ ? ? ? int i;
+ ? ? ? dma_cap_mask_t mask;
+
+ ? ? ? /* there can be only one */
+ ? ? ? BUG_ON(sdma_base);
+
+ ? ? ? iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ? ? ? irq = platform_get_irq(pdev, 0);
+ ? ? ? if (!iores || irq < 0 || !pdata)
+ ? ? ? ? ? ? ? return -EINVAL;
+
+ ? ? ? sdma_clk = clk_get(&pdev->dev, NULL);
+ ? ? ? if (IS_ERR(sdma_clk)) {
+ ? ? ? ? ? ? ? ret = PTR_ERR(sdma_clk);
+ ? ? ? ? ? ? ? goto err_clk;
+ ? ? ? }
+
+ ? ? ? if (cpu_is_mx31()) {
+ ? ? ? ? ? ? ? cpustr = "imx31";
+ ? ? ? ? ? ? ? version = mx31_revision() >> 4;
+ ? ? ? } else if (cpu_is_mx35()) {
+ ? ? ? ? ? ? ? cpustr = "imx35";
+/* FIXME: ? ? ?version = mx35_revision(); */
+ ? ? ? ? ? ? ? version = 2;
+ ? ? ? } else {
+ ? ? ? ? ? ? ? ret = -EINVAL;
+ ? ? ? ? ? ? ? goto err_cputype;
+ ? ? ? }
+
+ ? ? ? fwname = kasprintf(GFP_KERNEL, "sdma-%s-to%d.bin", cpustr, version);
+ ? ? ? if (!fwname) {
+ ? ? ? ? ? ? ? ret = -ENOMEM;
+ ? ? ? ? ? ? ? goto err_cputype;
+ ? ? ? }
+
+ ? ? ? ret = request_firmware(&fw, fwname, &pdev->dev);
+ ? ? ? if (ret) {
+ ? ? ? ? ? ? ? dev_err(&pdev->dev, "request firmware \"%s\" failed with %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fwname, ret);
+ ? ? ? ? ? ? ? kfree(fwname);
+ ? ? ? ? ? ? ? goto err_cputype;
+ ? ? ? }
+ ? ? ? kfree(fwname);
+
+ ? ? ? if (fw->size < sizeof(*header))
+ ? ? ? ? ? ? ? goto err_firmware;
+
+ ? ? ? header = (struct sdma_firmware_header *)fw->data;
+
+ ? ? ? if (header->magic != SDMA_FIRMWARE_MAGIC)
+ ? ? ? ? ? ? ? goto err_firmware;
+ ? ? ? if (header->ram_code_start + header->ram_code_size > fw->size)
+ ? ? ? ? ? ? ? goto err_firmware;
+
+ ? ? ? addr = (void *)header + header->script_addrs_start;
+ ? ? ? ram_code = (void *)header + header->ram_code_start;
+ ? ? ? memcpy(&__sdma_script_addrs, addr, sizeof(*addr));
+
+ ? ? ? ret = sdma_init(iores->start, irq, pdata->sdma_version,
+ ? ? ? ? ? ? ? ? ? ? ? ram_code, header->ram_code_size);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_firmware;
+
+ ? ? ? INIT_LIST_HEAD(&sdma_dma_device->channels);
+
+ ? ? ? /* Initialize channel parameters */
+ ? ? ? for (i = 0; i < MAX_DMA_CHANNELS; i++) {
+ ? ? ? ? ? ? ? struct sdma_channel *sdma = &sdma_data[i];
+
+ ? ? ? ? ? ? ? spin_lock_init(&sdma->lock);
+
+ ? ? ? ? ? ? ? dma_cap_set(DMA_SLAVE, sdma_dma_device->cap_mask);
+ ? ? ? ? ? ? ? dma_cap_set(DMA_CYCLIC, sdma_dma_device->cap_mask);
+
+ ? ? ? ? ? ? ? sdma->chan.device = sdma_dma_device;
+ ? ? ? ? ? ? ? sdma->chan.chan_id = i;
+
+ ? ? ? ? ? ? ? /* Add the channel to the DMAC list */
+ ? ? ? ? ? ? ? list_add_tail(&sdma->chan.device_node, &sdma_dma_device->channels);
+ ? ? ? }
+
+ ? ? ? sdma_dma_device->dev = &pdev->dev;
+
+ ? ? ? sdma_dma_device->device_alloc_chan_resources = sdma_alloc_chan_resources;

+ ? ? ? sdma_dma_device->device_free_chan_resources = sdma_free_chan_resources;
+ ? ? ? sdma_dma_device->device_tx_status = sdma_tx_status;
+ ? ? ? sdma_dma_device->device_prep_slave_sg = sdma_prep_slave_sg;
+ ? ? ? sdma_dma_device->device_prep_dma_cyclic = sdma_prep_dma_cyclic;
+ ? ? ? sdma_dma_device->device_control = sdma_control;
+ ? ? ? sdma_dma_device->device_issue_pending = sdma_issue_pending;
+
+ ? ? ? ret = dma_async_device_register(sdma_dma_device);
+ ? ? ? if (ret) {
+ ? ? ? ? ? ? ? dev_err(&pdev->dev, "unable to register DMAC\n");

+ ? ? ? ? ? ? ? goto err_firmware;
+ ? ? ? }
+
+ ? ? ? dev_info(&pdev->dev, "initialized (firmware %d.%d)\n",
+ ? ? ? ? ? ? ? ? ? ? ? header->version_major,
+ ? ? ? ? ? ? ? ? ? ? ? header->version_minor);
+
+ ? ? ? /* request channel 0. This is an internal control channel
+ ? ? ? ?* to the SDMA engine and not available to clients.
+ ? ? ? ?*/
+ ? ? ? dma_cap_zero(mask);
+ ? ? ? dma_cap_set(DMA_SLAVE, mask);
+ ? ? ? dma_request_channel(mask, NULL, NULL);
+
+ ? ? ? release_firmware(fw);
+
+ ? ? ? return 0;
+
+err_firmware:
+ ? ? ? release_firmware(fw);
+err_cputype:
+ ? ? ? clk_put(sdma_clk);
+err_clk:
+ ? ? ? return 0;
+}
+
+static int __devexit sdma_remove(struct platform_device *pdev)
+{
+ ? ? ? return -EBUSY;
+}
+
+static struct platform_driver sdma_driver = {
+ ? ? ? .driver ? ? ? ? = {
+ ? ? ? ? ? ? ? .name ? = "imx-sdma",
+ ? ? ? },
+ ? ? ? .probe ? ? ? ? ?= sdma_probe,
+ ? ? ? .remove ? ? ? ? = __devexit_p(sdma_remove),
+};
+
+static int __init sdma_module_init(void)
+{
+ ? ? ? return platform_driver_register(&sdma_driver);
+}
+subsys_initcall(sdma_module_init);
+
+MODULE_AUTHOR("Sascha Hauer, Pengutronix <[email protected]>");
+MODULE_DESCRIPTION("i.MX SDMA driver");
+MODULE_LICENSE("GPL");
--

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */

+
+#ifndef __ASM_ARCH_MXC_DMA_H__
+#define __ASM_ARCH_MXC_DMA_H__
+
+#include <linux/scatterlist.h>
+
+/*
+ * This enumerates peripheral types. Used for SDMA.
+ */
+typedef enum {

+ ? ? ? IMX_DMATYPE_SSI, ? ? ? ?/* MCU domain SSI */
+ ? ? ? IMX_DMATYPE_SSI_SP, ? ? /* Shared SSI */
+ ? ? ? IMX_DMATYPE_MMC, ? ? ? ?/* MMC */
+ ? ? ? IMX_DMATYPE_SDHC, ? ? ? /* SDHC */
+ ? ? ? IMX_DMATYPE_UART, ? ? ? /* MCU domain UART */
+ ? ? ? IMX_DMATYPE_UART_SP, ? ?/* Shared UART */
+ ? ? ? IMX_DMATYPE_FIRI, ? ? ? /* FIRI */
+ ? ? ? IMX_DMATYPE_CSPI, ? ? ? /* MCU domain CSPI */
+ ? ? ? IMX_DMATYPE_CSPI_SP, ? ?/* Shared CSPI */
+ ? ? ? IMX_DMATYPE_SIM, ? ? ? ?/* SIM */
+ ? ? ? IMX_DMATYPE_ATA, ? ? ? ?/* ATA */
+ ? ? ? IMX_DMATYPE_CCM, ? ? ? ?/* CCM */
+ ? ? ? IMX_DMATYPE_EXT, ? ? ? ?/* External peripheral */
+ ? ? ? IMX_DMATYPE_MSHC, ? ? ? /* Memory Stick Host Controller */
+ ? ? ? IMX_DMATYPE_MSHC_SP, ? ?/* Shared Memory Stick Host Controller */
+ ? ? ? IMX_DMATYPE_DSP, ? ? ? ?/* DSP */
+ ? ? ? IMX_DMATYPE_MEMORY, ? ? /* Memory */
+ ? ? ? IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
+ ? ? ? IMX_DMATYPE_SPDIF, ? ? ?/* SPDIF */
+ ? ? ? IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
+ ? ? ? IMX_DMATYPE_ASRC, ? ? ? /* ASRC */
+ ? ? ? IMX_DMATYPE_ESAI, ? ? ? /* ESAI */

+} sdma_peripheral_type;
+
+enum imx_dma_prio {
+ ? ? ? DMA_PRIO_HIGH = 0,
+ ? ? ? DMA_PRIO_MEDIUM = 1,
+ ? ? ? DMA_PRIO_LOW = 2
+};
+
+struct imx_dma_data {
+ ? ? ? int dma_request; /* DMA request line */

+ ? ? ? sdma_peripheral_type peripheral_type;
+ ? ? ? int priority;

+};
+
+static inline int imx_dma_is_ipu(struct dma_chan *chan)
+{
+ ? ? ? return !strcmp(dev_name(chan->device->dev), "ipu-core");
+}
+
+static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
+{
+ ? ? ? return !strcmp(dev_name(chan->device->dev), "imx-sdma");
+}
+
+#endif

new file mode 100644
index 0000000..5d542b8

@@ -0,0 +1,8 @@
+#ifndef __MACH_MXC_SDMA_H__
+#define __MACH_MXC_SDMA_H__
+
+struct sdma_platform_data {
+ ? ? ? int sdma_version;

+};
+
+#endif /* __MACH_MXC_SDMA_H__ */

index 9520cf0..f76bda9 100644
@@ -195,6 +195,14 @@ config PCH_DMA

+config IMX_SDMA
+ ? ? ? tristate "Atmel AHB DMA support"
+ ? ? ? depends on ARCH_MXC
+ ? ? ? select DMA_ENGINE
+ ? ? ? help
+ ? ? ? ? Support the i.MX SDMA engine. This engine is integrated into
+ ? ? ? ? Freescale i.MX25/31/35/51 chips.
+

index 72bd703..14d7a1b 100644
@@ -25,3 +25,4 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o

+obj-$(CONFIG_IMX_SDMA) += imx-sdma.o

new file mode 100644
index 0000000..3ba7905
@@ -0,0 +1,1383 @@
+/*
+ * drivers/dma/imx-sdma.c
+ *
+ * This file contains a driver for the Freescale Smart DMA engine
+ *
+ * Copyright 2010 Sascha Hauer, Pengutronix <[email protected]>
+ *
+ * Based on code from Freescale:
+ *
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/semaphore.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/dmaengine.h>
+
+#include <asm/irq.h>
+#include <mach/sdma.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
+
+/* SDMA registers */
+#define SDMA_H_C0PTR ? ? ? ? ? (sdma_base + 0x000)
+#define SDMA_H_INTR ? ? ? ? ? ?(sdma_base + 0x004)
+#define SDMA_H_STATSTOP ? ? ? ? ? ? ? ?(sdma_base + 0x008)
+#define SDMA_H_START ? ? ? ? ? (sdma_base + 0x00c)
+#define SDMA_H_EVTOVR ? ? ? ? ?(sdma_base + 0x010)
+#define SDMA_H_DSPOVR ? ? ? ? ?(sdma_base + 0x014)
+#define SDMA_H_HOSTOVR ? ? ? ? (sdma_base + 0x018)
+#define SDMA_H_EVTPEND ? ? ? ? (sdma_base + 0x01c)
+#define SDMA_H_DSPENBL ? ? ? ? (sdma_base + 0x020)
+#define SDMA_H_RESET ? ? ? ? ? (sdma_base + 0x024)
+#define SDMA_H_EVTERR ? ? ? ? ?(sdma_base + 0x028)
+#define SDMA_H_INTRMSK ? ? ? ? (sdma_base + 0x02c)
+#define SDMA_H_PSW ? ? ? ? ? ? (sdma_base + 0x030)
+#define SDMA_H_EVTERRDBG ? ? ? (sdma_base + 0x034)
+#define SDMA_H_CONFIG ? ? ? ? ?(sdma_base + 0x038)
+#define SDMA_ONCE_ENB ? ? ? ? ?(sdma_base + 0x040)
+#define SDMA_ONCE_DATA ? ? ? ? (sdma_base + 0x044)
+#define SDMA_ONCE_INSTR ? ? ? ? ? ? ? ?(sdma_base + 0x048)

+#define SDMA_ONCE_STAT ? ? ? ? (sdma_base + 0x04c)
+#define SDMA_ONCE_CMD ? ? ? ? ?(sdma_base + 0x050)
+#define SDMA_EVT_MIRROR ? ? ? ? ? ? ? ?(sdma_base + 0x054)
+#define SDMA_ILLINSTADDR ? ? ? (sdma_base + 0x058)
+#define SDMA_CHN0ADDR ? ? ? ? ?(sdma_base + 0x05c)
+#define SDMA_ONCE_RTB ? ? ? ? ?(sdma_base + 0x060)
+#define SDMA_XTRIG_CONF1 ? ? ? (sdma_base + 0x070)
+#define SDMA_XTRIG_CONF2 ? ? ? (sdma_base + 0x074)
+#define SDMA_CHNENBL_0 ? ? ? ? (sdma_base + (sdma_version == 2 ? 0x200 : 0x80))
+#define SDMA_CHNPRI_0 ? ? ? ? ?(sdma_base + 0x100)

+
+/*
+ * Buffer descriptor status values.
+ */
+#define BD_DONE ?0x01
+#define BD_WRAP ?0x02
+#define BD_CONT ?0x04
+#define BD_INTR ?0x08
+#define BD_RROR ?0x10
+#define BD_LAST ?0x20
+#define BD_EXTD ?0x80
+
+/*
+ * Data Node descriptor status values.
+ */
+#define DND_END_OF_FRAME ?0x80
+#define DND_END_OF_XFER ? 0x40
+#define DND_DONE ? ? ? ? ?0x20
+#define DND_UNUSED ? ? ? ?0x01
+
+/*
+ * IPCV2 descriptor status values.
+ */
+#define BD_IPCV2_END_OF_FRAME ?0x40
+
+#define IPCV2_MAX_NODES ? ? ? ?50
+/*
+ * Error bit set in the CCB status field by the SDMA,
+ * in setbd routine, in case of a transfer error
+ */
+#define DATA_ERROR ?0x10000000
+
+/*
+ * Buffer descriptor commands.
+ */
+#define C0_ADDR ? ? ? ? ? ? 0x01
+#define C0_LOAD ? ? ? ? ? ? 0x02
+#define C0_DUMP ? ? ? ? ? ? 0x03
+#define C0_SETCTX ? ? ? ? ? 0x07
+#define C0_GETCTX ? ? ? ? ? 0x03
+#define C0_SETDM ? ? ? ? ? ?0x01
+#define C0_SETPM ? ? ? ? ? ?0x04
+#define C0_GETDM ? ? ? ? ? ?0x02
+#define C0_GETPM ? ? ? ? ? ?0x08
+/*
+ * Change endianness indicator in the BD command field
+ */
+#define CHANGE_ENDIANNESS ? 0x80
+
+/*
+ * Mode/Count of data node descriptors - IPCv2

+ */
+#ifdef __BIG_ENDIAN
+struct sdma_mode_count {
+ ? ? ? u32 command : ?8; /* command mostlky used for channel 0 */

+ ? ? ? u32 status ?: ?8; /* E,R,I,C,W,D status bits stored here */
+ ? ? ? u32 count ? : 16; /* size of the buffer pointed by this BD */
+};
+#else
+struct sdma_mode_count {
+ ? ? ? u32 count ? : 16; /* size of the buffer pointed by this BD */
+ ? ? ? u32 status ?: ?8; /* E,R,I,C,W,D status bits stored here */
+ ? ? ? u32 command : ?8; /* command mostlky used for channel 0 */
+};
+#endif

+
+/*
+ * Buffer descriptor
+ */
+struct sdma_buffer_descriptor {
+ ? ? ? struct sdma_mode_count ?mode;
+ ? ? ? u32 buffer_addr; ? ?/* address of the buffer described */
+ ? ? ? u32 ext_buffer_addr; /* extended buffer address */

+};
+
+/*
+ * Channel control Block
+ */
+struct sdma_channel_control {
+ ? ? ? u32 current_bd_ptr; /* current buffer descriptor processed */
+ ? ? ? u32 base_bd_ptr; ? ?/* first element of buffer descriptor array */
+ ? ? ? void *unused;
+ ? ? ? void *unused1;

+};
+
+/**
+ * Context structure.
+ */
+#ifdef __BIG_ENDIAN
+struct sdma_state_registers {
+ ? ? ? u32 sf ? ? : 1; /* source fault while loading data */
+ ? ? ? u32 unused0: 1;
+ ? ? ? u32 rpc ? ?:14; /* return program counter */
+ ? ? ? u32 t ? ? ?: 1; /* test bit:status of arithmetic & test instruction*/
+ ? ? ? u32 unused1: 1;
+ ? ? ? u32 pc ? ? :14; /* program counter */
+ ? ? ? u32 lm ? ? : 2; /* loop mode */
+ ? ? ? u32 epc ? ?:14; /* loop end program counter */
+ ? ? ? u32 df ? ? : 1; /* destination fault while storing data */
+ ? ? ? u32 unused2: 1;
+ ? ? ? u32 spc ? ?:14; /* loop start program counter */
+};
+#else
+struct sdma_state_registers {
+ ? ? ? u32 pc ? ? :14; /* program counter */
+ ? ? ? u32 unused1: 1;
+ ? ? ? u32 t ? ? ?: 1; /* test bit: status of arithmetic & test instruction*/

+ ? ? ? u32 rpc ? ?:14; /* return program counter */
+ ? ? ? u32 unused0: 1;
+ ? ? ? u32 sf ? ? : 1; /* source fault while loading data */
+ ? ? ? u32 spc ? ?:14; /* loop start program counter */
+ ? ? ? u32 unused2: 1;
+ ? ? ? u32 df ? ? : 1; /* destination fault while storing data */
+ ? ? ? u32 epc ? ?:14; /* loop end program counter */
+ ? ? ? u32 lm ? ? : 2; /* loop mode */
+};
+#endif

+
+struct sdma_context_data {
+ ? ? ? struct sdma_state_registers ?channel_state; /* channel state bits */
+ ? ? ? u32 ?gReg[8]; /* general registers */
+ ? ? ? u32 ?mda; /* burst dma destination address register */
+ ? ? ? u32 ?msa; /* burst dma source address register */
+ ? ? ? u32 ?ms; ?/* burst dma status ?register */
+ ? ? ? u32 ?md; ?/* burst dma data ? ?register */
+ ? ? ? u32 ?pda; /* peripheral dma destination address register */
+ ? ? ? u32 ?psa; /* peripheral dma source address register */
+ ? ? ? u32 ?ps; ?/* peripheral dma ?status ?register */
+ ? ? ? u32 ?pd; ?/* peripheral dma ?data ? ?register */
+ ? ? ? u32 ?ca; ?/* CRC polynomial ?register */
+ ? ? ? u32 ?cs; ?/* CRC accumulator register */
+ ? ? ? u32 ?dda; /* dedicated core destination address register */
+ ? ? ? u32 ?dsa; /* dedicated core source address register */
+ ? ? ? u32 ?ds; ?/* dedicated core status ?register */
+ ? ? ? u32 ?dd; ?/* dedicated core data ? ?register */
+ ? ? ? u32 ?scratch0;
+ ? ? ? u32 ?scratch1;
+ ? ? ? u32 ?scratch2;

+ ? ? ? u32 ?scratch3;
+ ? ? ? u32 ?scratch4;
+ ? ? ? u32 ?scratch5;
+ ? ? ? u32 ?scratch6;
+ ? ? ? u32 ?scratch7;
+};
+
+struct sdma_channel {
+ ? ? ? /* Channel number */
+ ? ? ? int channel;

+ ? ? ? /* Transfer type. Needed for setting SDMA script */
+ ? ? ? enum dma_data_direction direction;
+ ? ? ? /* Peripheral type. Needed for setting SDMA script */
+ ? ? ? sdma_peripheral_type peripheral_type;
+ ? ? ? /* Peripheral event id */
+ ? ? ? int event_id;

+ ? ? ? /* Peripheral event id2 (for channels that use 2 events) */
+ ? ? ? int event_id2;

+ ? ? ? /* SDMA data access word size */
+ ? ? ? unsigned long word_size;

+
+ ? ? ? /* ID of the buffer that was processed */
+ ? ? ? unsigned int buf_tail;
+
+ ? ? ? wait_queue_head_t waitq; ? ? ? ?/* channel completion waitqeue */
+
+ ? ? ? int num_bd;

+
+ ? ? ? struct sdma_buffer_descriptor *bd;
+ ? ? ? dma_addr_t ? ? ?bd_phys;
+
+ ? ? ? int pc_from_device, pc_to_device;

+
+ ? ? ? unsigned long flags;

+ ? ? ? dma_addr_t per_address;
+
+ ? ? ? uint32_t event_mask1, event_mask2;

+ ? ? ? uint32_t watermark_level;
+ ? ? ? uint32_t shp_addr, per_addr;
+
+ ? ? ? /* DMA-Engine Channel */
+ ? ? ? struct dma_chan chan;
+
+ ? ? ? spinlock_t ? ? ? ? ? ? ?lock;
+ ? ? ? struct dma_async_tx_descriptor desc;
+ ? ? ? dma_cookie_t ? ? ? ? ? ?last_completed;
+ ? ? ? int busy;

+};
+
+#define IMX_DMA_SG_LOOP ? ? ? ? ? ? ? ?(1 << 0)

+
+#define MAX_DMA_CHANNELS 32
+#define MXC_SDMA_DEFAULT_PRIORITY 1
+#define MXC_SDMA_MIN_PRIORITY 1
+#define MXC_SDMA_MAX_PRIORITY 7
+
+/*
+ * This enumerates transfer types
+ */
+typedef enum {

+ ? ? ? emi_2_per = 0, ? ? ? ? ?/* EMI memory to peripheral */
+ ? ? ? emi_2_int, ? ? ? ? ? ? ?/* EMI memory to internal RAM */
+ ? ? ? emi_2_emi, ? ? ? ? ? ? ?/* EMI memory to EMI memory */
+ ? ? ? emi_2_dsp, ? ? ? ? ? ? ?/* EMI memory to DSP memory */
+ ? ? ? per_2_int, ? ? ? ? ? ? ?/* Peripheral to internal RAM */
+ ? ? ? per_2_emi, ? ? ? ? ? ? ?/* Peripheral to internal EMI memory */
+ ? ? ? per_2_dsp, ? ? ? ? ? ? ?/* Peripheral to DSP memory */
+ ? ? ? per_2_per, ? ? ? ? ? ? ?/* Peripheral to Peripheral */
+ ? ? ? int_2_per, ? ? ? ? ? ? ?/* Internal RAM to peripheral */
+ ? ? ? int_2_int, ? ? ? ? ? ? ?/* Internal RAM to Internal RAM */
+ ? ? ? int_2_emi, ? ? ? ? ? ? ?/* Internal RAM to EMI memory */
+ ? ? ? int_2_dsp, ? ? ? ? ? ? ?/* Internal RAM to DSP memory */
+ ? ? ? dsp_2_per, ? ? ? ? ? ? ?/* DSP memory to peripheral */
+ ? ? ? dsp_2_int, ? ? ? ? ? ? ?/* DSP memory to internal RAM */
+ ? ? ? dsp_2_emi, ? ? ? ? ? ? ?/* DSP memory to EMI memory */
+ ? ? ? dsp_2_dsp, ? ? ? ? ? ? ?/* DSP memory to DSP memory */
+ ? ? ? emi_2_dsp_loop, ? ? ? ? /* EMI memory to DSP memory loopback */
+ ? ? ? dsp_2_emi_loop, ? ? ? ? /* DSP memory to EMI memory loopback */
+ ? ? ? dvfs_pll, ? ? ? ? ? ? ? /* DVFS script with PLL change ? ? ? */
+ ? ? ? dvfs_pdr ? ? ? ? ? ? ? ?/* DVFS script without PLL change ? ?*/
+} sdma_transfer_type;
+
+/*
+ * Structure containing sdma request ?parameters.
+ */
+struct sdma_script_start_addrs {
+ ? ? ? int ap_2_ap_addr;
+ ? ? ? int ap_2_bp_addr;
+ ? ? ? int ap_2_ap_fixed_addr;
+ ? ? ? int bp_2_ap_addr;
+ ? ? ? int loopback_on_dsp_side_addr;
+ ? ? ? int mcu_interrupt_only_addr;
+
+ ? ? ? int firi_2_per_addr;
+ ? ? ? int firi_2_mcu_addr;
+ ? ? ? int per_2_firi_addr;
+ ? ? ? int mcu_2_firi_addr;
+
+ ? ? ? int uart_2_per_addr;
+ ? ? ? int uart_2_mcu_addr;
+ ? ? ? int per_2_app_addr;
+ ? ? ? int mcu_2_app_addr;
+ ? ? ? int per_2_per_addr;
+
+ ? ? ? int uartsh_2_per_addr;
+ ? ? ? int uartsh_2_mcu_addr;
+ ? ? ? int per_2_shp_addr;
+ ? ? ? int mcu_2_shp_addr;
+
+ ? ? ? int ata_2_mcu_addr;
+ ? ? ? int mcu_2_ata_addr;
+
+ ? ? ? int app_2_per_addr;
+ ? ? ? int app_2_mcu_addr;
+ ? ? ? int shp_2_per_addr;
+ ? ? ? int shp_2_mcu_addr;
+
+ ? ? ? int mshc_2_mcu_addr;
+ ? ? ? int mcu_2_mshc_addr;
+
+ ? ? ? int spdif_2_mcu_addr;
+ ? ? ? int mcu_2_spdif_addr;
+
+ ? ? ? int asrc_2_mcu_addr;
+
+ ? ? ? int ext_mem_2_ipu_addr;
+
+ ? ? ? int descrambler_addr;
+
+ ? ? ? int dptc_dvfs_addr;

+
+ ? ? ? int utra_addr;
+
+ ? ? ? int ram_code_start_addr;

+};
+
+#define SDMA_FIRMWARE_MAGIC 0x414d4453
+
+struct sdma_firmware_header {
+ ? ? ? uint32_t ? ? ? ?magic; /* "SDMA" */
+ ? ? ? uint32_t ? ? ? ?version_major; ?/* increased whenever layout of struct sdma_script_start_addrs changes */
+ ? ? ? uint32_t ? ? ? ?version_minor; ?/* firmware version */
+ ? ? ? uint32_t ? ? ? ?script_addrs_start; /* offset of struct sdma_script_start_addrs in this image */
+ ? ? ? uint32_t ? ? ? ?num_script_addrs; /* Number of script addresses in this image */
+ ? ? ? uint32_t ? ? ? ?ram_code_start; /* offset of SDMA ram image in this firmware image */
+ ? ? ? uint32_t ? ? ? ?ram_code_size; /* size of SDMA ram image */

+};
+
+static struct sdma_channel sdma_data[MAX_DMA_CHANNELS];
+static struct sdma_channel_control *channel_control;
+static void __iomem *sdma_base;
+static int sdma_version;

+static int sdma_num_events;

+static struct sdma_context_data *sdma_context;
+dma_addr_t sdma_context_phys;
+static struct dma_device __sdma_dma_device;
+static struct dma_device *sdma_dma_device = &__sdma_dma_device;

+
+#define SDMA_H_CONFIG_DSPDMA ? (1 << 12) /* indicates if the DSPDMA is used */
+#define SDMA_H_CONFIG_RTD_PINS (1 << 11) /* indicates if Real-Time Debug pins are enabled */
+#define SDMA_H_CONFIG_ACR ? ? ?(1 << 4) ?/* indicates if AHB freq /core freq = 2 or 1 */
+#define SDMA_H_CONFIG_CSM ? ? ?(3) ? ? ? /* indicates which context switch mode is selected*/
+
+static int sdma_config_ownership(int channel, int event_override,
+ ? ? ? ? ? ? ? ? ?int mcu_verride, int dsp_override)
+{
+ ? ? ? u32 evt, mcu, dsp;
+
+ ? ? ? if (event_override && mcu_verride && dsp_override)
+ ? ? ? ? ? ? ? return -EINVAL;
+
+ ? ? ? evt = readl(SDMA_H_EVTOVR);
+ ? ? ? mcu = readl(SDMA_H_HOSTOVR);
+ ? ? ? dsp = readl(SDMA_H_DSPOVR);
+
+ ? ? ? if (dsp_override)
+ ? ? ? ? ? ? ? dsp &= ~(1 << channel);
+ ? ? ? else
+ ? ? ? ? ? ? ? dsp |= (1 << channel);
+
+ ? ? ? if (event_override)
+ ? ? ? ? ? ? ? evt &= ~(1 << channel);
+ ? ? ? else
+ ? ? ? ? ? ? ? evt |= (1 << channel);
+
+ ? ? ? if (mcu_verride)
+ ? ? ? ? ? ? ? mcu &= ~(1 << channel);
+ ? ? ? else
+ ? ? ? ? ? ? ? mcu |= (1 << channel);
+
+ ? ? ? writel(evt, SDMA_H_EVTOVR);
+ ? ? ? writel(mcu, SDMA_H_HOSTOVR);
+ ? ? ? writel(dsp, SDMA_H_DSPOVR);
+
+ ? ? ? return 0;
+}
+
+/*
+ * sdma_run_channel - run a channel and wait till it's done
+ */
+static int sdma_run_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? int ret;
+

+ ? ? ? writel(1 << channel, SDMA_H_START);
+
+ ? ? ? ret = wait_event_interruptible(sdma->waitq,
+ ? ? ? ? ? ? ? ? ? ? ? !(readl(SDMA_H_STATSTOP) & (1 << channel)));

+ ? ? ? return ret;
+}
+
+static int sdma_load_script(void *buf, int size, u32 address)
+{
+ ? ? ? struct sdma_buffer_descriptor *bd0 = sdma_data[0].bd;
+ ? ? ? void *buf_virt;
+ ? ? ? dma_addr_t buf_phys;
+ ? ? ? int ret;
+
+ ? ? ? buf_virt = dma_alloc_coherent(NULL,
+ ? ? ? ? ? ? ? ? ? ? ? size,
+ ? ? ? ? ? ? ? ? ? ? ? &buf_phys, GFP_KERNEL);
+ ? ? ? if (!buf_virt)
+ ? ? ? ? ? ? ? return -ENOMEM;
+
+ ? ? ? bd0->mode.command = C0_SETPM;
+ ? ? ? bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+ ? ? ? bd0->mode.count = size / 2;
+ ? ? ? bd0->buffer_addr = buf_phys;
+ ? ? ? bd0->ext_buffer_addr = address;
+
+ ? ? ? memcpy(buf_virt, buf, size);
+
+ ? ? ? ret = sdma_run_channel(0);
+

+ ? ? ? dma_free_coherent(NULL, size, buf_virt, buf_phys);
+
+ ? ? ? return ret;
+}
+
+static void sdma_event_enable(int channel, int event)
+{
+ ? ? ? u32 val;
+
+ ? ? ? val = readl(SDMA_CHNENBL_0 + event * 4);

+ ? ? ? val |= (1 << channel);
+ ? ? ? writel(val, SDMA_CHNENBL_0 + event * 4);
+}
+
+static void sdma_event_disable(int channel, int event)
+{
+ ? ? ? u32 val;
+
+ ? ? ? val = readl(SDMA_CHNENBL_0 + event * 4);
+ ? ? ? val &= ~(1 << channel);
+ ? ? ? writel(val, SDMA_CHNENBL_0 + event * 4);

+}
+
+static void mxc_sdma_handle_channel_loop(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];

+ ? ? ? struct sdma_buffer_descriptor *bd;
+ ? ? ? int error = 0;

+
+ ? ? ? /*
+ ? ? ? ?* loop mode. Iterate over descriptors, re-setup them and
+ ? ? ? ?* call callback function.
+ ? ? ? ?*/
+ ? ? ? while (1) {
+ ? ? ? ? ? ? ? bd = &sdma->bd[sdma->buf_tail];
+
+ ? ? ? ? ? ? ? if (bd->mode.status & BD_DONE)
+ ? ? ? ? ? ? ? ? ? ? ? break;
+
+ ? ? ? ? ? ? ? if (bd->mode.status & BD_RROR)
+ ? ? ? ? ? ? ? ? ? ? ? error = -EIO;
+
+ ? ? ? ? ? ? ? bd->mode.status |= BD_DONE;
+ ? ? ? ? ? ? ? sdma->buf_tail++;
+ ? ? ? ? ? ? ? sdma->buf_tail %= sdma->num_bd;
+
+ ? ? ? ? ? ? ? if (sdma->desc.callback)
+ ? ? ? ? ? ? ? ? ? ? ? sdma->desc.callback(sdma->desc.callback_param);
+ ? ? ? }
+}
+
+static void mxc_sdma_handle_channel_normal(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? struct sdma_buffer_descriptor *bd;
+ ? ? ? int i, error = 0;
+
+ ? ? ? /*
+ ? ? ? ?* non loop mode. Iterate over all descriptors, collect
+ ? ? ? ?* errors and call callback function
+ ? ? ? ?*/
+ ? ? ? for (i = 0; i < sdma->num_bd; i++) {
+ ? ? ? ? ? ? ? bd = &sdma->bd[i];

+
+ ? ? ? ? ? ? ? ?if (bd->mode.status & (BD_DONE | BD_RROR))
+ ? ? ? ? ? ? ? ? ? ? ? error = -EIO;
+ ? ? ? }
+
+ ? ? ? if (sdma->desc.callback)
+ ? ? ? ? ? ? ? sdma->desc.callback(sdma->desc.callback_param);
+ ? ? ? sdma->last_completed = sdma->desc.cookie;
+
+ ? ? ? sdma->busy = 0;

+}
+
+static void mxc_sdma_handle_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+
+ ? ? ? wake_up_interruptible(&sdma->waitq);
+
+ ? ? ? /* not interested in channel 0 interrupts */
+ ? ? ? if (!channel)
+ ? ? ? ? ? ? ? return;
+
+ ? ? ? if (sdma->flags & IMX_DMA_SG_LOOP)
+ ? ? ? ? ? ? ? mxc_sdma_handle_channel_loop(channel);
+ ? ? ? else
+ ? ? ? ? ? ? ? mxc_sdma_handle_channel_normal(channel);
+}
+
+static irqreturn_t sdma_int_handler(int irq, void *dev_id)
+{
+ ? ? ? u32 stat;
+
+ ? ? ? stat = readl(SDMA_H_INTR);
+ ? ? ? writel(stat, SDMA_H_INTR);
+
+ ? ? ? while (stat) {
+ ? ? ? ? ? ? ? int channel = fls(stat) - 1;
+
+ ? ? ? ? ? ? ? mxc_sdma_handle_channel(channel);
+
+ ? ? ? ? ? ? ? stat &= ~(1 << channel);
+ ? ? ? }
+
+ ? ? ? return IRQ_HANDLED;
+}
+
+static struct clk *sdma_clk;
+
+/*
+ * Stores the start address of the SDMA scripts
+ */
+static struct sdma_script_start_addrs __sdma_script_addrs;
+static struct sdma_script_start_addrs *sdma_script_addrs = &__sdma_script_addrs;
+
+/*
+ * sets the pc of SDMA script according to the peripheral type
+ */
+static void sdma_get_pc(struct sdma_channel *sdma,
+ ? ? ? ? ? ? ? sdma_peripheral_type peripheral_type)
+{
+ ? ? ? int res = 0;
+ ? ? ? int per_2_emi = 0, emi_2_per = 0;
+ ? ? ? int per_2_int = 0, int_2_per = 0;

+ ? ? ? int per_2_per = 0, emi_2_emi = 0;
+
+ ? ? ? sdma->pc_from_device = 0;
+ ? ? ? sdma->pc_to_device = 0;

+
+ ? ? ? switch (peripheral_type) {
+ ? ? ? case IMX_DMATYPE_MEMORY:
+ ? ? ? ? ? ? ? emi_2_emi = sdma_script_addrs->ap_2_ap_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_DSP:
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->bp_2_ap_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->ap_2_bp_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_FIRI:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->firi_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->firi_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_firi_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_firi_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_UART:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->uart_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->uart_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_app_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_app_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_UART_SP:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->uartsh_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->uartsh_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_shp_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_shp_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_ATA:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->ata_2_mcu_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_ata_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_CSPI:
+ ? ? ? case IMX_DMATYPE_EXT:
+ ? ? ? case IMX_DMATYPE_SSI:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->app_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->app_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_app_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_app_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_SSI_SP:
+ ? ? ? case IMX_DMATYPE_MMC:
+ ? ? ? case IMX_DMATYPE_SDHC:
+ ? ? ? case IMX_DMATYPE_CSPI_SP:
+ ? ? ? case IMX_DMATYPE_ESAI:
+ ? ? ? case IMX_DMATYPE_MSHC_SP:
+ ? ? ? ? ? ? ? per_2_int = sdma_script_addrs->shp_2_per_addr;
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->shp_2_mcu_addr;
+ ? ? ? ? ? ? ? int_2_per = sdma_script_addrs->per_2_shp_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_shp_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_ASRC:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->asrc_2_mcu_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->asrc_2_mcu_addr;
+ ? ? ? ? ? ? ? per_2_per = sdma_script_addrs->per_2_per_addr;

+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_MSHC:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->mshc_2_mcu_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_mshc_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_CCM:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->dptc_dvfs_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_FIFO_MEMORY:
+ ? ? ? ? ? ? ? res = sdma_script_addrs->ap_2_ap_fixed_addr;

+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_SPDIF:
+ ? ? ? ? ? ? ? per_2_emi = sdma_script_addrs->spdif_2_mcu_addr;
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->mcu_2_spdif_addr;

+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_IPU_MEMORY:
+ ? ? ? ? ? ? ? emi_2_per = sdma_script_addrs->ext_mem_2_ipu_addr;
+ ? ? ? ? ? ? ? break;
+ ? ? ? default:
+ ? ? ? ? ? ? ? break;
+ ? ? ? }
+
+ ? ? ? sdma->pc_from_device = per_2_emi;
+ ? ? ? sdma->pc_to_device = emi_2_per;

+}
+
+static int sdma_load_context(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? int load_address;
+ ? ? ? struct sdma_buffer_descriptor *bd0 = sdma_data[0].bd;
+ ? ? ? int ret;
+
+ ? ? ? if (sdma->direction == DMA_FROM_DEVICE) {
+ ? ? ? ? ? ? ? load_address = sdma->pc_from_device;
+ ? ? ? } else {
+ ? ? ? ? ? ? ? load_address = sdma->pc_to_device;
+ ? ? ? }
+
+ ? ? ? if (load_address < 0)
+ ? ? ? ? ? ? ? return load_address;
+
+ ? ? ? pr_debug("%s: load_address = %d\n", __func__, load_address);

+ ? ? ? pr_debug("%s: wml = 0x%08x\n", __func__, sdma->watermark_level);
+ ? ? ? pr_debug("%s: shp_addr = 0x%08x\n", __func__, sdma->shp_addr);
+ ? ? ? pr_debug("%s: per_addr = 0x%08x\n", __func__, sdma->per_addr);
+ ? ? ? pr_debug("%s: event_mask1 = 0x%08x\n", __func__, sdma->event_mask1);
+ ? ? ? pr_debug("%s: event_mask2 = 0x%08x\n", __func__, sdma->event_mask2);

+
+ ? ? ? memset(sdma_context, 0, sizeof(*sdma_context));
+ ? ? ? sdma_context->channel_state.pc = load_address;
+
+ ? ? ? /* Send by context the event mask,base address for peripheral
+ ? ? ? ?* and watermark level
+ ? ? ? ?*/
+ ? ? ? sdma_context->gReg[0] = sdma->event_mask2;
+ ? ? ? sdma_context->gReg[1] = sdma->event_mask1;
+ ? ? ? sdma_context->gReg[2] = sdma->per_addr;
+ ? ? ? sdma_context->gReg[6] = sdma->shp_addr;
+ ? ? ? sdma_context->gReg[7] = sdma->watermark_level;
+
+ ? ? ? bd0->mode.command = C0_SETDM;
+ ? ? ? bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+ ? ? ? bd0->mode.count = sizeof(*sdma_context) / 4;
+ ? ? ? bd0->buffer_addr = sdma_context_phys;
+ ? ? ? bd0->ext_buffer_addr = 2048 + (sizeof(*sdma_context) / 4) * channel;
+
+ ? ? ? ret = sdma_run_channel(0);
+
+ ? ? ? return ret;
+}
+
+static void sdma_disable_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+
+ ? ? ? writel(1 << channel, SDMA_H_STATSTOP);
+ ? ? ? sdma->busy = 0;
+}
+
+static int sdma_config_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? int ret;
+
+ ? ? ? sdma_disable_channel(channel);
+
+ ? ? ? sdma->event_mask1 = 0;
+ ? ? ? sdma->event_mask2 = 0;
+ ? ? ? sdma->shp_addr = 0;
+ ? ? ? sdma->per_addr = 0;
+
+ ? ? ? if (sdma->event_id)

+ ? ? ? ? ? ? ? sdma_event_enable(channel, sdma->event_id);
+
+ ? ? ? switch (sdma->peripheral_type) {
+ ? ? ? case IMX_DMATYPE_DSP:
+ ? ? ? ? ? ? ? sdma_config_ownership(channel, 0, 1, 1);

+ ? ? ? ? ? ? ? break;
+ ? ? ? case IMX_DMATYPE_MEMORY:
+ ? ? ? ? ? ? ? sdma_config_ownership(channel, 0, 1, 0);
+ ? ? ? ? ? ? ? break;
+ ? ? ? default:
+ ? ? ? ? ? ? ? sdma_config_ownership(channel, 1, 1, 0);
+ ? ? ? ? ? ? ? break;
+ ? ? ? }
+
+ ? ? ? sdma_get_pc(sdma, sdma->peripheral_type);
+
+ ? ? ? if ((sdma->peripheral_type != IMX_DMATYPE_MEMORY) &&
+ ? ? ? ? ? ? ? ? ? ? ? (sdma->peripheral_type != IMX_DMATYPE_DSP)) {
+ ? ? ? ? ? ? ? /* Handle multiple event channels differently */
+ ? ? ? ? ? ? ? if (sdma->event_id2) {
+ ? ? ? ? ? ? ? ? ? ? ? sdma->event_mask2 = 1 << (sdma->event_id2 % 32);
+ ? ? ? ? ? ? ? ? ? ? ? if (sdma->event_id2 > 31)
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sdma->watermark_level |= 1 << 31;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->event_mask1 = 1 << (sdma->event_id % 32);
+ ? ? ? ? ? ? ? ? ? ? ? if (sdma->event_id > 31)
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sdma->watermark_level |= 1 << 30;
+ ? ? ? ? ? ? ? } else {
+ ? ? ? ? ? ? ? ? ? ? ? sdma->event_mask1 = 1 << sdma->event_id;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->event_mask2 = 1 << (sdma->event_id - 32);
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? /* Watermark Level */
+ ? ? ? ? ? ? ? sdma->watermark_level |= sdma->watermark_level;
+ ? ? ? ? ? ? ? /* Address */
+ ? ? ? ? ? ? ? sdma->shp_addr = sdma->per_address;
+ ? ? ? } else {
+ ? ? ? ? ? ? ? sdma->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
+ ? ? ? }
+
+ ? ? ? ret = sdma_load_context(channel);
+
+ ? ? ? return ret;
+}
+
+static int sdma_set_channel_priority(unsigned int channel, unsigned int priority)
+{
+ ? ? ? if (priority < MXC_SDMA_MIN_PRIORITY
+ ? ? ? ? ? || priority > MXC_SDMA_MAX_PRIORITY) {
+ ? ? ? ? ? ? ? return -EINVAL;
+ ? ? ? }
+
+ ? ? ? writel(priority, SDMA_CHNPRI_0 + 4 * channel);
+
+ ? ? ? return 0;
+}
+
+static int sdma_request_channel(int channel)
+{
+ ? ? ? struct sdma_channel *sdma = &sdma_data[channel];
+ ? ? ? int ret = -EBUSY;
+
+ ? ? ? sdma->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdma->bd_phys, GFP_KERNEL);
+ ? ? ? if (!sdma->bd) {

+ ? ? ? ? ? ? ? ret = -ENOMEM;
+ ? ? ? ? ? ? ? goto out;
+ ? ? ? }
+
+ ? ? ? memset(sdma->bd, 0, PAGE_SIZE);
+
+ ? ? ? channel_control[channel].base_bd_ptr = sdma->bd_phys;
+ ? ? ? channel_control[channel].current_bd_ptr = sdma->bd_phys;
+
+ ? ? ? clk_enable(sdma_clk);

+
+ ? ? ? sdma_set_channel_priority(channel, MXC_SDMA_DEFAULT_PRIORITY);
+
+ ? ? ? init_waitqueue_head(&sdma->waitq);
+
+ ? ? ? sdma->buf_tail = 0;
+
+ ? ? ? return 0;
+out:
+
+ ? ? ? return ret;
+}
+
+static void sdma_enable_channel(int channel)
+{
+ ? ? ? writel(1 << channel, SDMA_H_START);
+}
+
+static int __init sdma_init(unsigned long phys_base, int irq, int version,
+ ? ? ? ? ? ? ? void *ram_code,
+ ? ? ? ? ? ? ? int ram_code_size)
+{
+ ? ? ? int i, ret;
+ ? ? ? int channel;
+ ? ? ? dma_addr_t ccb_phys;
+
+ ? ? ? sdma_version = version;
+ ? ? ? switch (sdma_version) {
+ ? ? ? case 1:
+ ? ? ? ? ? ? ? sdma_num_events = 32;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case 2:
+ ? ? ? ? ? ? ? sdma_num_events = 48;
+ ? ? ? ? ? ? ? break;
+ ? ? ? default:
+ ? ? ? ? ? ? ? pr_err("SDMA: Unknown version %d. aborting\n", sdma_version);

+ ? ? ? ? ? ? ? return -ENODEV;
+ ? ? ? }
+
+ ? ? ? clk_enable(sdma_clk);
+
+ ? ? ? sdma_base = ioremap(phys_base, 4096);

+ ? ? ? if (!sdma_base) {
+ ? ? ? ? ? ? ? ret = -ENOMEM;
+ ? ? ? ? ? ? ? goto err_ioremap;
+ ? ? ? }
+
+ ? ? ? /* Initialize SDMA private data */
+ ? ? ? memset(sdma_data, 0, sizeof(struct sdma_channel) * MAX_DMA_CHANNELS);
+
+ ? ? ? for (channel = 0; channel < MAX_DMA_CHANNELS; channel++)
+ ? ? ? ? ? ? ? sdma_data[channel].channel = channel;
+
+ ? ? ? ret = request_irq(irq, sdma_int_handler, 0, "sdma", NULL);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_request_irq;
+
+ ? ? ? /* Be sure SDMA has not started yet */
+ ? ? ? writel(0, SDMA_H_C0PTR);
+
+ ? ? ? channel_control = dma_alloc_coherent(NULL,
+ ? ? ? ? ? ? ? ? ? ? ? MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
+ ? ? ? ? ? ? ? ? ? ? ? sizeof(struct sdma_context_data),
+ ? ? ? ? ? ? ? ? ? ? ? &ccb_phys, GFP_KERNEL);
+
+ ? ? ? if (!channel_control) {
+ ? ? ? ? ? ? ? ret = -ENOMEM;
+ ? ? ? ? ? ? ? goto err_dma_alloc;
+ ? ? ? }
+
+ ? ? ? sdma_context = (void *)channel_control +
+ ? ? ? ? ? ? ? MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
+ ? ? ? sdma_context_phys = ccb_phys +
+ ? ? ? ? ? ? ? MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
+
+ ? ? ? /* Zero-out the CCB structures array just allocated */
+ ? ? ? memset(channel_control, 0,
+ ? ? ? ? ? ? ? ? ? ? ? MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
+
+ ? ? ? /* disable all channels */
+ ? ? ? for (i = 0; i < sdma_num_events; i++)
+ ? ? ? ? ? ? ? writel(0, SDMA_CHNENBL_0 + i * 4);
+
+ ? ? ? /* All channels have priority 0 */
+ ? ? ? for (i = 0; i < MAX_DMA_CHANNELS; i++)
+ ? ? ? ? ? ? ? writel(0, SDMA_CHNPRI_0 + i * 4);
+
+ ? ? ? ret = sdma_request_channel(0);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_dma_alloc;
+
+ ? ? ? sdma_config_ownership(0, 0, 1, 0);
+
+ ? ? ? /* Set Command Channel (Channel Zero) */
+ ? ? ? writel(0x4050, SDMA_CHN0ADDR);
+
+ ? ? ? /* Set bits of CONFIG register but with static context switching */
+ ? ? ? /* FIXME: Check whether to set ACR bit depending on clock ratios */
+ ? ? ? writel(0, SDMA_H_CONFIG);
+
+ ? ? ? writel(ccb_phys, SDMA_H_C0PTR);
+
+ ? ? ? /* download the RAM image for SDMA */
+ ? ? ? sdma_load_script(ram_code,
+ ? ? ? ? ? ? ? ? ? ? ? ram_code_size,
+ ? ? ? ? ? ? ? ? ? ? ? sdma_script_addrs->ram_code_start_addr);
+
+ ? ? ? /* Set bits of CONFIG register with given context switching mode */
+ ? ? ? writel(SDMA_H_CONFIG_CSM, SDMA_H_CONFIG);
+
+ ? ? ? /* Initializes channel's priorities */
+ ? ? ? sdma_set_channel_priority(0, 7);
+
+ ? ? ? clk_disable(sdma_clk);
+
+ ? ? ? return 0;
+
+err_dma_alloc:
+ ? ? ? free_irq(irq, NULL);
+err_request_irq:
+ ? ? ? iounmap(sdma_base);
+err_ioremap:
+ ? ? ? clk_disable(sdma_clk);
+ ? ? ? pr_err("%s failed with %d\n", __func__, ret);
+ ? ? ? return ret;
+}
+
+static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdma)
+{
+ ? ? ? dma_cookie_t cookie = sdma->chan.cookie;
+
+ ? ? ? if (++cookie < 0)
+ ? ? ? ? ? ? ? cookie = 1;
+
+ ? ? ? sdma->chan.cookie = cookie;
+ ? ? ? sdma->desc.cookie = cookie;
+
+ ? ? ? return cookie;
+}
+
+static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
+{
+ ? ? ? return container_of(chan, struct sdma_channel, chan);
+}
+
+static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(tx->chan);
+ ? ? ? dma_cookie_t cookie;
+
+ ? ? ? spin_lock_irq(&sdma->lock);
+
+ ? ? ? cookie = sdma_assign_cookie(sdma);
+
+ ? ? ? sdma_enable_channel(tx->chan->chan_id);
+
+ ? ? ? spin_unlock_irq(&sdma->lock);
+
+ ? ? ? return cookie;
+}
+
+static int sdma_alloc_chan_resources(struct dma_chan *chan)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? struct imx_dma_data *data = chan->private;
+ ? ? ? int prio, ret;
+
+ ? ? ? /* No need to execute this for internal channel 0 */
+ ? ? ? if (!chan->chan_id)
+ ? ? ? ? ? ? ? return 0;
+
+ ? ? ? if (!data)

+ ? ? ? ? ? ? ? return -EINVAL;
+
+ ? ? ? switch (data->priority) {
+ ? ? ? case DMA_PRIO_HIGH:
+ ? ? ? ? ? ? ? prio = 3;

+ ? ? ? ? ? ? ? break;
+ ? ? ? case DMA_PRIO_MEDIUM:
+ ? ? ? ? ? ? ? prio = 2;
+ ? ? ? ? ? ? ? break;
+ ? ? ? case DMA_PRIO_LOW:
+ ? ? ? default:
+ ? ? ? ? ? ? ? prio = 1;
+ ? ? ? ? ? ? ? break;
+ ? ? ? }
+
+ ? ? ? sdma->peripheral_type = data->peripheral_type;
+ ? ? ? sdma->event_id = data->dma_request;
+ ? ? ? ret = sdma_set_channel_priority(chan->chan_id, prio);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? return ret;
+
+ ? ? ? if (chan->chan_id) {
+ ? ? ? ? ? ? ? ret = sdma_request_channel(chan->chan_id);
+ ? ? ? ? ? ? ? if (ret)
+ ? ? ? ? ? ? ? ? ? ? ? return ret;
+ ? ? ? }
+
+ ? ? ? dma_async_tx_descriptor_init(&sdma->desc, chan);
+ ? ? ? sdma->desc.tx_submit = sdma_tx_submit;
+ ? ? ? /* txd.flags will be overwritten in prep funcs */
+ ? ? ? sdma->desc.flags = DMA_CTRL_ACK;
+
+ ? ? ? return 0;
+}
+
+static void sdma_free_chan_resources(struct dma_chan *chan)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? int channel = chan->chan_id;
+
+ ? ? ? sdma_disable_channel(channel);
+
+ ? ? ? if (sdma->event_id)
+ ? ? ? ? ? ? ? sdma_event_disable(channel, sdma->event_id);
+ ? ? ? if (sdma->event_id2)
+ ? ? ? ? ? ? ? sdma_event_disable(channel, sdma->event_id2);
+
+ ? ? ? sdma->event_id = 0;
+ ? ? ? sdma->event_id2 = 0;
+
+ ? ? ? sdma_set_channel_priority(channel, 0);
+
+ ? ? ? dma_free_coherent(NULL, PAGE_SIZE, sdma->bd, sdma->bd_phys);
+
+ ? ? ? clk_disable(sdma_clk);
+}
+
+#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
+
+static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
+ ? ? ? ? ? ? ? struct dma_chan *chan, struct scatterlist *sgl,
+ ? ? ? ? ? ? ? unsigned int sg_len, enum dma_data_direction direction,
+ ? ? ? ? ? ? ? unsigned long flags)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? int ret, i, count;
+ ? ? ? int channel = chan->chan_id;
+ ? ? ? struct scatterlist *sg;
+

+ ? ? ? if (sdma->busy)
+ ? ? ? ? ? ? ? return NULL;
+ ? ? ? sdma->busy = 1;
+
+ ? ? ? sdma->flags = 0;

+
+ ? ? ? pr_debug("SDMA: setting up %d entries for channel %d.\n",
+ ? ? ? ? ? ? ? ? ? ? ? sg_len, channel);
+
+ ? ? ? sdma->direction = direction;
+ ? ? ? ret = sdma_load_context(channel);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_out;
+
+ ? ? ? if (sg_len > NUM_BD) {
+ ? ? ? ? ? ? ? pr_err("SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? channel, sg_len, NUM_BD);
+ ? ? ? ? ? ? ? ret = -EINVAL;
+ ? ? ? ? ? ? ? goto err_out;
+ ? ? ? }
+
+ ? ? ? for_each_sg(sgl, sg, sg_len, i) {
+ ? ? ? ? ? ? ? struct sdma_buffer_descriptor *bd = &sdma->bd[i];
+ ? ? ? ? ? ? ? int param;
+
+ ? ? ? ? ? ? ? bd->buffer_addr = sgl->dma_address;
+
+ ? ? ? ? ? ? ? count = sg->length;
+
+ ? ? ? ? ? ? ? if (count > 0xffff) {
+ ? ? ? ? ? ? ? ? ? ? ? pr_err("SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? channel, count, 0xffff);
+ ? ? ? ? ? ? ? ? ? ? ? ret = -EINVAL;
+ ? ? ? ? ? ? ? ? ? ? ? goto err_out;
+ ? ? ? ? ? ? ? }
+
+ ? ? ? ? ? ? ? bd->mode.count = count;
+
+ ? ? ? ? ? ? ? if (sdma->word_size > 4) {
+ ? ? ? ? ? ? ? ? ? ? ? ret = ?-EINVAL;
+ ? ? ? ? ? ? ? ? ? ? ? goto err_out;
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? if (sdma->word_size == 4)
+ ? ? ? ? ? ? ? ? ? ? ? bd->mode.command = 0;
+ ? ? ? ? ? ? ? else
+ ? ? ? ? ? ? ? ? ? ? ? bd->mode.command = sdma->word_size;
+
+ ? ? ? ? ? ? ? param = BD_DONE | BD_EXTD | BD_CONT;
+
+ ? ? ? ? ? ? ? if (sdma->flags & IMX_DMA_SG_LOOP) {
+ ? ? ? ? ? ? ? ? ? ? ? param |= BD_INTR;
+ ? ? ? ? ? ? ? ? ? ? ? if (i + 1 == sg_len)
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param |= BD_WRAP;
+ ? ? ? ? ? ? ? }
+
+ ? ? ? ? ? ? ? if (i + 1 == sg_len)
+ ? ? ? ? ? ? ? ? ? ? ? param |= BD_INTR;
+
+ ? ? ? ? ? ? ? pr_debug("entry %d: count: %d dma: 0x%08x %s%s\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i, count, sg->dma_address,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param & BD_WRAP ? "wrap" : "",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param & BD_INTR ? " intr" : "");
+
+ ? ? ? ? ? ? ? bd->mode.status = param;
+ ? ? ? }
+
+ ? ? ? sdma->num_bd = sg_len;
+ ? ? ? channel_control[channel].current_bd_ptr = sdma->bd_phys;
+
+ ? ? ? return &sdma->desc;
+err_out:
+ ? ? ? return NULL;
+}
+

+static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
+ ? ? ? ? ? ? ? struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
+ ? ? ? ? ? ? ? size_t period_len, enum dma_data_direction direction)
+{
+ ? ? ? int num_periods = buf_len / period_len;
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? int channel = chan->chan_id;
+ ? ? ? int ret, i = 0, buf = 0;
+
+ ? ? ? pr_debug("%s channel: %d\n", __func__, channel);

+
+ ? ? ? if (sdma->busy)
+ ? ? ? ? ? ? ? return NULL;
+
+ ? ? ? sdma->busy = 1;
+
+ ? ? ? sdma->flags |= IMX_DMA_SG_LOOP;
+ ? ? ? sdma->direction = direction;
+ ? ? ? ret = sdma_load_context(channel);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_out;
+
+ ? ? ? if (num_periods > NUM_BD) {
+ ? ? ? ? ? ? ? pr_err("SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? channel, num_periods, NUM_BD);
+ ? ? ? ? ? ? ? goto err_out;
+ ? ? ? }
+
+ ? ? ? if (period_len > 0xffff) {
+ ? ? ? ? ? ? ? pr_err("SDMA channel %d: maximum period size exceeded: %d > %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? channel, period_len, 0xffff);
+ ? ? ? ? ? ? ? goto err_out;
+ ? ? ? }
+
+ ? ? ? while (buf < buf_len) {
+ ? ? ? ? ? ? ? struct sdma_buffer_descriptor *bd = &sdma->bd[i];
+ ? ? ? ? ? ? ? int param;
+
+ ? ? ? ? ? ? ? bd->buffer_addr = dma_addr;
+
+ ? ? ? ? ? ? ? bd->mode.count = period_len;
+
+ ? ? ? ? ? ? ? if (sdma->word_size > 4)
+ ? ? ? ? ? ? ? ? ? ? ? goto err_out;
+ ? ? ? ? ? ? ? if (sdma->word_size == 4)
+ ? ? ? ? ? ? ? ? ? ? ? bd->mode.command = 0;
+ ? ? ? ? ? ? ? else
+ ? ? ? ? ? ? ? ? ? ? ? bd->mode.command = sdma->word_size;
+
+ ? ? ? ? ? ? ? param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
+ ? ? ? ? ? ? ? if (i + 1 == num_periods)
+ ? ? ? ? ? ? ? ? ? ? ? param |= BD_WRAP;
+
+ ? ? ? ? ? ? ? pr_debug("entry %d: count: %d dma: 0x%08x %s%s\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i, period_len, dma_addr,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param & BD_WRAP ? "wrap" : "",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? param & BD_INTR ? " intr" : "");
+
+ ? ? ? ? ? ? ? bd->mode.status = param;
+
+ ? ? ? ? ? ? ? dma_addr += period_len;
+ ? ? ? ? ? ? ? buf += period_len;
+
+ ? ? ? ? ? ? ? i++;
+ ? ? ? }
+
+ ? ? ? sdma->num_bd = num_periods;
+ ? ? ? channel_control[channel].current_bd_ptr = sdma->bd_phys;
+
+ ? ? ? return &sdma->desc;
+err_out:
+ ? ? ? sdma->busy = 0;
+ ? ? ? return NULL;
+}
+
+static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ ? ? ? ? ? ? ? unsigned long arg)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? struct dma_slave_config *dmaengine_cfg = (void *)arg;
+
+ ? ? ? switch (cmd) {
+ ? ? ? case DMA_TERMINATE_ALL:
+ ? ? ? ? ? ? ? sdma_disable_channel(chan->chan_id);
+ ? ? ? ? ? ? ? return 0;
+ ? ? ? case DMA_SLAVE_CONFIG:
+ ? ? ? ? ? ? ? if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
+ ? ? ? ? ? ? ? ? ? ? ? sdma->per_address = dmaengine_cfg->src_addr;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->watermark_level = dmaengine_cfg->src_maxburst;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->word_size = dmaengine_cfg->src_addr_width;
+ ? ? ? ? ? ? ? } else {
+ ? ? ? ? ? ? ? ? ? ? ? sdma->per_address = dmaengine_cfg->dst_addr;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->watermark_level = dmaengine_cfg->dst_maxburst;
+ ? ? ? ? ? ? ? ? ? ? ? sdma->word_size = dmaengine_cfg->dst_addr_width;
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? return sdma_config_channel(chan->chan_id);
+ ? ? ? default:
+ ? ? ? ? ? ? ? return -ENOSYS;
+ ? ? ? }
+
+ ? ? ? return -EINVAL;
+}
+
+static enum dma_status sdma_tx_status(struct dma_chan *chan,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_cookie_t cookie,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_tx_state *txstate)
+{
+ ? ? ? struct sdma_channel *sdma = to_sdma_chan(chan);
+ ? ? ? dma_cookie_t last_used;
+ ? ? ? enum dma_status ret;
+
+ ? ? ? last_used = chan->cookie;
+
+ ? ? ? ret = dma_async_is_complete(cookie, sdma->last_completed, last_used);
+ ? ? ? dma_set_tx_state(txstate, sdma->last_completed, last_used, 0);
+
+ ? ? ? return ret;
+}
+
+static void sdma_issue_pending(struct dma_chan *chan)
+{
+ ? ? ? /*
+ ? ? ? ?* Nothing to do. We only have a single descriptor
+ ? ? ? ?*/
+}
+
+static int __devinit sdma_probe(struct platform_device *pdev)
+{
+ ? ? ? int ret;
+ ? ? ? const struct firmware *fw;
+ ? ? ? const struct sdma_firmware_header *header;
+ ? ? ? const struct sdma_script_start_addrs *addr;
+ ? ? ? int irq;
+ ? ? ? unsigned short *ram_code;
+ ? ? ? struct resource *iores;
+ ? ? ? struct sdma_platform_data *pdata = pdev->dev.platform_data;
+ ? ? ? int version;
+ ? ? ? char *cpustr, *fwname;
+ ? ? ? int i;
+ ? ? ? dma_cap_mask_t mask;
+
+ ? ? ? /* there can be only one */
+ ? ? ? BUG_ON(sdma_base);
+
+ ? ? ? iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ? ? ? irq = platform_get_irq(pdev, 0);
+ ? ? ? if (!iores || irq < 0 || !pdata)
+ ? ? ? ? ? ? ? return -EINVAL;
+
+ ? ? ? sdma_clk = clk_get(&pdev->dev, NULL);
+ ? ? ? if (IS_ERR(sdma_clk)) {
+ ? ? ? ? ? ? ? ret = PTR_ERR(sdma_clk);
+ ? ? ? ? ? ? ? goto err_clk;
+ ? ? ? }
+
+ ? ? ? if (cpu_is_mx31()) {
+ ? ? ? ? ? ? ? cpustr = "imx31";
+ ? ? ? ? ? ? ? version = mx31_revision() >> 4;
+ ? ? ? } else if (cpu_is_mx35()) {
+ ? ? ? ? ? ? ? cpustr = "imx35";
+/* FIXME: ? ? ?version = mx35_revision(); */
+ ? ? ? ? ? ? ? version = 2;
+ ? ? ? } else {
+ ? ? ? ? ? ? ? ret = -EINVAL;
+ ? ? ? ? ? ? ? goto err_cputype;
+ ? ? ? }
+
+ ? ? ? fwname = kasprintf(GFP_KERNEL, "sdma-%s-to%d.bin", cpustr, version);
+ ? ? ? if (!fwname) {
+ ? ? ? ? ? ? ? ret = -ENOMEM;
+ ? ? ? ? ? ? ? goto err_cputype;
+ ? ? ? }
+
+ ? ? ? ret = request_firmware(&fw, fwname, &pdev->dev);
+ ? ? ? if (ret) {
+ ? ? ? ? ? ? ? dev_err(&pdev->dev, "request firmware \"%s\" failed with %d\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fwname, ret);
+ ? ? ? ? ? ? ? kfree(fwname);
+ ? ? ? ? ? ? ? goto err_cputype;
+ ? ? ? }
+ ? ? ? kfree(fwname);
+
+ ? ? ? if (fw->size < sizeof(*header))
+ ? ? ? ? ? ? ? goto err_firmware;
+
+ ? ? ? header = (struct sdma_firmware_header *)fw->data;
+
+ ? ? ? if (header->magic != SDMA_FIRMWARE_MAGIC)
+ ? ? ? ? ? ? ? goto err_firmware;
+ ? ? ? if (header->ram_code_start + header->ram_code_size > fw->size)
+ ? ? ? ? ? ? ? goto err_firmware;
+
+ ? ? ? addr = (void *)header + header->script_addrs_start;
+ ? ? ? ram_code = (void *)header + header->ram_code_start;
+ ? ? ? memcpy(&__sdma_script_addrs, addr, sizeof(*addr));
+
+ ? ? ? ret = sdma_init(iores->start, irq, pdata->sdma_version,
+ ? ? ? ? ? ? ? ? ? ? ? ram_code, header->ram_code_size);
+ ? ? ? if (ret)
+ ? ? ? ? ? ? ? goto err_firmware;
+
+ ? ? ? INIT_LIST_HEAD(&sdma_dma_device->channels);
+
+ ? ? ? /* Initialize channel parameters */
+ ? ? ? for (i = 0; i < MAX_DMA_CHANNELS; i++) {
+ ? ? ? ? ? ? ? struct sdma_channel *sdma = &sdma_data[i];
+
+ ? ? ? ? ? ? ? spin_lock_init(&sdma->lock);
+
+ ? ? ? ? ? ? ? dma_cap_set(DMA_SLAVE, sdma_dma_device->cap_mask);
+ ? ? ? ? ? ? ? dma_cap_set(DMA_CYCLIC, sdma_dma_device->cap_mask);
+
+ ? ? ? ? ? ? ? sdma->chan.device = sdma_dma_device;
+ ? ? ? ? ? ? ? sdma->chan.chan_id = i;
+
+ ? ? ? ? ? ? ? /* Add the channel to the DMAC list */
+ ? ? ? ? ? ? ? list_add_tail(&sdma->chan.device_node, &sdma_dma_device->channels);
+ ? ? ? }
+
+ ? ? ? sdma_dma_device->dev = &pdev->dev;
+
+ ? ? ? sdma_dma_device->device_alloc_chan_resources = sdma_alloc_chan_resources;
+ ? ? ? sdma_dma_device->device_free_chan_resources = sdma_free_chan_resources;
+ ? ? ? sdma_dma_device->device_tx_status = sdma_tx_status;
+ ? ? ? sdma_dma_device->device_prep_slave_sg = sdma_prep_slave_sg;
+ ? ? ? sdma_dma_device->device_prep_dma_cyclic = sdma_prep_dma_cyclic;

+ ? ? ? sdma_dma_device->device_control = sdma_control;
+ ? ? ? sdma_dma_device->device_issue_pending = sdma_issue_pending;
+
+ ? ? ? ret = dma_async_device_register(sdma_dma_device);
+ ? ? ? if (ret) {
+ ? ? ? ? ? ? ? dev_err(&pdev->dev, "unable to register DMAC\n");

+ ? ? ? ? ? ? ? goto err_firmware;
+ ? ? ? }
+
+ ? ? ? dev_info(&pdev->dev, "initialized (firmware %d.%d)\n",
+ ? ? ? ? ? ? ? ? ? ? ? header->version_major,
+ ? ? ? ? ? ? ? ? ? ? ? header->version_minor);
+
+ ? ? ? /* request channel 0. This is an internal control channel
+ ? ? ? ?* to the SDMA engine and not available to clients.
+ ? ? ? ?*/
+ ? ? ? dma_cap_zero(mask);
+ ? ? ? dma_cap_set(DMA_SLAVE, mask);
+ ? ? ? dma_request_channel(mask, NULL, NULL);
+
+ ? ? ? release_firmware(fw);
+
+ ? ? ? return 0;
+
+err_firmware:
+ ? ? ? release_firmware(fw);
+err_cputype:
+ ? ? ? clk_put(sdma_clk);
+err_clk:
+ ? ? ? return 0;
+}
+
+static int __devexit sdma_remove(struct platform_device *pdev)
+{
+ ? ? ? return -EBUSY;
+}
+
+static struct platform_driver sdma_driver = {
+ ? ? ? .driver ? ? ? ? = {
+ ? ? ? ? ? ? ? .name ? = "imx-sdma",
+ ? ? ? },
+ ? ? ? .probe ? ? ? ? ?= sdma_probe,
+ ? ? ? .remove ? ? ? ? = __devexit_p(sdma_remove),
+};
+
+static int __init sdma_module_init(void)
+{
+ ? ? ? return platform_driver_register(&sdma_driver);
+}
+subsys_initcall(sdma_module_init);
+
+MODULE_AUTHOR("Sascha Hauer, Pengutronix <[email protected]>");
+MODULE_DESCRIPTION("i.MX SDMA driver");
+MODULE_LICENSE("GPL");
--

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
Regards,
Alexei Babich, circuit design engineer, Rezonans plc., Chelyabinsk, Russia
http://www.rez.ru
Jabber ID: impatt at jabber.ru
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
---
 arch/arm/mach-imx/include/mach/dma-v1.h |    8 +-
 arch/arm/mach-mx3/Kconfig               |    2 +
 arch/arm/plat-mxc/Kconfig               |   10 +
 arch/arm/plat-mxc/include/mach/dma.h    |   64 ++
 arch/arm/plat-mxc/include/mach/sdma.h   |   17 +
 drivers/dma/Kconfig                     |    8 +
 drivers/dma/Makefile                    |    1 +
 drivers/dma/imx-sdma.c                  | 1386 +++++++++++++++++++++++++++++++
 8 files changed, 1490 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/dma.h
 create mode 100644 arch/arm/plat-mxc/include/mach/sdma.h
 create mode 100644 drivers/dma/imx-sdma.c
index 287431c..ac6fd71 100644
@@ -27,6 +27,8 @@
 
 #define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 
+#include <mach/dma.h>
+
 #define IMX_DMA_CHANNELS  16
 
 #define DMA_MODE_READ		0

@@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name);
 
 void imx_dma_free(int channel);
 
-enum imx_dma_prio {
-	DMA_PRIO_HIGH = 0,
-	DMA_PRIO_MEDIUM = 1,
-	DMA_PRIO_LOW = 2
-};
-
 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 
 #endif	/* __MACH_DMA_V1_H__ */

index 85beece..301375c 100644
@@ -3,12 +3,14 @@ if ARCH_MX3
 config ARCH_MX31
 	select ARCH_HAS_RNGA
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 	bool
 
 config ARCH_MX35
 	bool
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 
 comment "MX3 platforms:"
 

index 0527e65..6741625 100644
@@ -109,4 +109,14 @@ config ARCH_MXC_AUDMUX_V1
 config ARCH_MXC_AUDMUX_V2
 	bool
 
+config IMX_HAVE_SDMA
+	bool
+
+config IMX_SDMA
+	depends on IMX_HAVE_SDMA
+	tristate "Enable SDMA support"
+	help
+	  Include support for the SDMA engine. The SDMA engine needs additional
+	  firmware support. SDMA can be compiled as a module to support loading
+	  the firmware when a rootfs is present.
 endif

new file mode 100644
index 0000000..9be1122
@@ -0,0 +1,17 @@
+#ifndef __MACH_MXC_SDMA_H__
+#define __MACH_MXC_SDMA_H__
+
+/**
+ * struct sdma_platform_data - platform specific data for SDMA engine
+ *
+ * @sdma_version	The version of this SDMA engine
+ * @cpu_name		used to generate the firmware name
+ * @to_version		CPU Tape out version
+ */
+struct sdma_platform_data {
+	int sdma_version;
+	char *cpu_name;
+	int to_version;
+};
+
+#endif /* __MACH_MXC_SDMA_H__ */

index 9520cf0..ff68307 100644
@@ -195,6 +195,14 @@ config PCH_DMA
 	help
 	  Enable support for the Topcliff PCH DMA engine.
 
+config IMX_SDMA
+	tristate "i.MX SDMA support"
+	depends on ARCH_MXC
+	select DMA_ENGINE
+	help
+	  Support the i.MX SDMA engine. This engine is integrated into
+	  Freescale i.MX25/31/35/51 chips.
+
 config DMA_ENGINE
 	bool
 

index 72bd703..14d7a1b 100644
@@ -25,3 +25,4 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
 obj-$(CONFIG_PCH_DMA) += pch_dma.o
+obj-$(CONFIG_IMX_SDMA) += imx-sdma.o

1.7.1

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
+/*
+ * Buffer descriptor
+ */
+struct sdma_buffer_descriptor {
+ ? ? ? struct sdma_mode_count ?mode;
+ ? ? ? u32 buffer_addr; ? ?/* address of the buffer described */
+ ? ? ? u32 ext_buffer_addr; /* extended buffer address */

---
 arch/arm/mach-imx/include/mach/dma-v1.h |    8 +-
 arch/arm/mach-mx3/Kconfig               |    2 +
 arch/arm/plat-mxc/Kconfig               |   10 +
 arch/arm/plat-mxc/include/mach/dma.h    |   64 ++
 arch/arm/plat-mxc/include/mach/sdma.h   |   17 +
 drivers/dma/Kconfig                     |    8 +
 drivers/dma/Makefile                    |    1 +
 drivers/dma/imx-sdma.c                  | 1395 +++++++++++++++++++++++++++++++
 8 files changed, 1499 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/dma.h
 create mode 100644 arch/arm/plat-mxc/include/mach/sdma.h
 create mode 100644 drivers/dma/imx-sdma.c
index 287431c..ac6fd71 100644
@@ -27,6 +27,8 @@
 
 #define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 
+#include <mach/dma.h>
+
 #define IMX_DMA_CHANNELS  16
 
 #define DMA_MODE_READ		0

@@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name);
 
 void imx_dma_free(int channel);
 
-enum imx_dma_prio {
-	DMA_PRIO_HIGH = 0,
-	DMA_PRIO_MEDIUM = 1,
-	DMA_PRIO_LOW = 2
-};
-
 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 
 #endif	/* __MACH_DMA_V1_H__ */

index 85beece..301375c 100644
@@ -3,12 +3,14 @@ if ARCH_MX3
 config ARCH_MX31
 	select ARCH_HAS_RNGA
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 	bool
 
 config ARCH_MX35
 	bool
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 
 comment "MX3 platforms:"
 

index 0527e65..6741625 100644
@@ -109,4 +109,14 @@ config ARCH_MXC_AUDMUX_V1
 config ARCH_MXC_AUDMUX_V2
 	bool
 
+config IMX_HAVE_SDMA
+	bool
+
+config IMX_SDMA
+	depends on IMX_HAVE_SDMA
+	tristate "Enable SDMA support"
+	help
+	  Include support for the SDMA engine. The SDMA engine needs additional
+	  firmware support. SDMA can be compiled as a module to support loading
+	  the firmware when a rootfs is present.
 endif

new file mode 100644
index 0000000..9be1122
@@ -0,0 +1,17 @@
+#ifndef __MACH_MXC_SDMA_H__
+#define __MACH_MXC_SDMA_H__
+
+/**
+ * struct sdma_platform_data - platform specific data for SDMA engine
+ *
+ * @sdma_version	The version of this SDMA engine
+ * @cpu_name		used to generate the firmware name
+ * @to_version		CPU Tape out version
+ */
+struct sdma_platform_data {
+	int sdma_version;
+	char *cpu_name;
+	int to_version;
+};
+
+#endif /* __MACH_MXC_SDMA_H__ */

index 9520cf0..ff68307 100644
@@ -195,6 +195,14 @@ config PCH_DMA
 	help
 	  Enable support for the Topcliff PCH DMA engine.
 
+config IMX_SDMA
+	tristate "i.MX SDMA support"
+	depends on ARCH_MXC
+	select DMA_ENGINE
+	help
+	  Support the i.MX SDMA engine. This engine is integrated into
+	  Freescale i.MX25/31/35/51 chips.
+
 config DMA_ENGINE
 	bool
 

index 72bd703..14d7a1b 100644
@@ -25,3 +25,4 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
 obj-$(CONFIG_PCH_DMA) += pch_dma.o
+obj-$(CONFIG_IMX_SDMA) += imx-sdma.o

1.7.1

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
(...)
+/* SDMA registers */
+#define SDMA_H_C0PTR ? ? ? ? ? (sdma->regs + 0x000)
+#define SDMA_H_INTR ? ? ? ? ? ?(sdma->regs + 0x004)
+#define SDMA_H_STATSTOP ? ? ? ? ? ? ? ?(sdma->regs + 0x008)
+#define SDMA_H_START ? ? ? ? ? (sdma->regs + 0x00c)
+#define SDMA_H_EVTOVR ? ? ? ? ?(sdma->regs + 0x010)
+#define SDMA_H_DSPOVR ? ? ? ? ?(sdma->regs + 0x014)
+#define SDMA_H_HOSTOVR ? ? ? ? (sdma->regs + 0x018)
+#define SDMA_H_EVTPEND ? ? ? ? (sdma->regs + 0x01c)
+#define SDMA_H_DSPENBL ? ? ? ? (sdma->regs + 0x020)
+#define SDMA_H_RESET ? ? ? ? ? (sdma->regs + 0x024)
+#define SDMA_H_EVTERR ? ? ? ? ?(sdma->regs + 0x028)
+#define SDMA_H_INTRMSK ? ? ? ? (sdma->regs + 0x02c)
+#define SDMA_H_PSW ? ? ? ? ? ? (sdma->regs + 0x030)
+#define SDMA_H_EVTERRDBG ? ? ? (sdma->regs + 0x034)
+#define SDMA_H_CONFIG ? ? ? ? ?(sdma->regs + 0x038)
+#define SDMA_ONCE_ENB ? ? ? ? ?(sdma->regs + 0x040)
+#define SDMA_ONCE_DATA ? ? ? ? (sdma->regs + 0x044)
+#define SDMA_ONCE_INSTR ? ? ? ? ? ? ? ?(sdma->regs + 0x048)

+#define SDMA_ONCE_STAT ? ? ? ? (sdma->regs + 0x04c)
+#define SDMA_ONCE_CMD ? ? ? ? ?(sdma->regs + 0x050)
+#define SDMA_EVT_MIRROR ? ? ? ? ? ? ? ?(sdma->regs + 0x054)
+#define SDMA_ILLINSTADDR ? ? ? (sdma->regs + 0x058)
+#define SDMA_CHN0ADDR ? ? ? ? ?(sdma->regs + 0x05c)
+#define SDMA_ONCE_RTB ? ? ? ? ?(sdma->regs + 0x060)
+#define SDMA_XTRIG_CONF1 ? ? ? (sdma->regs + 0x070)
+#define SDMA_XTRIG_CONF2 ? ? ? (sdma->regs + 0x074)
+#define SDMA_CHNENBL_0 ? ? ? ? (sdma->regs + (sdma->version == 2 ? 0x200 : 0x80))
+#define SDMA_CHNPRI_0 ? ? ? ? ?(sdma->regs + 0x100)

+struct sdma_channel_control {
+ ? ? ? dma_addr_t current_bd_ptr; /* current buffer descriptor processed */
+ ? ? ? dma_addr_t base_bd_ptr; ? ?/* first element of buffer descriptor array */
+ ? ? ? u32 unused;
+ ? ? ? u32 unused1;
+} __attribute__ ((packed));
 
(...)
+/**
+ * struct sdma_channel - housekeeping for a SDMA channel
+ *
+ * @sdma ? ? ? ? ? ? ? pointer to the SDMA engine for this channel
+ * @channel ? ? ? ? ? ?the channel number, matches dmaengine chan_id
+ * @direction ? ? ? ? ?transfer type. Needed for setting SDMA script
+ * @peripheral_type ? ?Peripheral type. Needed for setting SDMA script
+ * @event_id ? ? ? ? ? aka dma request line
+ * @event_id2 ? ? ? ? ?for channels that use 2 events
+ * @word_size ? ? ? ? ?peripheral access size
+ * @buf_tail ? ? ? ? ? ID of the buffer that was processed

+ * @done ? ? ? ? ? ? ? channel completion
+ * @num_bd ? ? ? ? ? ? max NUM_BD. number of descriptors currently handling
+ */
+struct sdma_channel {
+ ? ? ? struct sdma_engine ? ? ? ? ? ? ?*sdma;
+ ? ? ? unsigned int ? ? ? ? ? ? ? ? ? ?channel;
+ ? ? ? enum dma_data_direction ? ? ? ? direction;
+ ? ? ? enum sdma_peripheral_type ? ? ? peripheral_type;
+ ? ? ? unsigned int ? ? ? ? ? ? ? ? ? ?event_id;
+ ? ? ? unsigned int ? ? ? ? ? ? ? ? ? ?event_id2;

+};
+
+#define IMX_DMA_SG_LOOP ? ? ? ? ? ? ? ?(1 << 0)
+
+#define MAX_DMA_CHANNELS 32
+#define MXC_SDMA_DEFAULT_PRIORITY 1
+#define MXC_SDMA_MIN_PRIORITY 1
+#define MXC_SDMA_MAX_PRIORITY 7
+
+/*
+ * This enumerates transfer types
+ */
+enum {
+ ? ? ? emi_2_per = 0, ? ? ? ? ?/* EMI memory to peripheral */
+ ? ? ? emi_2_int, ? ? ? ? ? ? ?/* EMI memory to internal RAM */
+ ? ? ? emi_2_emi, ? ? ? ? ? ? ?/* EMI memory to EMI memory */
+ ? ? ? emi_2_dsp, ? ? ? ? ? ? ?/* EMI memory to DSP memory */
+ ? ? ? per_2_int, ? ? ? ? ? ? ?/* Peripheral to internal RAM */
+ ? ? ? per_2_emi, ? ? ? ? ? ? ?/* Peripheral to internal EMI memory */
+ ? ? ? per_2_dsp, ? ? ? ? ? ? ?/* Peripheral to DSP memory */
+ ? ? ? per_2_per, ? ? ? ? ? ? ?/* Peripheral to Peripheral */
+ ? ? ? int_2_per, ? ? ? ? ? ? ?/* Internal RAM to peripheral */
+ ? ? ? int_2_int, ? ? ? ? ? ? ?/* Internal RAM to Internal RAM */
+ ? ? ? int_2_emi, ? ? ? ? ? ? ?/* Internal RAM to EMI memory */

+ ? ? ? int_2_dsp, ? ? ? ? ? ? ?/* Internal RAM to DSP memory */
+ ? ? ? dsp_2_per, ? ? ? ? ? ? ?/* DSP memory to peripheral */
+ ? ? ? dsp_2_int, ? ? ? ? ? ? ?/* DSP memory to internal RAM */
+ ? ? ? dsp_2_emi, ? ? ? ? ? ? ?/* DSP memory to EMI memory */
+ ? ? ? dsp_2_dsp, ? ? ? ? ? ? ?/* DSP memory to DSP memory */
+ ? ? ? emi_2_dsp_loop, ? ? ? ? /* EMI memory to DSP memory loopback */
+ ? ? ? dsp_2_emi_loop, ? ? ? ? /* DSP memory to EMI memory loopback */
+ ? ? ? dvfs_pll, ? ? ? ? ? ? ? /* DVFS script with PLL change ? ? ? */
+ ? ? ? dvfs_pdr ? ? ? ? ? ? ? ?/* DVFS script without PLL change ? ?*/
+} sdma_transfer_type;

+/*
+ * Stores the start address of the SDMA scripts
+ */
+static struct sdma_script_start_addrs __sdma_script_addrs;
+static struct sdma_script_start_addrs *sdma_script_addrs = &__sdma_script_addrs;

(...)
+/* SDMA registers */
+#define SDMA_H_C0PTR ? ? ? ? ? (sdma->regs + 0x000)
+#define SDMA_H_INTR ? ? ? ? ? ?(sdma->regs + 0x004)
+#define SDMA_H_STATSTOP ? ? ? ? ? ? ? ?(sdma->regs + 0x008)
+#define SDMA_H_START ? ? ? ? ? (sdma->regs + 0x00c)
+#define SDMA_H_EVTOVR ? ? ? ? ?(sdma->regs + 0x010)
+#define SDMA_H_DSPOVR ? ? ? ? ?(sdma->regs + 0x014)
+#define SDMA_H_HOSTOVR ? ? ? ? (sdma->regs + 0x018)
+#define SDMA_H_EVTPEND ? ? ? ? (sdma->regs + 0x01c)
+#define SDMA_H_DSPENBL ? ? ? ? (sdma->regs + 0x020)
+#define SDMA_H_RESET ? ? ? ? ? (sdma->regs + 0x024)
+#define SDMA_H_EVTERR ? ? ? ? ?(sdma->regs + 0x028)
+#define SDMA_H_INTRMSK ? ? ? ? (sdma->regs + 0x02c)
+#define SDMA_H_PSW ? ? ? ? ? ? (sdma->regs + 0x030)
+#define SDMA_H_EVTERRDBG ? ? ? (sdma->regs + 0x034)
+#define SDMA_H_CONFIG ? ? ? ? ?(sdma->regs + 0x038)
+#define SDMA_ONCE_ENB ? ? ? ? ?(sdma->regs + 0x040)
+#define SDMA_ONCE_DATA ? ? ? ? (sdma->regs + 0x044)
+#define SDMA_ONCE_INSTR ? ? ? ? ? ? ? ?(sdma->regs + 0x048)

+#define SDMA_ONCE_STAT ? ? ? ? (sdma->regs + 0x04c)
+#define SDMA_ONCE_CMD ? ? ? ? ?(sdma->regs + 0x050)
+#define SDMA_EVT_MIRROR ? ? ? ? ? ? ? ?(sdma->regs + 0x054)
+#define SDMA_ILLINSTADDR ? ? ? (sdma->regs + 0x058)
+#define SDMA_CHN0ADDR ? ? ? ? ?(sdma->regs + 0x05c)
+#define SDMA_ONCE_RTB ? ? ? ? ?(sdma->regs + 0x060)
+#define SDMA_XTRIG_CONF1 ? ? ? (sdma->regs + 0x070)
+#define SDMA_XTRIG_CONF2 ? ? ? (sdma->regs + 0x074)
+#define SDMA_CHNENBL_0 ? ? ? ? (sdma->regs + (sdma->version == 2 ? 0x200 : 0x80))
+#define SDMA_CHNPRI_0 ? ? ? ? ?(sdma->regs + 0x100)

+
+/*
+ * This enumerates transfer types
+ */
+enum {
+ ? ? ? emi_2_per = 0, ? ? ? ? ?/* EMI memory to peripheral */
+ ? ? ? emi_2_int, ? ? ? ? ? ? ?/* EMI memory to internal RAM */
+ ? ? ? emi_2_emi, ? ? ? ? ? ? ?/* EMI memory to EMI memory */
+ ? ? ? emi_2_dsp, ? ? ? ? ? ? ?/* EMI memory to DSP memory */
+ ? ? ? per_2_int, ? ? ? ? ? ? ?/* Peripheral to internal RAM */
+ ? ? ? per_2_emi, ? ? ? ? ? ? ?/* Peripheral to internal EMI memory */
+ ? ? ? per_2_dsp, ? ? ? ? ? ? ?/* Peripheral to DSP memory */
+ ? ? ? per_2_per, ? ? ? ? ? ? ?/* Peripheral to Peripheral */
+ ? ? ? int_2_per, ? ? ? ? ? ? ?/* Internal RAM to peripheral */
+ ? ? ? int_2_int, ? ? ? ? ? ? ?/* Internal RAM to Internal RAM */
+ ? ? ? int_2_emi, ? ? ? ? ? ? ?/* Internal RAM to EMI memory */

+ ? ? ? int_2_dsp, ? ? ? ? ? ? ?/* Internal RAM to DSP memory */
+ ? ? ? dsp_2_per, ? ? ? ? ? ? ?/* DSP memory to peripheral */
+ ? ? ? dsp_2_int, ? ? ? ? ? ? ?/* DSP memory to internal RAM */
+ ? ? ? dsp_2_emi, ? ? ? ? ? ? ?/* DSP memory to EMI memory */
+ ? ? ? dsp_2_dsp, ? ? ? ? ? ? ?/* DSP memory to DSP memory */
+ ? ? ? emi_2_dsp_loop, ? ? ? ? /* EMI memory to DSP memory loopback */
+ ? ? ? dsp_2_emi_loop, ? ? ? ? /* DSP memory to EMI memory loopback */
+ ? ? ? dvfs_pll, ? ? ? ? ? ? ? /* DVFS script with PLL change ? ? ? */
+ ? ? ? dvfs_pdr ? ? ? ? ? ? ? ?/* DVFS script without PLL change ? ?*/
+} sdma_transfer_type;

+/*
+ * Stores the start address of the SDMA scripts
+ */
+static struct sdma_script_start_addrs __sdma_script_addrs;
+static struct sdma_script_start_addrs *sdma_script_addrs = &__sdma_script_addrs;

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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---
 arch/arm/mach-imx/include/mach/dma-v1.h |    8 +-
 arch/arm/mach-mx3/Kconfig               |    2 +
 arch/arm/plat-mxc/Kconfig               |   10 +
 arch/arm/plat-mxc/include/mach/dma.h    |   64 ++
 arch/arm/plat-mxc/include/mach/sdma.h   |   17 +
 drivers/dma/Kconfig                     |    8 +
 drivers/dma/Makefile                    |    1 +
 drivers/dma/imx-sdma.c                  | 1395 +++++++++++++++++++++++++++++++
 8 files changed, 1499 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/dma.h
 create mode 100644 arch/arm/plat-mxc/include/mach/sdma.h
 create mode 100644 drivers/dma/imx-sdma.c
index 287431c..ac6fd71 100644
@@ -27,6 +27,8 @@
 
 #define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 
+#include <mach/dma.h>
+
 #define IMX_DMA_CHANNELS  16
 
 #define DMA_MODE_READ		0

@@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name);
 
 void imx_dma_free(int channel);
 
-enum imx_dma_prio {
-	DMA_PRIO_HIGH = 0,
-	DMA_PRIO_MEDIUM = 1,
-	DMA_PRIO_LOW = 2
-};
-
 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 
 #endif	/* __MACH_DMA_V1_H__ */

index 85beece..301375c 100644
@@ -3,12 +3,14 @@ if ARCH_MX3
 config ARCH_MX31
 	select ARCH_HAS_RNGA
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 	bool
 
 config ARCH_MX35
 	bool
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 
 comment "MX3 platforms:"
 

index 0527e65..6741625 100644
@@ -109,4 +109,14 @@ config ARCH_MXC_AUDMUX_V1
 config ARCH_MXC_AUDMUX_V2
 	bool
 
+config IMX_HAVE_SDMA
+	bool
+
+config IMX_SDMA
+	depends on IMX_HAVE_SDMA
+	tristate "Enable SDMA support"
+	help
+	  Include support for the SDMA engine. The SDMA engine needs additional
+	  firmware support. SDMA can be compiled as a module to support loading
+	  the firmware when a rootfs is present.
 endif

new file mode 100644
index 0000000..69d181f

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_DMA_H__
+#define __ASM_ARCH_MXC_DMA_H__

+
+#include <linux/scatterlist.h>
+
+/*
+ * This enumerates peripheral types. Used for SDMA.
+ */
+enum sdma_peripheral_type {
+	IMX_DMATYPE_SSI,	/* MCU domain SSI */
+	IMX_DMATYPE_SSI_SP,	/* Shared SSI */
+	IMX_DMATYPE_MMC,	/* MMC */
+	IMX_DMATYPE_SDHC,	/* SDHC */
+	IMX_DMATYPE_UART,	/* MCU domain UART */
+	IMX_DMATYPE_UART_SP,	/* Shared UART */
+	IMX_DMATYPE_FIRI,	/* FIRI */
+	IMX_DMATYPE_CSPI,	/* MCU domain CSPI */
+	IMX_DMATYPE_CSPI_SP,	/* Shared CSPI */
+	IMX_DMATYPE_SIM,	/* SIM */
+	IMX_DMATYPE_ATA,	/* ATA */
+	IMX_DMATYPE_CCM,	/* CCM */
+	IMX_DMATYPE_EXT,	/* External peripheral */
+	IMX_DMATYPE_MSHC,	/* Memory Stick Host Controller */
+	IMX_DMATYPE_MSHC_SP,	/* Shared Memory Stick Host Controller */
+	IMX_DMATYPE_DSP,	/* DSP */
+	IMX_DMATYPE_MEMORY,	/* Memory */
+	IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
+	IMX_DMATYPE_SPDIF,	/* SPDIF */
+	IMX_DMATYPE_IPU_MEMORY,	/* IPU Memory */
+	IMX_DMATYPE_ASRC,	/* ASRC */
+	IMX_DMATYPE_ESAI,	/* ESAI */
+};
+
+enum imx_dma_prio {
+	DMA_PRIO_HIGH = 0,
+	DMA_PRIO_MEDIUM = 1,
+	DMA_PRIO_LOW = 2
+};
+
+struct imx_dma_data {
+	int dma_request; /* DMA request line */
+	enum sdma_peripheral_type peripheral_type;
+	int priority;
+};
+
+static inline int imx_dma_is_ipu(struct dma_chan *chan)
+{
+	return !strcmp(dev_name(chan->device->dev), "ipu-core");
+}
+
+static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
+{
+	return !strcmp(dev_name(chan->device->dev), "imx-sdma");
+}
+
+#endif

new file mode 100644
index 0000000..9be1122

@@ -0,0 +1,17 @@
+#ifndef __MACH_MXC_SDMA_H__
+#define __MACH_MXC_SDMA_H__

+
+/**
+ * struct sdma_platform_data - platform specific data for SDMA engine
+ *
+ * @sdma_version	The version of this SDMA engine
+ * @cpu_name		used to generate the firmware name
+ * @to_version		CPU Tape out version
+ */
+struct sdma_platform_data {
+	int sdma_version;
+	char *cpu_name;
+	int to_version;
+};
+
+#endif /* __MACH_MXC_SDMA_H__ */

index 9520cf0..ff68307 100644
@@ -195,6 +195,14 @@ config PCH_DMA
 	help
 	  Enable support for the Topcliff PCH DMA engine.
 
+config IMX_SDMA
+	tristate "i.MX SDMA support"
+	depends on ARCH_MXC
+	select DMA_ENGINE
+	help
+	  Support the i.MX SDMA engine. This engine is integrated into
+	  Freescale i.MX25/31/35/51 chips.
+
 config DMA_ENGINE
 	bool
 

index 72bd703..14d7a1b 100644
@@ -25,3 +25,4 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
 obj-$(CONFIG_PCH_DMA) += pch_dma.o
+obj-$(CONFIG_IMX_SDMA) += imx-sdma.o

new file mode 100644
index 0000000..c447fc0
@@ -0,0 +1,1395 @@
+/*
+ * drivers/dma/imx-sdma.c
+ *
+ * This file contains a driver for the Freescale Smart DMA engine
+ *
+ * Copyright 2010 Sascha Hauer, Pengutronix <[email protected]>
+ *
+ * Based on code from Freescale:
+ *
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/semaphore.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/dmaengine.h>
+
+#include <asm/irq.h>
+#include <mach/sdma.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
+
+/* SDMA registers */
+#define SDMA_H_C0PTR		(sdma->regs + 0x000)
+#define SDMA_H_INTR		(sdma->regs + 0x004)
+#define SDMA_H_STATSTOP		(sdma->regs + 0x008)
+#define SDMA_H_START		(sdma->regs + 0x00c)
+#define SDMA_H_EVTOVR		(sdma->regs + 0x010)
+#define SDMA_H_DSPOVR		(sdma->regs + 0x014)
+#define SDMA_H_HOSTOVR		(sdma->regs + 0x018)
+#define SDMA_H_EVTPEND		(sdma->regs + 0x01c)
+#define SDMA_H_DSPENBL		(sdma->regs + 0x020)
+#define SDMA_H_RESET		(sdma->regs + 0x024)
+#define SDMA_H_EVTERR		(sdma->regs + 0x028)
+#define SDMA_H_INTRMSK		(sdma->regs + 0x02c)
+#define SDMA_H_PSW		(sdma->regs + 0x030)
+#define SDMA_H_EVTERRDBG	(sdma->regs + 0x034)
+#define SDMA_H_CONFIG		(sdma->regs + 0x038)
+#define SDMA_ONCE_ENB		(sdma->regs + 0x040)
+#define SDMA_ONCE_DATA		(sdma->regs + 0x044)
+#define SDMA_ONCE_INSTR		(sdma->regs + 0x048)

+#define SDMA_ONCE_STAT		(sdma->regs + 0x04c)
+#define SDMA_ONCE_CMD		(sdma->regs + 0x050)
+#define SDMA_EVT_MIRROR		(sdma->regs + 0x054)
+#define SDMA_ILLINSTADDR	(sdma->regs + 0x058)
+#define SDMA_CHN0ADDR		(sdma->regs + 0x05c)
+#define SDMA_ONCE_RTB		(sdma->regs + 0x060)
+#define SDMA_XTRIG_CONF1	(sdma->regs + 0x070)
+#define SDMA_XTRIG_CONF2	(sdma->regs + 0x074)
+#define SDMA_CHNENBL_0		(sdma->regs + (sdma->version == 2 ? 0x200 : 0x80))
+#define SDMA_CHNPRI_0		(sdma->regs + 0x100)

	u32 sdma_read(struct whatever *sdma, unsigned offset)
	{
		return __raw_readl(sdma->regs + offset);
	}
	...
+
+/*
+ * Buffer descriptor status values.
+ */
+#define BD_DONE  0x01
+#define BD_WRAP  0x02
+#define BD_CONT  0x04
+#define BD_INTR  0x08
+#define BD_RROR  0x10
+#define BD_LAST  0x20
+#define BD_EXTD  0x80
+
+/*
+ * Data Node descriptor status values.
+ */
+#define DND_END_OF_FRAME  0x80
+#define DND_END_OF_XFER   0x40
+#define DND_DONE          0x20
+#define DND_UNUSED        0x01
+
+/*
+ * IPCV2 descriptor status values.
+ */
+#define BD_IPCV2_END_OF_FRAME  0x40
+
+#define IPCV2_MAX_NODES        50
+/*
+ * Error bit set in the CCB status field by the SDMA,
+ * in setbd routine, in case of a transfer error
+ */
+#define DATA_ERROR  0x10000000
+
+/*
+ * Buffer descriptor commands.
+ */
+#define C0_ADDR             0x01
+#define C0_LOAD             0x02
+#define C0_DUMP             0x03
+#define C0_SETCTX           0x07
+#define C0_GETCTX           0x03
+#define C0_SETDM            0x01
+#define C0_SETPM            0x04
+#define C0_GETDM            0x02
+#define C0_GETPM            0x08
+/*
+ * Change endianness indicator in the BD command field

+ */
+#define CHANGE_ENDIANNESS   0x80
+
+/*
+ * Mode/Count of data node descriptors - IPCv2
+ */
+struct sdma_mode_count {
+	u32 count   : 16; /* size of the buffer pointed by this BD */
+	u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
+	u32 command :  8; /* command mostlky used for channel 0 */

+};
+
+/*
+ * Buffer descriptor
+ */
+struct sdma_buffer_descriptor {
+	struct sdma_mode_count  mode;
+	dma_addr_t buffer_addr;    /* address of the buffer described */
+	dma_addr_t ext_buffer_addr; /* extended buffer address */
+} __attribute__ ((packed));
+
+/*
+ * Channel control Block
+ */
+struct sdma_channel_control {
+	dma_addr_t current_bd_ptr; /* current buffer descriptor processed */
+	dma_addr_t base_bd_ptr;    /* first element of buffer descriptor array */
+	u32 unused;
+	u32 unused1;
+} __attribute__ ((packed));
+
+/**
+ * struct sdma_state_registers - SDMA context for a channel
+ *
+ * @pc:		program counter
+ * @t:		test bit: status of arithmetic & test instruction
+ * @rpc:	return program counter
+ * @sf:		source fault while loading data
+ * @spc:	loop start program counter
+ * @df:		destination fault while storing data
+ * @epc:	loop end program counter
+ * @lm:		loop mode
+ */
+struct sdma_state_registers {
+	u32 pc     :14;
+	u32 unused1: 1;

+	u32 t      : 1;
+	u32 rpc    :14;
+	u32 unused0: 1;
+	u32 sf     : 1;
+	u32 spc    :14;
+	u32 unused2: 1;
+	u32 df     : 1;
+	u32 epc    :14;
+	u32 lm     : 2;
+} __attribute__ ((packed));

+
+/**
+ * struct sdma_context_data - sdma context specific to a channel
+ *
+ * @channel_state:	channel state bits
+ * @gReg:		general registers
+ * @mda:		burst dma destination address register
+ * @msa:		burst dma source address register
+ * @ms:			burst dma status register
+ * @md:			burst dma data register
+ * @pda:		peripheral dma destination address register
+ * @psa:		peripheral dma source address register
+ * @ps:			peripheral dma status register
+ * @pd:			peripheral dma data register
+ * @ca:			CRC polynomial register
+ * @cs:			CRC accumulator register
+ * @dda:		dedicated core destination address register
+ * @dsa:		dedicated core source address register
+ * @ds:			dedicated core status register
+ * @dd:			dedicated core data register
+ */
+struct sdma_context_data {
+	struct sdma_state_registers  channel_state;
+	u32  gReg[8];
+	u32  mda;
+	u32  msa;
+	u32  ms;
+	u32  md;
+	u32  pda;
+	u32  psa;
+	u32  ps;
+	u32  pd;
+	u32  ca;
+	u32  cs;
+	u32  dda;
+	u32  dsa;
+	u32  ds;

+	u32  dd;
+	u32  scratch0;
+	u32  scratch1;
+	u32  scratch2;
+	u32  scratch3;
+	u32  scratch4;
+	u32  scratch5;
+	u32  scratch6;
+	u32  scratch7;
+} __attribute__ ((packed));

+
+#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
+
+struct sdma_engine;
+
+/**
+ * struct sdma_channel - housekeeping for a SDMA channel
+ *
+ * @sdma		pointer to the SDMA engine for this channel
+ * @channel		the channel number, matches dmaengine chan_id
+ * @direction		transfer type. Needed for setting SDMA script
+ * @peripheral_type	Peripheral type. Needed for setting SDMA script
+ * @event_id		aka dma request line
+ * @event_id2		for channels that use 2 events
+ * @word_size		peripheral access size
+ * @buf_tail		ID of the buffer that was processed
+ * @done		channel completion
+ * @num_bd		max NUM_BD. number of descriptors currently handling
+ */
+struct sdma_channel {
+	struct sdma_engine		*sdma;
+	unsigned int			channel;
+	enum dma_data_direction		direction;
+	enum sdma_peripheral_type	peripheral_type;
+	unsigned int			event_id;
+	unsigned int			event_id2;
+	enum dma_slave_buswidth		word_size;
+	unsigned int			buf_tail;
+	struct completion		done;
+	unsigned int			num_bd;
+	struct sdma_buffer_descriptor	*bd;
+	dma_addr_t			bd_phys;
+	unsigned int			pc_from_device, pc_to_device;
+	unsigned long			flags;
+	dma_addr_t			per_address;
+	u32				event_mask1, event_mask2;
+	u32				watermark_level;
+	u32				shp_addr, per_addr;
+	struct dma_chan			chan;
+	spinlock_t			lock;
+	struct dma_async_tx_descriptor	desc;
+	dma_cookie_t			last_completed;
+	enum dma_status			status;
+};
+
+#define IMX_DMA_SG_LOOP		(1 << 0)
+
+#define MAX_DMA_CHANNELS 32
+#define MXC_SDMA_DEFAULT_PRIORITY 1
+#define MXC_SDMA_MIN_PRIORITY 1
+#define MXC_SDMA_MAX_PRIORITY 7

+
+/*
+ * This enumerates transfer types
+ */
+enum {
+	emi_2_per = 0,		/* EMI memory to peripheral */
+	emi_2_int,		/* EMI memory to internal RAM */
+	emi_2_emi,		/* EMI memory to EMI memory */
+	emi_2_dsp,		/* EMI memory to DSP memory */
+	per_2_int,		/* Peripheral to internal RAM */

+	per_2_emi,		/* Peripheral to internal EMI memory */
+	per_2_dsp,		/* Peripheral to DSP memory */
+	per_2_per,		/* Peripheral to Peripheral */
+	int_2_per,		/* Internal RAM to peripheral */
+	int_2_int,		/* Internal RAM to Internal RAM */
+	int_2_emi,		/* Internal RAM to EMI memory */
+	int_2_dsp,		/* Internal RAM to DSP memory */
+	dsp_2_per,		/* DSP memory to peripheral */
+	dsp_2_int,		/* DSP memory to internal RAM */
+	dsp_2_emi,		/* DSP memory to EMI memory */
+	dsp_2_dsp,		/* DSP memory to DSP memory */
+	emi_2_dsp_loop,		/* EMI memory to DSP memory loopback */
+	dsp_2_emi_loop,		/* DSP memory to EMI memory loopback */
+	dvfs_pll,		/* DVFS script with PLL change       */
+	dvfs_pdr		/* DVFS script without PLL change    */
+} sdma_transfer_type;
+
+/**
+ * struct sdma_script_start_addrs - SDMA script start pointers
+ *
+ * start addresses of the different functions in the physical
+ * address space of the SDMA engine.
+ */
+struct sdma_script_start_addrs {
+	u32 ap_2_ap_addr;
+	u32 ap_2_bp_addr;
+	u32 ap_2_ap_fixed_addr;
+	u32 bp_2_ap_addr;
+	u32 loopback_on_dsp_side_addr;
+	u32 mcu_interrupt_only_addr;
+	u32 firi_2_per_addr;
+	u32 firi_2_mcu_addr;
+	u32 per_2_firi_addr;
+	u32 mcu_2_firi_addr;
+	u32 uart_2_per_addr;
+	u32 uart_2_mcu_addr;
+	u32 per_2_app_addr;
+	u32 mcu_2_app_addr;
+	u32 per_2_per_addr;
+	u32 uartsh_2_per_addr;
+	u32 uartsh_2_mcu_addr;
+	u32 per_2_shp_addr;
+	u32 mcu_2_shp_addr;
+	u32 ata_2_mcu_addr;
+	u32 mcu_2_ata_addr;
+	u32 app_2_per_addr;
+	u32 app_2_mcu_addr;
+	u32 shp_2_per_addr;
+	u32 shp_2_mcu_addr;
+	u32 mshc_2_mcu_addr;

+	u32 mcu_2_mshc_addr;
+	u32 spdif_2_mcu_addr;
+	u32 mcu_2_spdif_addr;
+	u32 asrc_2_mcu_addr;
+	u32 ext_mem_2_ipu_addr;
+	u32 descrambler_addr;
+	u32 dptc_dvfs_addr;
+	u32 utra_addr;
+	u32 ram_code_start_addr;
+};

	struct {
		const char *name;
		u32 addr;
	} start_addr[];
+
+#define SDMA_FIRMWARE_MAGIC 0x414d4453
+
+/**
+ * struct sdma_firmware_header - Layout of the firmware image
+ *
+ * @magic		"SDMA"
+ * @version_major	increased whenever layout of struct sdma_script_start_addrs
+ *			changes.
+ * @version_minor	firmware minor version (for binary compatible changes)
+ * @script_addrs_start	offset of struct sdma_script_start_addrs in this image
+ * @num_script_addrs	Number of script addresses in this image
+ * @ram_code_start	offset of SDMA ram image in this firmware image
+ * @ram_code_size	size of SDMA ram image
+ */
+struct sdma_firmware_header {
+	u32	magic;
+	u32	version_major;
+	u32	version_minor;
+	u32	script_addrs_start;
+	u32	num_script_addrs;
+	u32	ram_code_start;
+	u32	ram_code_size;
+};
+
+struct sdma_engine {
+	struct device			*dev;
+	struct sdma_channel		channel[MAX_DMA_CHANNELS];
+	struct sdma_channel_control	*channel_control;
+	void __iomem			*regs;
+	unsigned int			version;
+	unsigned int			num_events;
+	struct sdma_context_data	*context;
+	dma_addr_t			context_phys;
+	struct dma_device		dma_device;
+	struct clk			*clk;
+};
+
+#define SDMA_H_CONFIG_DSPDMA	(1 << 12) /* indicates if the DSPDMA is used */
+#define SDMA_H_CONFIG_RTD_PINS	(1 << 11) /* indicates if Real-Time Debug pins are enabled */
+#define SDMA_H_CONFIG_ACR	(1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
+#define SDMA_H_CONFIG_CSM	(3)       /* indicates which context switch mode is selected*/
+
+static int sdma_config_ownership(struct sdma_channel *sdmac,
+		bool event_override, bool mcu_verride, bool dsp_override)
+{

+	struct sdma_engine *sdma = sdmac->sdma;
+	int channel = sdmac->channel;
+	u32 evt, mcu, dsp;
+
+	if (event_override && mcu_verride && dsp_override)
+		return -EINVAL;
+
+	evt = readl(SDMA_H_EVTOVR);
+	mcu = readl(SDMA_H_HOSTOVR);
+	dsp = readl(SDMA_H_DSPOVR);

Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
+     evt = readl(SDMA_H_EVTOVR);
+     mcu = readl(SDMA_H_HOSTOVR);
+     dsp = readl(SDMA_H_DSPOVR);

+     evt = readl(SDMA_H_EVTOVR);
+     mcu = readl(SDMA_H_HOSTOVR);
+     dsp = readl(SDMA_H_DSPOVR);

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
+     evt = readl(SDMA_H_EVTOVR);
+     mcu = readl(SDMA_H_HOSTOVR);
+     dsp = readl(SDMA_H_DSPOVR);

+     evt = readl(SDMA_H_EVTOVR);
+     mcu = readl(SDMA_H_HOSTOVR);
+     dsp = readl(SDMA_H_DSPOVR);

Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
+{
+	int ret;
+	const struct firmware *fw;
+	const struct sdma_firmware_header *header;
+	const struct sdma_script_start_addrs *addr;
+	int irq;
+	unsigned short *ram_code;
+	struct resource *iores;
+	struct sdma_platform_data *pdata = pdev->dev.platform_data;
+	char *fwname;
+	int i;
+	dma_cap_mask_t mask;
+	struct sdma_engine *sdma;
+
+	sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
+	if (!sdma)
+		return -ENOMEM;
+
+	sdma->dev = &pdev->dev;
+
+	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+	if (!iores || irq < 0 || !pdata) {

+		ret = -EINVAL;
+		goto err_irq;
+	}
+
+	sdma->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(sdma->clk)) {
+		ret = PTR_ERR(sdma->clk);
+		goto err_clk;
+	}
+

+	sdma->regs = ioremap(iores->start, resource_size(iores));
+	if (!sdma->regs) {
+		ret = -ENOMEM;
+		goto err_ioremap;
+	}
+
+
 
+static int __devexit sdma_remove(struct platform_device *pdev)

___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
 arch/arm/mach-imx/include/mach/dma-v1.h |    8 +-
 arch/arm/mach-mx3/Kconfig               |    2 +
 arch/arm/plat-mxc/Kconfig               |   10 +
 arch/arm/plat-mxc/include/mach/dma.h    |   64 ++
 arch/arm/plat-mxc/include/mach/sdma.h   |   17 +
 drivers/dma/Kconfig                     |    8 +
 drivers/dma/Makefile                    |    1 +
 drivers/dma/imx-sdma.c                  | 1392 +++++++++++++++++++++++++++++++
 8 files changed, 1496 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/dma.h
 create mode 100644 arch/arm/plat-mxc/include/mach/sdma.h
 create mode 100644 drivers/dma/imx-sdma.c
index 287431c..ac6fd71 100644
@@ -27,6 +27,8 @@
 
 #define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 
+#include <mach/dma.h>
+
 #define IMX_DMA_CHANNELS  16
 
 #define DMA_MODE_READ		0

@@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name);
 
 void imx_dma_free(int channel);
 
-enum imx_dma_prio {
-	DMA_PRIO_HIGH = 0,
-	DMA_PRIO_MEDIUM = 1,
-	DMA_PRIO_LOW = 2
-};
-
 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 
 #endif	/* __MACH_DMA_V1_H__ */

index 85beece..301375c 100644
@@ -3,12 +3,14 @@ if ARCH_MX3
 config ARCH_MX31
 	select ARCH_HAS_RNGA
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 	bool
 
 config ARCH_MX35
 	bool
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
+	select IMX_HAVE_SDMA
 
 comment "MX3 platforms:"
 

index 0527e65..6741625 100644
@@ -109,4 +109,14 @@ config ARCH_MXC_AUDMUX_V1
 config ARCH_MXC_AUDMUX_V2
 	bool
 
+config IMX_HAVE_SDMA
+	bool
+
+config IMX_SDMA
+	depends on IMX_HAVE_SDMA
+	tristate "Enable SDMA support"
+	help
+	  Include support for the SDMA engine. The SDMA engine needs additional
+	  firmware support. SDMA can be compiled as a module to support loading
+	  the firmware when a rootfs is present.
 endif

new file mode 100644
index 0000000..9be1122
@@ -0,0 +1,17 @@
+#ifndef __MACH_MXC_SDMA_H__
+#define __MACH_MXC_SDMA_H__
+
+/**
+ * struct sdma_platform_data - platform specific data for SDMA engine
+ *
+ * @sdma_version	The version of this SDMA engine
+ * @cpu_name		used to generate the firmware name
+ * @to_version		CPU Tape out version
+ */
+struct sdma_platform_data {
+	int sdma_version;
+	char *cpu_name;
+	int to_version;
+};
+
+#endif /* __MACH_MXC_SDMA_H__ */

index 9520cf0..ff68307 100644
@@ -195,6 +195,14 @@ config PCH_DMA
 	help
 	  Enable support for the Topcliff PCH DMA engine.
 
+config IMX_SDMA
+	tristate "i.MX SDMA support"
+	depends on ARCH_MXC
+	select DMA_ENGINE
+	help
+	  Support the i.MX SDMA engine. This engine is integrated into
+	  Freescale i.MX25/31/35/51 chips.
+
 config DMA_ENGINE
 	bool
 

index 72bd703..14d7a1b 100644
@@ -25,3 +25,4 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
 obj-$(CONFIG_PCH_DMA) += pch_dma.o
+obj-$(CONFIG_IMX_SDMA) += imx-sdma.o

1.7.1

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
+static int sdma_config_ownership(struct sdma_channel *sdmac,
+		bool event_override, bool mcu_verride, bool dsp_override)
+{
+	struct sdma_engine *sdma = sdmac->sdma;
+	int channel = sdmac->channel;
+	u32 evt, mcu, dsp;
+
+	if (event_override && mcu_verride && dsp_override)
+		return -EINVAL;
+
+	evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
+	mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
+	dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
+
+	if (dsp_override)
+		dsp &= ~(1 << channel);
+	else
+		dsp |= (1 << channel);
+
+	if (event_override)
+		evt &= ~(1 << channel);
+	else
+		evt |= (1 << channel);
+
+	if (mcu_verride)

+		mcu &= ~(1 << channel);
+	else
+		mcu |= (1 << channel);
+
+	__raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
+	__raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
+	__raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
+
+	return 0;
+}

+	struct sdma_engine *sdma = sdmac->sdma;
+	int channel = sdmac->channel;
+	u32 val;
+	u32 chnenbl = chnenbl_ofs(sdma, event);
+
+	val = __raw_readl(sdma->regs + chnenbl);
+	val |= (1 << channel);
+	__raw_writel(val, sdma->regs + chnenbl);
+}
