cxgb4 fixes / enhancements.

Here are 2 more fixes for 2.6.37. These two resolve all the known fastreg issues for T4.

Steve Wise (2):
RDMA/cxgb4: Fastreg NSMR fixes.
RDMA/cxgb4: Don't set completion flag for read requests.

 drivers/infiniband/hw/cxgb4/provider.c |    4 +-
 drivers/infiniband/hw/cxgb4/qp.c       |   54 +++++++++++++++-----------------
 drivers/infiniband/hw/cxgb4/t4.h       |    4 +-
 3 files changed, 30 insertions(+), 32 deletions(-)

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---

 drivers/infiniband/hw/cxgb4/qp.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

index 44ad386..7097ec4 100644
@@ -639,7 +639,7 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 			fw_opcode = FW_RI_RDMA_READ_WR;
 			swsqe->opcode = FW_RI_READ_REQ;
 			if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
-				fw_flags |= FW_RI_RDMA_READ_INVALIDATE;
+				fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 			else
 				fw_flags = 0;
 			err = build_rdma_read(wqe, wr, &len16);

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- Remove dsgl support - doesn't work in T4.

- Wrap the immediate PBL as needed when building it in the wr.

- Adjust max pbl depth allowed based on ulptx alignment requirements.

- Bump the slots per SQ to 5 to allow up to 128MB fast registers.

- Advertise fastreg support by default.

---

 drivers/infiniband/hw/cxgb4/provider.c |    4 +-
 drivers/infiniband/hw/cxgb4/qp.c       |   52 +++++++++++++++-----------------
 drivers/infiniband/hw/cxgb4/t4.h       |    4 +-
 3 files changed, 29 insertions(+), 31 deletions(-)

index a49a9c1..81e1277 100644
@@ -54,9 +54,9 @@
 
 #include "iw_cxgb4.h"
 
-static int fastreg_support;
+static int fastreg_support = 1;
 module_param(fastreg_support, int, 0644);
-MODULE_PARM_DESC(fastreg_support, "Advertise fastreg support (default=0)");
+MODULE_PARM_DESC(fastreg_support, "Advertise fastreg support (default=1)");
 
 static int c4iw_modify_port(struct ib_device *ibdev,
 			    u8 port, int port_modify_mask,

index 17ea5fc..7000442 100644
@@ -66,7 +66,7 @@ struct t4_status_page {
 
 #define T4_EQ_ENTRY_SIZE 64
 
-#define T4_SQ_NUM_SLOTS 4
+#define T4_SQ_NUM_SLOTS 5
 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
 			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))

@@ -79,7 +79,7 @@ struct t4_status_page {
 			sizeof(struct fw_ri_rdma_write_wr) - \
 			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
-			sizeof(struct fw_ri_immd)))
+			sizeof(struct fw_ri_immd)) & ~31UL)
 #define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
 
 #define T4_RQ_NUM_SLOTS 2

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thanks, applied both of these plus the other series of 11.
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