Skip to contentSkip to conversation

mfd: fix TWL4030 COR bit polarity for BCI SIH block

PATCH In review Grazvydas Ignotas 3 participants 3 messages Sep 28, 2010 – Oct 18, 2010

Subsystems (2)
lore
Share & tools
lore
#0 lore raw

PATCH 1/1 mfd: fix TWL4030 COR bit polarity for BCI SIH block

The chip TRM documentation contradicts itself about this bit, page 174 of swcu050e says bit should be 0 for clear-on-read behavior, while page 487 says it should be 1. Testing shows it should be 1, so set the .set_cor flag accordingly. This is needed for upcoming BCI charging driver to function.

---
 drivers/mfd/twl4030-irq.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
drivers/mfd/twl4030-irq.c +2 -1
index 097f24d..5b5a559 100644
@@ -144,6 +144,7 @@ static const struct sih sih_modules_twl4030[6] = {
 		.name		= "bci",
 		.module		= TWL4030_MODULE_INTERRUPTS,
 		.control_offset	= TWL4030_INTERRUPTS_BCISIHCTRL,
+		.set_cor	= true,
 		.bits		= 12,
 		.bytes_ixr	= 2,
 		.edr_offset	= TWL4030_INTERRUPTS_BCIEDR1,
@@ -408,7 +409,7 @@ static int twl4030_init_sih_modules(unsigned line)
 		 * set Clear-On-Read (COR) bit.
 		 *
 		 * NOTE that sometimes COR polarity is documented as being
-		 * inverted:  for MADC and BCI, COR=1 means "clear on write".
+		 * inverted:  for MADC, COR=1 means "clear on write".
 		 * And for PWR_INT it's not documented...
 		 */
 		if (sih->set_cor) {
Signature · 1 line
1.6.3.3
maintainer Acked-by on v1 1/1
#1 lore raw
Quoted 7 lines · Grazvydas Ignotas

The chip TRM documentation contradicts itself about this bit, page 174 of swcu050e says bit should be 0 for clear-on-read behavior, while page 487 says it should be 1. Testing shows it should be 1, so set the .set_cor flag accordingly. This is needed for upcoming BCI charging driver to function.

#2 lore raw
In reply to Grazvydas Ignotas

Hi Grazvydas,

Quoted 5 lines · Grazvydas Ignotas

The chip TRM documentation contradicts itself about this bit, page 174 of swcu050e says bit should be 0 for clear-on-read behavior, while page 487 says it should be 1. Testing shows it should be 1, so set the .set_cor flag accordingly. This is needed for upcoming BCI charging driver to function.

Patch applied, thanks.

Cheers,
Samuel.

Quoted 29 lines
---
 drivers/mfd/twl4030-irq.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
drivers/mfd/twl4030-irq.c +2 -1
index 097f24d..5b5a559 100644
@@ -144,6 +144,7 @@ static const struct sih sih_modules_twl4030[6] = {
 		.name		= "bci",
 		.module		= TWL4030_MODULE_INTERRUPTS,
 		.control_offset	= TWL4030_INTERRUPTS_BCISIHCTRL,
+		.set_cor	= true,
 		.bits		= 12,
 		.bytes_ixr	= 2,
 		.edr_offset	= TWL4030_INTERRUPTS_BCIEDR1,
@@ -408,7 +409,7 @@ static int twl4030_init_sih_modules(unsigned line)
 		 * set Clear-On-Read (COR) bit.
 		 *
 		 * NOTE that sometimes COR polarity is documented as being
-		 * inverted:  for MADC and BCI, COR=1 means "clear on write".
+		 * inverted:  for MADC, COR=1 means "clear on write".
 		 * And for PWR_INT it's not documented...
 		 */
 		if (sih->set_cor) {
Signature · 1 line
1.6.3.3
Signature · 2 lines
Intel Open Source Technology Centre
http://oss.intel.com/