Fix prm/cm accessor api's usage on OMAP4

RFC PATCH In review Rajendra Nayak 5 participants 10 messages Aug 10, 2010 – Oct 18, 2010

Subsystems (4)

Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP powerdomain SoC adaptation layer support

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Rajendra Nayak

author

2010-08-10 15:03 UTC #0 lore raw

cover Fix prm/cm accessor api's usage on OMAP4

Hi,

This RFC patch series fixes the prm and cm accessor api usage which is broken today on OMAP4.

OMAP's have always had PRCM split into PRM for power and reset management and CM for clock management.
In OMAP4 the split (physically) is not very straight forward and there are instances of clock management control registers in PRM and vice versa.
However it still makes sense, even on OMAP4 to logically split PRCM into PRM and CM for better understanding and to avoid adding additonal complexity in higher level frameworks which rely on the accessor api;s to do the low level register accesses.

Hence this patch series makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.

regards,
Rajendra

Rajendra Nayak (2):
OMAP4: PRCM: Add prcm_mpu_base to omap_globals
OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

 arch/arm/mach-omap2/cm.h                 |    4 +-
 arch/arm/mach-omap2/prcm-common.h        |   58 +++++++++++++++---------
 arch/arm/mach-omap2/prcm.c               |   73 ++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/prm.h                |    4 +-
 arch/arm/plat-omap/common.c              |    1 +
 arch/arm/plat-omap/include/plat/common.h |    1 +
 6 files changed, 112 insertions(+), 29 deletions(-)

Rajendra Nayak

author

2010-08-10 15:03 UTC #1 lore raw

RFC PATCH 1/2 OMAP4: PRCM: Add prcm_mpu_base to omap_globals

OMAP4 has a local PRCM (for individual CPU control) block. Hence add a new prcm_mpu_base to handle this in the omap_globals structure.

Signed-off-by Rajendra Nayak <[email protected]>

Cc Kevin Hilman <[email protected]>

Cc Paul Walmsley <[email protected]>

Cc Benoit Cousson <[email protected]>

---
 arch/arm/mach-omap2/prcm.c               |    5 +++++
 arch/arm/plat-omap/common.c              |    1 +
 arch/arm/plat-omap/include/plat/common.h |    1 +
 3 files changed, 7 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/prcm.c +5 -0

index c201374..4df30d0 100644
@@ -35,6 +35,7 @@
 #include "prm-regbits-24xx.h"
 
 static void __iomem *prm_base;
+static void __iomem *prcm_mpu_base;
 static void __iomem *cm_base;
 static void __iomem *cm2_base;

@@ -282,6 +283,10 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 		prm_base = ioremap(omap2_globals->prm, SZ_8K);
 		WARN_ON(!prm_base);
 	}
+	if (omap2_globals->prcm_mpu) {
+		prcm_mpu_base = ioremap(omap2_globals->prcm_mpu, SZ_8K);
+		WARN_ON(!prcm_mpu_base);
+	}
 	if (omap2_globals->cm) {
 		cm_base = ioremap(omap2_globals->cm, SZ_8K);
 		WARN_ON(!cm_base);

arch/arm/plat-omap/common.c +1 -0

index 3008e71..8603a46 100644
@@ -338,6 +338,7 @@ static struct omap_globals omap4_globals = {
 	.tap	= OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
 	.ctrl	= OMAP443X_CTRL_BASE,
 	.prm	= OMAP4430_PRM_BASE,
+	.prcm_mpu	= OMAP4430_PRCM_MPU_BASE,
 	.cm	= OMAP4430_CM_BASE,
 	.cm2	= OMAP4430_CM2_BASE,
 	.uart1_phys	= OMAP4_UART1_BASE,

arch/arm/plat-omap/include/plat/common.h +1 -0

index 9776b41..47baf9d 100644
@@ -48,6 +48,7 @@ struct omap_globals {
 	unsigned long   sms;            /* SDRAM Memory Scheduler */
 	unsigned long   ctrl;           /* System Control Module */
 	unsigned long   prm;            /* Power and Reset Management */
+	unsigned long   prcm_mpu;	/* Local MPU PRM */
 	unsigned long   cm;             /* Clock Management */
 	unsigned long   cm2;
 	unsigned long	uart1_phys;

Signature · 1 line

1.7.0.4

Rajendra Nayak

author

2010-08-10 15:03 UTC #2 lore raw

RFC PATCH 2/2 OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

Hence this patch makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.

To do this the submodule offsets within PRM/CM1 and CM2 have additonal info embedded in them specifying what base address to use while trying to access registers in the given submodule.

The 16 bit signed submodule offset is defined for OMAP4 as
<Bit 15> | <Bit 14:13> | <Bit 12:0>
<Sign bit> | <base identifier> | <submodule offset from base>

For older OMAP's the base identifier is always set to 0.

Signed-off-by Rajendra Nayak <[email protected]>

Cc Kevin Hilman <[email protected]>

Cc Paul Walmsley <[email protected]>

Cc Benoit Cousson <[email protected]>

---
 arch/arm/mach-omap2/cm.h          |    4 +-
 arch/arm/mach-omap2/prcm-common.h |   58 ++++++++++++++++++++-----------
 arch/arm/mach-omap2/prcm.c        |   68 ++++++++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/prm.h         |    4 +-
 4 files changed, 105 insertions(+), 29 deletions(-)

arch/arm/mach-omap2/cm.h +2 -2

index a02ca30..7b7ef09 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_CM_REGADDR(module, reg)				\
 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
 #define OMAP44XX_CM1_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + ((module) & (MOD_MASK)) + (reg))
 #define OMAP44XX_CM2_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + ((module) & (MOD_MASK)) + (reg))
 
 #include "cm44xx.h"

arch/arm/mach-omap2/prcm-common.h +37 ~~-21~~

85 lines not on this page · raw message

arch/arm/mach-omap2/prcm.c +64 -4

90 lines not on this page · raw message

arch/arm/mach-omap2/prm.h +2 -2

index 588873b..72456cc 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 #define OMAP44XX_PRM_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE +	((module) & (MOD_MASK)) + (reg))
 #define OMAP44XX_PRCM_MPU_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + ((module) & (MOD_MASK)) + (reg))
 
 #include "prm44xx.h"

Signature · 1 line

1.7.0.4

Kevin Hilman

2010-08-24 21:39 UTC #3 lore raw

Re: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

Quoted 23 lines · Rajendra Nayak

OMAP's have always had PRCM split into PRM for power and reset management and CM for clock management.
In OMAP4 the split (physically) is not very straight forward and there are instances of clock management control registers in PRM and vice versa.
However it still makes sense, even on OMAP4 to logically split PRCM into PRM and CM for better understanding and to avoid adding additonal complexity in higher level frameworks which rely on the accessor api;s to do the low level register accesses.
Hence this patch makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.
To do this the submodule offsets within PRM/CM1 and CM2 have additonal info embedded in them specifying what base address to use while trying to access registers in the given submodule.
The 16 bit signed submodule offset is defined for OMAP4 as
<Bit 15> | <Bit 14:13> | <Bit 12:0>
<Sign bit> | <base identifier> | <submodule offset from base>

Quoted 6 lines

For older OMAP's the base identifier is always set to 0.
Signed-off-by Rajendra Nayak <[email protected]>
Cc Kevin Hilman <[email protected]>
Cc Paul Walmsley <[email protected]>
Cc Benoit Cousson <[email protected]>

I'm OK with this approach, but I don't like the extra overhead added for every PRCM access on OMAP2/3.

What if you keep the original functions and add new functions for OMAP4, and use function pointers init'd at runtime (based on the existence of prcm_mpu_base)

Kevin

Quoted 227 lines

---
 arch/arm/mach-omap2/cm.h          |    4 +-
 arch/arm/mach-omap2/prcm-common.h |   58 ++++++++++++++++++++-----------
 arch/arm/mach-omap2/prcm.c        |   68 ++++++++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/prm.h         |    4 +-
 4 files changed, 105 insertions(+), 29 deletions(-)

arch/arm/mach-omap2/cm.h +2 -2

index a02ca30..7b7ef09 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_CM_REGADDR(module, reg)				\
 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
 #define OMAP44XX_CM1_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + ((module) & (MOD_MASK)) + (reg))
 #define OMAP44XX_CM2_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + ((module) & (MOD_MASK)) + (reg))
 
 #include "cm44xx.h"

arch/arm/mach-omap2/prcm-common.h +37 ~~-21~~

index 995b7ed..b93d33e 100644
@@ -57,10 +57,26 @@
 #define BITFIELD(l_bit, u_bit)	\
 	(BITS(u_bit) & ~((BITS(l_bit)) >> 1))
 
-/* OMAP44XX specific module offsets */
+/*
+ * OMAP44XX specific module offsets
+ * The 16 bit submodule offset is defined for OMAP4 as
+ * <Bit 15>	| <Bit 14:13> 		| <Bit 12:0>
+ * <Sign bit>	| <base identifier>	| <submodule offset from base>
+ */
 
-/* CM1 instances */
+#define DEFAULT_BASE	0x0
+#define PRM_BASE	0x1
+#define PRCM_MPU_BASE	0x2
+#define CM2_BASE	0x3
 
+#define BASE_ID_SHIFT	13
+#define MOD_MASK	((1 << BASE_ID_SHIFT)-1)
+
+#define PRM_BASE_ID		(PRM_BASE << BASE_ID_SHIFT)
+#define PRCM_MPU_BASE_ID	(PRCM_MPU_BASE << BASE_ID_SHIFT)
+#define CM2_BASE_ID		(CM2_BASE << BASE_ID_SHIFT)
+
+/* CM1 instances */
 #define OMAP4430_CM1_OCP_SOCKET_MOD	0x0000
 #define OMAP4430_CM1_CKGEN_MOD		0x0100
 #define OMAP4430_CM1_MPU_MOD		0x0300

@@ -71,19 +87,19 @@
 
 /* CM2 instances */
 
-#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000
-#define OMAP4430_CM2_CKGEN_MOD		0x0100
-#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600
-#define OMAP4430_CM2_CORE_MOD		0x0700
-#define OMAP4430_CM2_IVAHD_MOD		0x0f00
-#define OMAP4430_CM2_CAM_MOD		0x1000
-#define OMAP4430_CM2_DSS_MOD		0x1100
-#define OMAP4430_CM2_GFX_MOD		0x1200
-#define OMAP4430_CM2_L3INIT_MOD		0x1300
-#define OMAP4430_CM2_L4PER_MOD		0x1400
-#define OMAP4430_CM2_CEFUSE_MOD		0x1600
-#define OMAP4430_CM2_RESTORE_MOD	0x1e00
-#define OMAP4430_CM2_INSTR_MOD		0x1f00
+#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000 | CM2_BASE_ID
+#define OMAP4430_CM2_CKGEN_MOD		0x0100 | CM2_BASE_ID
+#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600 | CM2_BASE_ID
+#define OMAP4430_CM2_CORE_MOD		0x0700 | CM2_BASE_ID
+#define OMAP4430_CM2_IVAHD_MOD		0x0f00 | CM2_BASE_ID
+#define OMAP4430_CM2_CAM_MOD		0x1000 | CM2_BASE_ID
+#define OMAP4430_CM2_DSS_MOD		0x1100 | CM2_BASE_ID
+#define OMAP4430_CM2_GFX_MOD		0x1200 | CM2_BASE_ID
+#define OMAP4430_CM2_L3INIT_MOD		0x1300 | CM2_BASE_ID
+#define OMAP4430_CM2_L4PER_MOD		0x1400 | CM2_BASE_ID
+#define OMAP4430_CM2_CEFUSE_MOD		0x1600 | CM2_BASE_ID
+#define OMAP4430_CM2_RESTORE_MOD	0x1e00 | CM2_BASE_ID
+#define OMAP4430_CM2_INSTR_MOD		0x1f00 | CM2_BASE_ID
 
 /* PRM instances */

@@ -102,9 +118,9 @@
 #define OMAP4430_PRM_L4PER_MOD		0x1400
 #define OMAP4430_PRM_CEFUSE_MOD		0x1600
 #define OMAP4430_PRM_WKUP_MOD		0x1700
-#define OMAP4430_PRM_WKUP_CM_MOD	0x1800
+#define OMAP4430_PRM_WKUP_CM_MOD	0x1800 | PRM_BASE_ID
 #define OMAP4430_PRM_EMU_MOD		0x1900
-#define OMAP4430_PRM_EMU_CM_MOD		0x1a00
+#define OMAP4430_PRM_EMU_CM_MOD		0x1a00 | PRM_BASE_ID
 #define OMAP4430_PRM_DEVICE_MOD		0x1b00
 #define OMAP4430_PRM_INSTR_MOD		0x1f00

@@ -114,10 +130,10 @@
 
 /* PRCM_MPU instances */
 
-#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000
-#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200
-#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400
-#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800 | PRCM_MPU_BASE_ID
 
 
 /* 24XX register bits shared between CM & PRM registers */

arch/arm/mach-omap2/prcm.c +64 -4

index 4df30d0..124e866 100644
@@ -182,13 +182,40 @@ static inline void __omap_prcm_write(u32 value, void __iomem *base,
 /* Read a register in a PRM module */
 u32 prm_read_mod_reg(s16 module, u16 idx)
 {
-	return __omap_prcm_read(prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		return __omap_prcm_read(prcm_mpu_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	default:
+		pr_err("Unknown PRM submodule base\n");
+	}
+	return 0;
 }
 
 /* Write into a register in a PRM module */
 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-	__omap_prcm_write(val, prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		__omap_prcm_write(val, prcm_mpu_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown PRM submodule base\n");
+		break;
+	}
 }
 
 /* Read-modify-write a register in a PRM module. Caller must lock */

@@ -219,13 +246,46 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
-	return __omap_prcm_read(cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	case CM2_BASE:
+		return __omap_prcm_read(cm2_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(cm_base, module, idx);
+	default:
+		pr_err("Unknown CM submodule base\n");
+	}
+	return 0;
 }
 
 /* Write into a register in a CM module */
 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-	__omap_prcm_write(val, cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	case CM2_BASE:
+		__omap_prcm_write(val, cm2_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, cm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown CM submodule base\n");
+		break;
+	}
 }
 
 /* Read-modify-write a register in a CM module. Caller must lock */

arch/arm/mach-omap2/prm.h +2 -2

index 588873b..72456cc 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 #define OMAP44XX_PRM_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE +	((module) & (MOD_MASK)) + (reg))
 #define OMAP44XX_PRCM_MPU_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + ((module) & (MOD_MASK)) + (reg))
 
 #include "prm44xx.h"

Nayak, Rajendra

author

2010-08-25 08:56 UTC #4 lore raw

RE: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

Quoted 42 lines

-----Original Message-----
From: Kevin Hilman [mailto:[email protected]]
Sent: Wednesday, August 25, 2010 3:10 AM
To: Nayak, Rajendra
Cc: [email protected]; [email protected]; Cousson, Benoit
Subject: Re: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4
Quoted 23 lines · Rajendra Nayak
OMAP's have always had PRCM split into PRM for power and reset management and CM for clock management.
In OMAP4 the split (physically) is not very straight forward and there are instances of clock management control registers in PRM and vice versa.
However it still makes sense, even on OMAP4 to logically split PRCM into PRM and CM for better understanding and to avoid adding additonal complexity in higher level frameworks which rely on the accessor api;s to do the low level register accesses.
Hence this patch makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.
To do this the submodule offsets within PRM/CM1 and CM2 have additonal info embedded in them specifying what base address to use while trying to access registers in the given submodule.
The 16 bit signed submodule offset is defined for OMAP4 as
<Bit 15> | <Bit 14:13> | <Bit 12:0>
<Sign bit> | <base identifier> | <submodule offset from base>
Quoted 6 lines
For older OMAP's the base identifier is always set to 0.
Signed-off-by Rajendra Nayak <[email protected]>
Cc Kevin Hilman <[email protected]>
Cc Paul Walmsley <[email protected]>
Cc Benoit Cousson <[email protected]>

Quoted 6 lines

I'm OK with this approach, but I don't like the extra overhead added for every PRCM access on OMAP2/3.
What if you keep the original functions and add new functions for OMAP4, and use function pointers init'd at runtime (based on the existence of prcm_mpu_base)

Hi Kevin,

I actually have a series to split the powerdomain f/w into platform specific and platform independent functions. With that I should be able to get rid of this single function (for prm) for omap2/3 and omap4 and have separate functions. I can do a similar split for clockdomain framework and do the same for the cm functions. I will post the powerdomain split patches soon for review. Do you think it still makes sense to have this function pointer approach in the interim?
Regards,
Rajendra

Quoted 248 lines

Kevin

Quoted 3 lines

---
 arch/arm/mach-omap2/cm.h          |    4 +-
 arch/arm/mach-omap2/prcm-common.h |   58 ++++++++++++++++++++----

-------

Quoted 1 line

 arch/arm/mach-omap2/prcm.c        |   68

++++++++++++++++++++++++++++++++++--

arch/arm/mach-omap2/cm.h line 24

Quoted 10 lines

 arch/arm/mach-omap2/prm.h         |    4 +-
 4 files changed, 105 insertions(+), 29 deletions(-)

arch/arm/mach-omap2/cm.h +0 -0

index a02ca30..7b7ef09 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_CM_REGADDR(module, reg)				\
 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) +

(reg))

arch/arm/mach-omap2/cm.h line 26

Quoted 2 lines

arch/arm/mach-omap2/cm.h +0 -1

 #define OMAP44XX_CM1_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) +

(reg))

arch/arm/mach-omap2/cm.h line 26

Quoted 1 line

arch/arm/mach-omap2/cm.h +1 -0
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + ((module) &

(MOD_MASK)) + (reg))

arch/arm/mach-omap2/cm.h line 28

Quoted 2 lines

arch/arm/mach-omap2/cm.h +0 -1

 #define OMAP44XX_CM2_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) +

(reg))

arch/arm/mach-omap2/cm.h line 28

Quoted 1 line

arch/arm/mach-omap2/cm.h +1 -0
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + ((module) &

(MOD_MASK)) + (reg))

arch/arm/mach-omap2/prcm-

Quoted 4 lines

arch/arm/mach-omap2/cm.h +0 -0
 #include "cm44xx.h"
 
arch/arm/mach-omap2/prcm- renamed from arch/arm/mach-omap2/prcm-common.h +0 -0

common.h

Quoted 78 lines

index 995b7ed..b93d33e 100644

arch/arm/mach-omap2/prcm-common.h +33 ~~-17~~

@@ -57,10 +57,26 @@
 #define BITFIELD(l_bit, u_bit)	\
 	(BITS(u_bit) & ~((BITS(l_bit)) >> 1))
 
-/* OMAP44XX specific module offsets */
+/*
+ * OMAP44XX specific module offsets
+ * The 16 bit submodule offset is defined for OMAP4 as
+ * <Bit 15>	| <Bit 14:13> 		| <Bit 12:0>
+ * <Sign bit>	| <base identifier>	| <submodule offset from base>
+ */
 
-/* CM1 instances */
+#define DEFAULT_BASE	0x0
+#define PRM_BASE	0x1
+#define PRCM_MPU_BASE	0x2
+#define CM2_BASE	0x3
 
+#define BASE_ID_SHIFT	13
+#define MOD_MASK	((1 << BASE_ID_SHIFT)-1)
+
+#define PRM_BASE_ID		(PRM_BASE << BASE_ID_SHIFT)
+#define PRCM_MPU_BASE_ID	(PRCM_MPU_BASE << BASE_ID_SHIFT)
+#define CM2_BASE_ID		(CM2_BASE << BASE_ID_SHIFT)
+
+/* CM1 instances */
 #define OMAP4430_CM1_OCP_SOCKET_MOD	0x0000
 #define OMAP4430_CM1_CKGEN_MOD		0x0100
 #define OMAP4430_CM1_MPU_MOD		0x0300

@@ -71,19 +87,19 @@
 
 /* CM2 instances */
 
-#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000
-#define OMAP4430_CM2_CKGEN_MOD		0x0100
-#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600
-#define OMAP4430_CM2_CORE_MOD		0x0700
-#define OMAP4430_CM2_IVAHD_MOD		0x0f00
-#define OMAP4430_CM2_CAM_MOD		0x1000
-#define OMAP4430_CM2_DSS_MOD		0x1100
-#define OMAP4430_CM2_GFX_MOD		0x1200
-#define OMAP4430_CM2_L3INIT_MOD		0x1300
-#define OMAP4430_CM2_L4PER_MOD		0x1400
-#define OMAP4430_CM2_CEFUSE_MOD		0x1600
-#define OMAP4430_CM2_RESTORE_MOD	0x1e00
-#define OMAP4430_CM2_INSTR_MOD		0x1f00
+#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000 | CM2_BASE_ID
+#define OMAP4430_CM2_CKGEN_MOD		0x0100 | CM2_BASE_ID
+#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600 | CM2_BASE_ID
+#define OMAP4430_CM2_CORE_MOD		0x0700 | CM2_BASE_ID
+#define OMAP4430_CM2_IVAHD_MOD		0x0f00 | CM2_BASE_ID
+#define OMAP4430_CM2_CAM_MOD		0x1000 | CM2_BASE_ID
+#define OMAP4430_CM2_DSS_MOD		0x1100 | CM2_BASE_ID
+#define OMAP4430_CM2_GFX_MOD		0x1200 | CM2_BASE_ID
+#define OMAP4430_CM2_L3INIT_MOD		0x1300 | CM2_BASE_ID
+#define OMAP4430_CM2_L4PER_MOD		0x1400 | CM2_BASE_ID
+#define OMAP4430_CM2_CEFUSE_MOD		0x1600 | CM2_BASE_ID
+#define OMAP4430_CM2_RESTORE_MOD	0x1e00 | CM2_BASE_ID
+#define OMAP4430_CM2_INSTR_MOD		0x1f00 | CM2_BASE_ID
 
 /* PRM instances */

@@ -102,9 +118,9 @@
 #define OMAP4430_PRM_L4PER_MOD		0x1400
 #define OMAP4430_PRM_CEFUSE_MOD		0x1600
 #define OMAP4430_PRM_WKUP_MOD		0x1700
-#define OMAP4430_PRM_WKUP_CM_MOD	0x1800
+#define OMAP4430_PRM_WKUP_CM_MOD	0x1800 | PRM_BASE_ID
 #define OMAP4430_PRM_EMU_MOD		0x1900
-#define OMAP4430_PRM_EMU_CM_MOD		0x1a00
+#define OMAP4430_PRM_EMU_CM_MOD		0x1a00 | PRM_BASE_ID
 #define OMAP4430_PRM_DEVICE_MOD		0x1b00
 #define OMAP4430_PRM_INSTR_MOD		0x1f00

arch/arm/mach-omap2/prcm-common.h line 133

Quoted 8 lines

arch/arm/mach-omap2/prcm-common.h +1 -4

@@ -114,10 +130,10 @@
 
 /* PRCM_MPU instances */
 
-#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000
-#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200
-#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400
-#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000 |

PRCM_MPU_BASE_ID

arch/arm/mach-omap2/prcm-common.h line 134

Quoted 1 line

arch/arm/mach-omap2/prcm-common.h +1 -0
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200 |

PRCM_MPU_BASE_ID

arch/arm/mach-omap2/prcm-common.h line 135

Quoted 1 line

arch/arm/mach-omap2/prcm-common.h +1 -0
+#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400 |

PRCM_MPU_BASE_ID

arch/arm/mach-omap2/prcm-common.h line 136

Quoted 1 line

arch/arm/mach-omap2/prcm-common.h +1 -0
+#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800 |

PRCM_MPU_BASE_ID

arch/arm/mach-omap2/prcm.c static inline void __omap_prcm_write(u32 value, void

Quoted 8 lines

arch/arm/mach-omap2/prcm-common.h +0 -0

 /* 24XX register bits shared between CM & PRM registers */

arch/arm/mach-omap2/prcm.c +0 -0

index 4df30d0..124e866 100644
@@ -182,13 +182,40 @@ static inline void __omap_prcm_write(u32 value, void

__iomem *base,

arch/arm/mach-omap2/prcm.c u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32

Quoted 43 lines

arch/arm/mach-omap2/prcm.c +29 -2

 /* Read a register in a PRM module */
 u32 prm_read_mod_reg(s16 module, u16 idx)
 {
-	return __omap_prcm_read(prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		return __omap_prcm_read(prcm_mpu_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	default:
+		pr_err("Unknown PRM submodule base\n");
+	}
+	return 0;
 }
 
 /* Write into a register in a PRM module */
 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-	__omap_prcm_write(val, prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		__omap_prcm_write(val, prcm_mpu_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown PRM submodule base\n");
+		break;
+	}
 }
 
 /* Read-modify-write a register in a PRM module. Caller must lock */

@@ -219,13 +246,46 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32

mask)

Quoted 53 lines

arch/arm/mach-omap2/prcm.c +35 -2

 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
-	return __omap_prcm_read(cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	case CM2_BASE:
+		return __omap_prcm_read(cm2_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(cm_base, module, idx);
+	default:
+		pr_err("Unknown CM submodule base\n");
+	}
+	return 0;
 }
 
 /* Write into a register in a CM module */
 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-	__omap_prcm_write(val, cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	case CM2_BASE:
+		__omap_prcm_write(val, cm2_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, cm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown CM submodule base\n");
+		break;
+	}
 }
 
 /* Read-modify-write a register in a CM module. Caller must lock */

arch/arm/mach-omap2/prm.h +0 -0

index 588873b..72456cc 100644

arch/arm/mach-omap2/prm.h line 26

Quoted 5 lines

arch/arm/mach-omap2/prm.h +1 -1

@@ -23,9 +23,9 @@
 #define OMAP34XX_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 #define OMAP44XX_PRM_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE +	((module) &

(MOD_MASK)) + (reg))

arch/arm/mach-omap2/prm.h line 28

Quoted 2 lines

arch/arm/mach-omap2/prm.h +0 -1

 #define OMAP44XX_PRCM_MPU_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) +

(reg))

arch/arm/mach-omap2/prm.h line 28

Quoted 1 line

arch/arm/mach-omap2/prm.h +1 -0
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + ((module) &

(MOD_MASK)) + (reg))

Quoted 2 lines

arch/arm/mach-omap2/prm.h +0 -0
 #include "prm44xx.h"

Kevin Hilman

2010-08-25 18:16 UTC #5 lore raw

Re: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

Quoted 47 lines · Rajendra

Quoted 40 lines
-----Original Message-----
From: Kevin Hilman [mailto:[email protected]]
Sent: Wednesday, August 25, 2010 3:10 AM
To: Nayak, Rajendra
Cc: [email protected]; [email protected]; Cousson, Benoit
Subject: Re: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4
Quoted 23 lines · Rajendra Nayak
OMAP's have always had PRCM split into PRM for power and reset management and CM for clock management.
In OMAP4 the split (physically) is not very straight forward and there are instances of clock management control registers in PRM and vice versa.
However it still makes sense, even on OMAP4 to logically split PRCM into PRM and CM for better understanding and to avoid adding additonal complexity in higher level frameworks which rely on the accessor api;s to do the low level register accesses.
Hence this patch makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.
To do this the submodule offsets within PRM/CM1 and CM2 have additonal info embedded in them specifying what base address to use while trying to access registers in the given submodule.
The 16 bit signed submodule offset is defined for OMAP4 as
<Bit 15> | <Bit 14:13> | <Bit 12:0>
<Sign bit> | <base identifier> | <submodule offset from base>
Quoted 6 lines
For older OMAP's the base identifier is always set to 0.
Signed-off-by Rajendra Nayak <[email protected]>
Cc Kevin Hilman <[email protected]>
Cc Paul Walmsley <[email protected]>
Cc Benoit Cousson <[email protected]>
Quoted 6 lines
I'm OK with this approach, but I don't like the extra overhead added for every PRCM access on OMAP2/3.
What if you keep the original functions and add new functions for OMAP4, and use function pointers init'd at runtime (based on the existence of prcm_mpu_base)

Quoted 6 lines

I actually have a series to split the powerdomain f/w into platform specific and platform independent functions. With that I should be able to get rid of this single function (for prm) for omap2/3 and omap4 and have separate functions. I can do a similar split for clockdomain framework and do the same for the cm functions. I will post the powerdomain split patches soon for review.

OK.

Quoted 1 line

Do you think it still makes sense to have this function pointer approach in the interim?

No, it sounds like your split-up approach is better all around.

Kevin

Nayak, Rajendra

author

2010-09-23 14:15 UTC #6 lore raw

RE: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

In reply to Rajendra Nayak

Quoted 30 lines

-----Original Message-----
From: [email protected] [mailto:linux-omap- [email protected]] On Behalf Of Nayak, Rajendra
Sent: Tuesday, August 10, 2010 8:33 PM
To: [email protected]
Cc: [email protected]; [email protected]; Cousson, Benoit; Nayak, Rajendra
Subject: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4
OMAP's have always had PRCM split into PRM for power and reset management and CM for clock management.
In OMAP4 the split (physically) is not very straight forward and there are instances of clock management control registers in PRM and vice versa.
However it still makes sense, even on OMAP4 to logically split PRCM into PRM and CM for better understanding and to avoid adding additonal complexity in higher level frameworks which rely on the accessor api;s to do the low level register accesses.
Hence this patch makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.
To do this the submodule offsets within PRM/CM1 and CM2 have additonal info embedded in them specifying what base address to use while trying to access registers in the given submodule.

Quoted 5 lines

The 16 bit signed submodule offset is defined for OMAP4 as
<Bit 15> | <Bit 14:13> | <Bit 12:0>
<Sign bit> | <base identifier> | <submodule offset from base>
For older OMAP's the base identifier is always set to 0.

Hi Paul,

Any thoughts on this patch/approach?

Regards,
Rajendra

Quoted 257 lines

Signed-off-by Rajendra Nayak <[email protected]>

Cc Kevin Hilman <[email protected]>

Cc Paul Walmsley <[email protected]>

Cc Benoit Cousson <[email protected]>

---
 arch/arm/mach-omap2/cm.h          |    4 +-
 arch/arm/mach-omap2/prcm-common.h |   58 ++++++++++++++++++++------
-----
 arch/arm/mach-omap2/prcm.c        |   68
++++++++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/prm.h         |    4 +-
 4 files changed, 105 insertions(+), 29 deletions(-)

arch/arm/mach-omap2/cm.h +1 -2

index a02ca30..7b7ef09 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_CM_REGADDR(module, reg)				\
 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) +
 (reg))
 #define OMAP44XX_CM1_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) +
 (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + ((module) &
 (MOD_MASK)) + (reg))
 #define OMAP44XX_CM2_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) +

(reg))

arch/arm/mach-omap2/cm.h +1 -0

+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + ((module) &

(MOD_MASK)) + (reg))

#include "cm44xx.h"

arch/arm/mach-omap2/prcm- renamed from arch/arm/mach-omap2/prcm-common.h +0 -0

common.h
index 995b7ed..b93d33e 100644

arch/arm/mach-omap2/prcm-common.h +34 ~~-21~~

@@ -57,10 +57,26 @@
 #define BITFIELD(l_bit, u_bit)	\
 	(BITS(u_bit) & ~((BITS(l_bit)) >> 1))
 
-/* OMAP44XX specific module offsets */
+/*
+ * OMAP44XX specific module offsets
+ * The 16 bit submodule offset is defined for OMAP4 as
+ * <Bit 15>	| <Bit 14:13> 		| <Bit 12:0>
+ * <Sign bit>	| <base identifier>	| <submodule offset from base>
+ */
 
-/* CM1 instances */
+#define DEFAULT_BASE	0x0
+#define PRM_BASE	0x1
+#define PRCM_MPU_BASE	0x2
+#define CM2_BASE	0x3
 
+#define BASE_ID_SHIFT	13
+#define MOD_MASK	((1 << BASE_ID_SHIFT)-1)
+
+#define PRM_BASE_ID		(PRM_BASE << BASE_ID_SHIFT)
+#define PRCM_MPU_BASE_ID	(PRCM_MPU_BASE << BASE_ID_SHIFT)
+#define CM2_BASE_ID		(CM2_BASE << BASE_ID_SHIFT)
+
+/* CM1 instances */
 #define OMAP4430_CM1_OCP_SOCKET_MOD	0x0000
 #define OMAP4430_CM1_CKGEN_MOD		0x0100
 #define OMAP4430_CM1_MPU_MOD		0x0300

@@ -71,19 +87,19 @@
 
 /* CM2 instances */
 
-#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000
-#define OMAP4430_CM2_CKGEN_MOD		0x0100
-#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600
-#define OMAP4430_CM2_CORE_MOD		0x0700
-#define OMAP4430_CM2_IVAHD_MOD		0x0f00
-#define OMAP4430_CM2_CAM_MOD		0x1000
-#define OMAP4430_CM2_DSS_MOD		0x1100
-#define OMAP4430_CM2_GFX_MOD		0x1200
-#define OMAP4430_CM2_L3INIT_MOD		0x1300
-#define OMAP4430_CM2_L4PER_MOD		0x1400
-#define OMAP4430_CM2_CEFUSE_MOD		0x1600
-#define OMAP4430_CM2_RESTORE_MOD	0x1e00
-#define OMAP4430_CM2_INSTR_MOD		0x1f00
+#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000 | CM2_BASE_ID
+#define OMAP4430_CM2_CKGEN_MOD		0x0100 | CM2_BASE_ID
+#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600 | CM2_BASE_ID
+#define OMAP4430_CM2_CORE_MOD		0x0700 | CM2_BASE_ID
+#define OMAP4430_CM2_IVAHD_MOD		0x0f00 | CM2_BASE_ID
+#define OMAP4430_CM2_CAM_MOD		0x1000 | CM2_BASE_ID
+#define OMAP4430_CM2_DSS_MOD		0x1100 | CM2_BASE_ID
+#define OMAP4430_CM2_GFX_MOD		0x1200 | CM2_BASE_ID
+#define OMAP4430_CM2_L3INIT_MOD		0x1300 | CM2_BASE_ID
+#define OMAP4430_CM2_L4PER_MOD		0x1400 | CM2_BASE_ID
+#define OMAP4430_CM2_CEFUSE_MOD		0x1600 | CM2_BASE_ID
+#define OMAP4430_CM2_RESTORE_MOD	0x1e00 | CM2_BASE_ID
+#define OMAP4430_CM2_INSTR_MOD		0x1f00 | CM2_BASE_ID
 
 /* PRM instances */

@@ -102,9 +118,9 @@
 #define OMAP4430_PRM_L4PER_MOD		0x1400
 #define OMAP4430_PRM_CEFUSE_MOD		0x1600
 #define OMAP4430_PRM_WKUP_MOD		0x1700
-#define OMAP4430_PRM_WKUP_CM_MOD	0x1800
+#define OMAP4430_PRM_WKUP_CM_MOD	0x1800 | PRM_BASE_ID
 #define OMAP4430_PRM_EMU_MOD		0x1900
-#define OMAP4430_PRM_EMU_CM_MOD		0x1a00
+#define OMAP4430_PRM_EMU_CM_MOD		0x1a00 | PRM_BASE_ID
 #define OMAP4430_PRM_DEVICE_MOD		0x1b00
 #define OMAP4430_PRM_INSTR_MOD		0x1f00

@@ -114,10 +130,10 @@
 
 /* PRCM_MPU instances */
 
-#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000
-#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200
-#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400
-#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000 |

PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200 |
PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400 |
PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800 |
PRCM_MPU_BASE_ID

/* 24XX register bits shared between CM & PRM registers */

arch/arm/mach-omap2/prcm.c +29 -2

index 4df30d0..124e866 100644
@@ -182,13 +182,40 @@ static inline void __omap_prcm_write(u32 value, void
 __iomem *base,
 /* Read a register in a PRM module */
 u32 prm_read_mod_reg(s16 module, u16 idx)
 {
-	return __omap_prcm_read(prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		return __omap_prcm_read(prcm_mpu_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	default:
+		pr_err("Unknown PRM submodule base\n");
+	}
+	return 0;
 }
 
 /* Write into a register in a PRM module */
 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-	__omap_prcm_write(val, prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		__omap_prcm_write(val, prcm_mpu_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown PRM submodule base\n");
+		break;
+	}
 }

/* Read-modify-write a register in a PRM module. Caller must lock */

arch/arm/mach-omap2/prcm.c +35 -2

@@ -219,13 +246,46 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32
 mask)
 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
-	return __omap_prcm_read(cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	case CM2_BASE:
+		return __omap_prcm_read(cm2_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(cm_base, module, idx);
+	default:
+		pr_err("Unknown CM submodule base\n");
+	}
+	return 0;
 }
 
 /* Write into a register in a CM module */
 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-	__omap_prcm_write(val, cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	case CM2_BASE:
+		__omap_prcm_write(val, cm2_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, cm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown CM submodule base\n");
+		break;
+	}
 }

/* Read-modify-write a register in a CM module. Caller must lock */

arch/arm/mach-omap2/prm.h +2 -2

index 588873b..72456cc 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 #define OMAP44XX_PRM_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE +	((module) &
 (MOD_MASK)) + (reg))
 #define OMAP44XX_PRCM_MPU_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) +
 (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + ((module) &
 (MOD_MASK)) + (reg))

#include "prm44xx.h"

--
1.7.0.4

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Paul Walmsley

maintainer

2010-10-14 18:44 UTC #7 lore raw

Re: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

In reply to Rajendra Nayak

Hello Rajendra,

Quoted 15 lines · Rajendra Nayak

OMAP's have always had PRCM split into PRM for power and reset management and CM for clock management.
In OMAP4 the split (physically) is not very straight forward and there are instances of clock management control registers in PRM and vice versa.
However it still makes sense, even on OMAP4 to logically split PRCM into PRM and CM for better understanding and to avoid adding additonal complexity in higher level frameworks which rely on the accessor api;s to do the low level register accesses.
Hence this patch makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.

Quoted 7 lines

To do this the submodule offsets within PRM/CM1 and CM2 have additonal info embedded in them specifying what base address to use while trying to access registers in the given submodule.
The 16 bit signed submodule offset is defined for OMAP4 as
<Bit 15> | <Bit 14:13> | <Bit 12:0>
<Sign bit> | <base identifier> | <submodule offset from base>

The concern that I have with embedding multiple parameters into a single parameter is that it seems like a hack. Why not add an extra parameter for the base identifier, rather than packing it into an existing parameter?

I am not necessarily opposed to your patch as it exists. But I would like to hear your opinions first on separating out the base identifier parameter as a separate function parameter, and then adding an extra field for it into any data structure that would need it. Could you write briefly if you see any significant advantages/disadvantages to that approach?

Quoted 242 lines

For older OMAP's the base identifier is always set to 0.

Signed-off-by Rajendra Nayak <[email protected]>

Cc Kevin Hilman <[email protected]>

Cc Paul Walmsley <[email protected]>

Cc Benoit Cousson <[email protected]>

---
 arch/arm/mach-omap2/cm.h          |    4 +-
 arch/arm/mach-omap2/prcm-common.h |   58 ++++++++++++++++++++-----------
 arch/arm/mach-omap2/prcm.c        |   68 ++++++++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/prm.h         |    4 +-
 4 files changed, 105 insertions(+), 29 deletions(-)

arch/arm/mach-omap2/cm.h +2 -2

index a02ca30..7b7ef09 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_CM_REGADDR(module, reg)				\
 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
 #define OMAP44XX_CM1_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + ((module) & (MOD_MASK)) + (reg))
 #define OMAP44XX_CM2_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + ((module) & (MOD_MASK)) + (reg))
 
 #include "cm44xx.h"

arch/arm/mach-omap2/prcm-common.h +37 ~~-21~~

index 995b7ed..b93d33e 100644
@@ -57,10 +57,26 @@
 #define BITFIELD(l_bit, u_bit)	\
 	(BITS(u_bit) & ~((BITS(l_bit)) >> 1))
 
-/* OMAP44XX specific module offsets */
+/*
+ * OMAP44XX specific module offsets
+ * The 16 bit submodule offset is defined for OMAP4 as
+ * <Bit 15>	| <Bit 14:13> 		| <Bit 12:0>
+ * <Sign bit>	| <base identifier>	| <submodule offset from base>
+ */
 
-/* CM1 instances */
+#define DEFAULT_BASE	0x0
+#define PRM_BASE	0x1
+#define PRCM_MPU_BASE	0x2
+#define CM2_BASE	0x3
 
+#define BASE_ID_SHIFT	13
+#define MOD_MASK	((1 << BASE_ID_SHIFT)-1)
+
+#define PRM_BASE_ID		(PRM_BASE << BASE_ID_SHIFT)
+#define PRCM_MPU_BASE_ID	(PRCM_MPU_BASE << BASE_ID_SHIFT)
+#define CM2_BASE_ID		(CM2_BASE << BASE_ID_SHIFT)
+
+/* CM1 instances */
 #define OMAP4430_CM1_OCP_SOCKET_MOD	0x0000
 #define OMAP4430_CM1_CKGEN_MOD		0x0100
 #define OMAP4430_CM1_MPU_MOD		0x0300

@@ -71,19 +87,19 @@
 
 /* CM2 instances */
 
-#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000
-#define OMAP4430_CM2_CKGEN_MOD		0x0100
-#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600
-#define OMAP4430_CM2_CORE_MOD		0x0700
-#define OMAP4430_CM2_IVAHD_MOD		0x0f00
-#define OMAP4430_CM2_CAM_MOD		0x1000
-#define OMAP4430_CM2_DSS_MOD		0x1100
-#define OMAP4430_CM2_GFX_MOD		0x1200
-#define OMAP4430_CM2_L3INIT_MOD		0x1300
-#define OMAP4430_CM2_L4PER_MOD		0x1400
-#define OMAP4430_CM2_CEFUSE_MOD		0x1600
-#define OMAP4430_CM2_RESTORE_MOD	0x1e00
-#define OMAP4430_CM2_INSTR_MOD		0x1f00
+#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000 | CM2_BASE_ID
+#define OMAP4430_CM2_CKGEN_MOD		0x0100 | CM2_BASE_ID
+#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600 | CM2_BASE_ID
+#define OMAP4430_CM2_CORE_MOD		0x0700 | CM2_BASE_ID
+#define OMAP4430_CM2_IVAHD_MOD		0x0f00 | CM2_BASE_ID
+#define OMAP4430_CM2_CAM_MOD		0x1000 | CM2_BASE_ID
+#define OMAP4430_CM2_DSS_MOD		0x1100 | CM2_BASE_ID
+#define OMAP4430_CM2_GFX_MOD		0x1200 | CM2_BASE_ID
+#define OMAP4430_CM2_L3INIT_MOD		0x1300 | CM2_BASE_ID
+#define OMAP4430_CM2_L4PER_MOD		0x1400 | CM2_BASE_ID
+#define OMAP4430_CM2_CEFUSE_MOD		0x1600 | CM2_BASE_ID
+#define OMAP4430_CM2_RESTORE_MOD	0x1e00 | CM2_BASE_ID
+#define OMAP4430_CM2_INSTR_MOD		0x1f00 | CM2_BASE_ID
 
 /* PRM instances */

@@ -102,9 +118,9 @@
 #define OMAP4430_PRM_L4PER_MOD		0x1400
 #define OMAP4430_PRM_CEFUSE_MOD		0x1600
 #define OMAP4430_PRM_WKUP_MOD		0x1700
-#define OMAP4430_PRM_WKUP_CM_MOD	0x1800
+#define OMAP4430_PRM_WKUP_CM_MOD	0x1800 | PRM_BASE_ID
 #define OMAP4430_PRM_EMU_MOD		0x1900
-#define OMAP4430_PRM_EMU_CM_MOD		0x1a00
+#define OMAP4430_PRM_EMU_CM_MOD		0x1a00 | PRM_BASE_ID
 #define OMAP4430_PRM_DEVICE_MOD		0x1b00
 #define OMAP4430_PRM_INSTR_MOD		0x1f00

@@ -114,10 +130,10 @@
 
 /* PRCM_MPU instances */
 
-#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000
-#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200
-#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400
-#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800 | PRCM_MPU_BASE_ID
 
 
 /* 24XX register bits shared between CM & PRM registers */

arch/arm/mach-omap2/prcm.c +64 -4

index 4df30d0..124e866 100644
@@ -182,13 +182,40 @@ static inline void __omap_prcm_write(u32 value, void __iomem *base,
 /* Read a register in a PRM module */
 u32 prm_read_mod_reg(s16 module, u16 idx)
 {
-	return __omap_prcm_read(prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		return __omap_prcm_read(prcm_mpu_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	default:
+		pr_err("Unknown PRM submodule base\n");
+	}
+	return 0;
 }
 
 /* Write into a register in a PRM module */
 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-	__omap_prcm_write(val, prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		__omap_prcm_write(val, prcm_mpu_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown PRM submodule base\n");
+		break;
+	}
 }
 
 /* Read-modify-write a register in a PRM module. Caller must lock */

@@ -219,13 +246,46 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
-	return __omap_prcm_read(cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	case CM2_BASE:
+		return __omap_prcm_read(cm2_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(cm_base, module, idx);
+	default:
+		pr_err("Unknown CM submodule base\n");
+	}
+	return 0;
 }
 
 /* Write into a register in a CM module */
 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-	__omap_prcm_write(val, cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module) >> BASE_ID_SHIFT;
+	module &= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	case CM2_BASE:
+		__omap_prcm_write(val, cm2_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, cm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown CM submodule base\n");
+		break;
+	}
 }
 
 /* Read-modify-write a register in a CM module. Caller must lock */

arch/arm/mach-omap2/prm.h +2 -2

index 588873b..72456cc 100644
@@ -23,9 +23,9 @@
 #define OMAP34XX_PRM_REGADDR(module, reg)				\
 		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
 #define OMAP44XX_PRM_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE +	((module) & (MOD_MASK)) + (reg))
 #define OMAP44XX_PRCM_MPU_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + ((module) & (MOD_MASK)) + (reg))
 
 #include "prm44xx.h"

Signature · 6 lines

1.7.0.4

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- Paul

Cousson, Benoit

2010-10-15 16:07 UTC #8 lore raw

Re: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

Hi Paul,

Quoted 23 lines · Paul Walmsley

Hello Rajendra,
Quoted 19 lines · Rajendra Nayak
OMAP's have always had PRCM split into PRM for power and reset management and CM for clock management.
In OMAP4 the split (physically) is not very straight forward and there are instances of clock management control registers in PRM and vice versa.
However it still makes sense, even on OMAP4 to logically split PRCM into PRM and CM for better understanding and to avoid adding additonal complexity in higher level frameworks which rely on the accessor api;s to do the low level register accesses.
Hence this patch makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.
To do this the submodule offsets within PRM/CM1 and CM2 have additonal info embedded in them specifying what base address to use while trying to access registers in the given submodule.

Quoted 8 lines

Quoted 3 lines
The 16 bit signed submodule offset is defined for OMAP4 as
<Bit 15> |<Bit 14:13> |<Bit 12:0>
<Sign bit> |<base identifier> |<submodule offset from base>
The concern that I have with embedding multiple parameters into a single parameter is that it seems like a hack. Why not add an extra parameter for the base identifier, rather than packing it into an existing parameter?

The primary constraint that lead us to that proposal was to minimize the impact on the existing code and API for previous OMAPs. That was clearly the goal #1.
The other one was the relative simplicity of the implementation.

The user of these OMAP4430_XXXX_MOD macros does not have to care if this is a real offset or just an id.

Quoted 6 lines

I am not necessarily opposed to your patch as it exists. But I would like to hear your opinions first on separating out the base identifier parameter as a separate function parameter, and then adding an extra field for it into any data structure that would need it. Could you write briefly if you see any significant advantages/disadvantages to that approach?

The disadvantage is the relative complexity for the caller of this API, that will have to know what partition should be used.
It is fine if the caller is the powerdomain or clockdomain fmwk, but what about all the other callers we have here and there?
When we looked at that in Bangalore, we realized that a bunch of code is using these prm/cm APIs. Maybe some cleanup can be done, like in the save / restore part, but we still have some user of that.

For the moment, I do not really see any advantage of such approach.
The partitioning is changing on every OMAPs, so we do have to abstract that. If it is not done at that level, we will have to define another API on top of that to do exactly the same job.

Regards,
Benoit

Quoted 246 lines

Quoted 238 lines

For older OMAP's the base identifier is always set to 0.

Signed-off-by Rajendra Nayak<[email protected]>

Cc Kevin Hilman<[email protected]>

Cc Paul Walmsley<[email protected]>

Cc Benoit Cousson<[email protected]>

---
  arch/arm/mach-omap2/cm.h          |    4 +-
  arch/arm/mach-omap2/prcm-common.h |   58 ++++++++++++++++++++-----------
  arch/arm/mach-omap2/prcm.c        |   68 ++++++++++++++++++++++++++++++++++--
  arch/arm/mach-omap2/prm.h         |    4 +-
  4 files changed, 105 insertions(+), 29 deletions(-)

arch/arm/mach-omap2/cm.h +2 -2

index a02ca30..7b7ef09 100644
@@ -23,9 +23,9 @@
  #define OMAP34XX_CM_REGADDR(module, reg)				\
  			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
  #define OMAP44XX_CM1_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + ((module)&  (MOD_MASK)) + (reg))
  #define OMAP44XX_CM2_REGADDR(module, reg)				\
-			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
+			OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + ((module)&  (MOD_MASK)) + (reg))
 
  #include "cm44xx.h"

arch/arm/mach-omap2/prcm-common.h +37 ~~-21~~

index 995b7ed..b93d33e 100644
@@ -57,10 +57,26 @@
  #define BITFIELD(l_bit, u_bit)	\
  	(BITS(u_bit)&  ~((BITS(l_bit))>>  1))
 
-/* OMAP44XX specific module offsets */
+/*
+ * OMAP44XX specific module offsets
+ * The 16 bit submodule offset is defined for OMAP4 as
+ *<Bit 15>	|<Bit 14:13>  		|<Bit 12:0>
+ *<Sign bit>	|<base identifier>	|<submodule offset from base>
+ */
 
-/* CM1 instances */
+#define DEFAULT_BASE	0x0
+#define PRM_BASE	0x1
+#define PRCM_MPU_BASE	0x2
+#define CM2_BASE	0x3
 
+#define BASE_ID_SHIFT	13
+#define MOD_MASK	((1<<  BASE_ID_SHIFT)-1)
+
+#define PRM_BASE_ID		(PRM_BASE<<  BASE_ID_SHIFT)
+#define PRCM_MPU_BASE_ID	(PRCM_MPU_BASE<<  BASE_ID_SHIFT)
+#define CM2_BASE_ID		(CM2_BASE<<  BASE_ID_SHIFT)
+
+/* CM1 instances */
  #define OMAP4430_CM1_OCP_SOCKET_MOD	0x0000
  #define OMAP4430_CM1_CKGEN_MOD		0x0100
  #define OMAP4430_CM1_MPU_MOD		0x0300

@@ -71,19 +87,19 @@
 
  /* CM2 instances */
 
-#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000
-#define OMAP4430_CM2_CKGEN_MOD		0x0100
-#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600
-#define OMAP4430_CM2_CORE_MOD		0x0700
-#define OMAP4430_CM2_IVAHD_MOD		0x0f00
-#define OMAP4430_CM2_CAM_MOD		0x1000
-#define OMAP4430_CM2_DSS_MOD		0x1100
-#define OMAP4430_CM2_GFX_MOD		0x1200
-#define OMAP4430_CM2_L3INIT_MOD		0x1300
-#define OMAP4430_CM2_L4PER_MOD		0x1400
-#define OMAP4430_CM2_CEFUSE_MOD		0x1600
-#define OMAP4430_CM2_RESTORE_MOD	0x1e00
-#define OMAP4430_CM2_INSTR_MOD		0x1f00
+#define OMAP4430_CM2_OCP_SOCKET_MOD	0x0000 | CM2_BASE_ID
+#define OMAP4430_CM2_CKGEN_MOD		0x0100 | CM2_BASE_ID
+#define OMAP4430_CM2_ALWAYS_ON_MOD	0x0600 | CM2_BASE_ID
+#define OMAP4430_CM2_CORE_MOD		0x0700 | CM2_BASE_ID
+#define OMAP4430_CM2_IVAHD_MOD		0x0f00 | CM2_BASE_ID
+#define OMAP4430_CM2_CAM_MOD		0x1000 | CM2_BASE_ID
+#define OMAP4430_CM2_DSS_MOD		0x1100 | CM2_BASE_ID
+#define OMAP4430_CM2_GFX_MOD		0x1200 | CM2_BASE_ID
+#define OMAP4430_CM2_L3INIT_MOD		0x1300 | CM2_BASE_ID
+#define OMAP4430_CM2_L4PER_MOD		0x1400 | CM2_BASE_ID
+#define OMAP4430_CM2_CEFUSE_MOD		0x1600 | CM2_BASE_ID
+#define OMAP4430_CM2_RESTORE_MOD	0x1e00 | CM2_BASE_ID
+#define OMAP4430_CM2_INSTR_MOD		0x1f00 | CM2_BASE_ID
 
  /* PRM instances */

@@ -102,9 +118,9 @@
  #define OMAP4430_PRM_L4PER_MOD		0x1400
  #define OMAP4430_PRM_CEFUSE_MOD		0x1600
  #define OMAP4430_PRM_WKUP_MOD		0x1700
-#define OMAP4430_PRM_WKUP_CM_MOD	0x1800
+#define OMAP4430_PRM_WKUP_CM_MOD	0x1800 | PRM_BASE_ID
  #define OMAP4430_PRM_EMU_MOD		0x1900
-#define OMAP4430_PRM_EMU_CM_MOD		0x1a00
+#define OMAP4430_PRM_EMU_CM_MOD		0x1a00 | PRM_BASE_ID
  #define OMAP4430_PRM_DEVICE_MOD		0x1b00
  #define OMAP4430_PRM_INSTR_MOD		0x1f00

@@ -114,10 +130,10 @@
 
  /* PRCM_MPU instances */
 
-#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000
-#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200
-#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400
-#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD	0x0000 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD	0x0200 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_CPU0_MOD		0x0400 | PRCM_MPU_BASE_ID
+#define OMAP4430_PRCM_MPU_CPU1_MOD		0x0800 | PRCM_MPU_BASE_ID
 
 
  /* 24XX register bits shared between CM&  PRM registers */

arch/arm/mach-omap2/prcm.c +64 -4

index 4df30d0..124e866 100644
@@ -182,13 +182,40 @@ static inline void __omap_prcm_write(u32 value, void __iomem *base,
  /* Read a register in a PRM module */
  u32 prm_read_mod_reg(s16 module, u16 idx)
  {
-	return __omap_prcm_read(prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module)>>  BASE_ID_SHIFT;
+	module&= MOD_MASK;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		return __omap_prcm_read(prcm_mpu_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	default:
+		pr_err("Unknown PRM submodule base\n");
+	}
+	return 0;
  }
 
  /* Write into a register in a PRM module */
  void prm_write_mod_reg(u32 val, s16 module, u16 idx)
  {
-	__omap_prcm_write(val, prm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module)>>  BASE_ID_SHIFT;
+
+	switch (base) {
+	case PRCM_MPU_BASE:
+		__omap_prcm_write(val, prcm_mpu_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown PRM submodule base\n");
+		break;
+	}
  }
 
  /* Read-modify-write a register in a PRM module. Caller must lock */

@@ -219,13 +246,46 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
  /* Read a register in a CM module */
  u32 cm_read_mod_reg(s16 module, u16 idx)
  {
-	return __omap_prcm_read(cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module)>>  BASE_ID_SHIFT;
+	module&= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		return __omap_prcm_read(prm_base, module, idx);
+	case CM2_BASE:
+		return __omap_prcm_read(cm2_base, module, idx);
+	case DEFAULT_BASE:
+		return __omap_prcm_read(cm_base, module, idx);
+	default:
+		pr_err("Unknown CM submodule base\n");
+	}
+	return 0;
  }
 
  /* Write into a register in a CM module */
  void cm_write_mod_reg(u32 val, s16 module, u16 idx)
  {
-	__omap_prcm_write(val, cm_base, module, idx);
+	u32 base = 0;
+
+	base = abs(module)>>  BASE_ID_SHIFT;
+	module&= MOD_MASK;
+
+	switch (base) {
+	case PRM_BASE:
+		__omap_prcm_write(val, prm_base, module, idx);
+		break;
+	case CM2_BASE:
+		__omap_prcm_write(val, cm2_base, module, idx);
+		break;
+	case DEFAULT_BASE:
+		__omap_prcm_write(val, cm_base, module, idx);
+		break;
+	default:
+		pr_err("Unknown CM submodule base\n");
+		break;
+	}
  }
 
  /* Read-modify-write a register in a CM module. Caller must lock */

arch/arm/mach-omap2/prm.h +2 -3

index 588873b..72456cc 100644
@@ -23,9 +23,9 @@
  #define OMAP34XX_PRM_REGADDR(module, reg)				\
  		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
  #define OMAP44XX_PRM_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE +	((module)&  (MOD_MASK)) + (reg))
  #define OMAP44XX_PRCM_MPU_REGADDR(module, reg)				\
-		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
+		OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + ((module)&  (MOD_MASK)) + (reg))
 
  #include "prm44xx.h"
 
--

1.7.0.4

Quoted 5 lines

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- Paul

Tony Lindgren

maintainer

2010-10-18 22:53 UTC #9 lore raw

Re: [RFC][PATCH 2/2] OMAP4: PRCM: Fix usage of prm/cm accessor api's for OMAP4

Quoted 59 lines · Cousson, Benoit

Hi Paul,
Quoted 23 lines · Paul Walmsley
Hello Rajendra,
Quoted 19 lines · Rajendra Nayak
OMAP's have always had PRCM split into PRM for power and reset management and CM for clock management.
In OMAP4 the split (physically) is not very straight forward and there are instances of clock management control registers in PRM and vice versa.
However it still makes sense, even on OMAP4 to logically split PRCM into PRM and CM for better understanding and to avoid adding additonal complexity in higher level frameworks which rely on the accessor api;s to do the low level register accesses.
Hence this patch makes sure that any clock management code can use the cm_read/write* accessor apis (without knowing the physical split) and power and reset management code can use prm_read/write* accessor api;s.
To do this the submodule offsets within PRM/CM1 and CM2 have additonal info embedded in them specifying what base address to use while trying to access registers in the given submodule.
Quoted 8 lines
Quoted 3 lines
The 16 bit signed submodule offset is defined for OMAP4 as
<Bit 15> |<Bit 14:13> |<Bit 12:0>
<Sign bit> |<base identifier> |<submodule offset from base>
The concern that I have with embedding multiple parameters into a single parameter is that it seems like a hack. Why not add an extra parameter for the base identifier, rather than packing it into an existing parameter?
The primary constraint that lead us to that proposal was to minimize the impact on the existing code and API for previous OMAPs. That was clearly the goal #1.
The other one was the relative simplicity of the implementation.
The user of these OMAP4430_XXXX_MOD macros does not have to care if this is a real offset or just an id.
Quoted 6 lines
I am not necessarily opposed to your patch as it exists. But I would like to hear your opinions first on separating out the base identifier parameter as a separate function parameter, and then adding an extra field for it into any data structure that would need it. Could you write briefly if you see any significant advantages/disadvantages to that approach?
The disadvantage is the relative complexity for the caller of this API, that will have to know what partition should be used. It is fine if the caller is the powerdomain or clockdomain fmwk, but what about all the other callers we have here and there? When we looked at that in Bangalore, we realized that a bunch of code is using these prm/cm APIs. Maybe some cleanup can be done, like in the save / restore part, but we still have some user of that.

Quoted 4 lines

For the moment, I do not really see any advantage of such approach. The partitioning is changing on every OMAPs, so we do have to abstract that. If it is not done at that level, we will have to define another API on top of that to do exactly the same job.

I think we should be able to deal with the partitions properly by ioremapping them separately as needed. Might as well do it now.

Regards,

Tony