powerpc/8xxx: Refactor SRIO initialization into common code

PATCH Superseded Kumar Gala 4 participants 37 messages Jan 6, 2011 – Jan 11, 2011 PowerPC

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Kumar Gala

author

2011-01-06 16:58 UTC #0 lore raw

PATCH 1/7 powerpc/8xxx: Refactor SRIO initialization into common code

Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.

We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.

We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.

Introduced the following standard defines for board config.h:

CONFIG_SYS_HAS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)

[ These mimic what we have for PCI and PCIe controllers ]

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cpu_init.c     |    8 +++
 arch/powerpc/cpu/mpc85xx/fdt.c          |    7 +++
 arch/powerpc/cpu/mpc8xxx/Makefile       |    1 +
 arch/powerpc/cpu/mpc8xxx/fdt.c          |   21 ++++++++
 arch/powerpc/cpu/mpc8xxx/srio.c         |   86 +++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_law.h      |    1 +
 board/freescale/corenet_ds/corenet_ds.c |   44 ----------------
 include/configs/corenet_ds.h            |   17 +++---
 8 files changed, 133 insertions(+), 52 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c

arch/powerpc/cpu/mpc85xx/cpu_init.c +8 -0

index 4a6cc65..b2be1fc 100644
@@ -40,6 +40,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_HAS_SRIO
+extern void srio_init(void);
+#endif
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,

@@ -384,6 +388,10 @@ int cpu_init_r(void)
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();
 
+#ifdef CONFIG_SYS_HAS_SRIO
+	srio_init();
+#endif
+
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif

arch/powerpc/cpu/mpc85xx/fdt.c +7 -0

index 53e0596..5cfe497 100644
@@ -38,6 +38,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_qe_setup(void *blob);
 extern void ft_fixup_num_cores(void *blob);
+#ifdef CONFIG_SYS_HAS_SRIO
+extern void ft_srio_setup(void *blob);
+#endif
 
 #ifdef CONFIG_MP
 #include "mp.h"

@@ -478,4 +481,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_qportals(blob);
 #endif
+
+#ifdef CONFIG_SYS_HAS_SRIO
+	ft_srio_setup(blob);
+#endif
 }

arch/powerpc/cpu/mpc8xxx/Makefile +1 -0

index 95c73be..99332e6 100644
@@ -16,6 +16,7 @@ endif
 
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
+COBJS-$(CONFIG_SYS_HAS_SRIO) += srio.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/cpu/mpc8xxx/fdt.c +21 -0

index 54e60bb..e9dbdc2 100644
@@ -28,6 +28,7 @@
 #include <fdt_support.h>
 #include <asm/mp.h>
 #include <asm/fsl_enet.h>
+#include <asm/fsl_serdes.h>
 
 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)

@@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
 	return fdt_setprop_string(blob, offset, "phy-connection-type",
 					 fsl_phy_enet_if_str[phyc]);
 }
+
+#ifdef CONFIG_SYS_HAS_SRIO
+void ft_srio_setup(void *blob)
+{
+#ifdef CONFIG_SRIO1
+	if (!is_serdes_configured(SRIO1)) {
+		fdt_del_node_and_alias(blob, "rio0");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio0");
+#endif
+#ifdef CONFIG_SRIO2
+	if (!is_serdes_configured(SRIO2)) {
+		fdt_del_node_and_alias(blob, "rio1");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio1");
+#endif
+}
+#endif

arch/powerpc/cpu/mpc8xxx/srio.c new file +86 -0

86 lines not on this page · raw message

arch/powerpc/include/asm/fsl_law.h +1 -0

index 0e255ff..6a4279c 100644
@@ -90,6 +90,7 @@ enum law_trgt_if {
 #define LAW_TRGT_IF_PCI_1	LAW_TRGT_IF_PCI
 #define LAW_TRGT_IF_PCIX	LAW_TRGT_IF_PCI
 #define LAW_TRGT_IF_PCIE_2	LAW_TRGT_IF_PCI_2
+#define LAW_TRGT_IF_RIO_1	LAW_TRGT_IF_RIO
 
 #ifdef CONFIG_MPC8641
 #define LAW_TRGT_IF_PCIE_1	LAW_TRGT_IF_PCI

board/freescale/corenet_ds/corenet_ds.c +0 ~~-44~~

66 lines not on this page · raw message

include/configs/corenet_ds.h +9 -8

index e1cd1b0..477ca09 100644
@@ -51,6 +51,7 @@
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
+#define CONFIG_SYS_HAS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */

@@ -265,21 +266,21 @@
 /*
  * RapidIO
  */
-#define CONFIG_SYS_RIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_RIO1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_RIO1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
 
-#define CONFIG_SYS_RIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #else
-#define CONFIG_SYS_RIO2_MEM_PHYS	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
 #endif
-#define CONFIG_SYS_RIO2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
  * General PCI

Signature · 1 line

1.7.2.3

Kumar Gala

author

2011-01-06 16:58 UTC #1 lore raw

PATCH 2/7 powerpc/85xx: Convert MPC8548CDS to use common SRIO init code

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8548cds/law.c |    5 +----
 board/freescale/mpc8548cds/tlb.c |    9 ++++-----
 include/configs/MPC8548CDS.h     |   15 ++++++++-------
 3 files changed, 13 insertions(+), 16 deletions(-)

board/freescale/mpc8548cds/law.c +1 -4

index e59fee8..5b6943d 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -57,9 +57,6 @@ struct law_entry law_table[] = {
 #endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_RIO_MEM_PHYS
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8548cds/tlb.c +4 -5

index 2267ad7..b2c1b31 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -58,21 +58,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1G, 1),
 
-#ifdef CONFIG_SYS_RIO_MEM_PHYS
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/*
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
-#endif
+
 	/*
 	 * TLB 5:	64M	Non-cacheable, guarded
 	 * 0xe000_0000	1M	CCSRBAR

include/configs/MPC8548CDS.h +8 -7

index 4c5b998..da1f728 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007, 2010 Freescale Semiconductor.
+ * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -40,10 +40,12 @@
 #define CONFIG_SYS_TEXT_BASE	0xfff80000
 #endif
 
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		/* enable any pci type devices */
 #define CONFIG_PCI1		/* PCI controller 1 */
 #define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
-#undef CONFIG_RIO
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */

@@ -364,14 +366,13 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
 #endif
 
-#ifdef CONFIG_RIO
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_VIRT	0xC0000000
-#define CONFIG_SYS_RIO_MEM_BUS	0xC0000000
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
-#endif
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
 #ifdef CONFIG_LEGACY
 #define BRIDGE_ID 17

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 06:54 UTC #2 lore raw

PATCH 2/7 powerpc/85xx: Convert MPC8548CDS to use common SRIO init code

Quoted 6 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>

---

board/freescale/mpc8548cds/law.c |    5 +----
board/freescale/mpc8548cds/tlb.c |    9 ++++-----
include/configs/MPC8548CDS.h     |   15 ++++++++-------
3 files changed, 13 insertions(+), 16 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-06 16:58 UTC #3 lore raw

PATCH 3/7 powerpc/85xx: Convert MPC8568MDS to use common SRIO init code

In reply to Kumar Gala

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8568mds/law.c |    3 +--
 include/configs/MPC8568MDS.h     |   12 ++++++++----
 2 files changed, 9 insertions(+), 6 deletions(-)

board/freescale/mpc8568mds/law.c +1 -2

index e24b72b..c5cf7ba 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -50,7 +50,6 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };

include/configs/MPC8568MDS.h +8 -4

index a491650..0c858c9 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007, 2010 Freescale Semiconductor.
+ * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -35,6 +35,9 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xfff80000
 
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* PCI controller */
 #define CONFIG_PCIE1		1	/* PCIE controller */

@@ -303,9 +306,10 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 
-#define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_SRIO_MEM_BUS	0xc0000000
-#define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
 #ifdef CONFIG_QE
 /*

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 06:54 UTC #4 lore raw

PATCH 3/7 powerpc/85xx: Convert MPC8568MDS to use common SRIO init code

Quoted 5 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8568mds/law.c | 3 +--
include/configs/MPC8568MDS.h | 12 ++++++++----
2 files changed, 9 insertions(+), 6 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-06 16:58 UTC #5 lore raw

PATCH 4/7 powerpc/85xx: Convert MPC8569MDS to use common SRIO init code

In reply to Kumar Gala

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8569mds/law.c |    3 +--
 include/configs/MPC8569MDS.h     |   12 ++++++++----
 2 files changed, 9 insertions(+), 6 deletions(-)

board/freescale/mpc8569mds/law.c +1 -2

index bcd0311..4f4a93b 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -52,7 +52,6 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
 #endif
 	SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

include/configs/MPC8569MDS.h +8 -4

index 814c175..2c2d775 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -35,6 +35,9 @@
 
 #define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
 
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		1	/* Disable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */

@@ -355,9 +358,10 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 
-#define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_SRIO_MEM_BUS		0xc0000000
-#define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
 #ifdef CONFIG_QE
 /*

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 06:54 UTC #6 lore raw

PATCH 4/7 powerpc/85xx: Convert MPC8569MDS to use common SRIO init code

Quoted 5 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8569mds/law.c | 3 +--
include/configs/MPC8569MDS.h | 12 ++++++++----
2 files changed, 9 insertions(+), 6 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-06 16:58 UTC #7 lore raw

PATCH 5/7 powerpc/86xx: Enable common SRIO init code

In reply to Kumar Gala

Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/cpu/mpc86xx/fdt.c        |    9 ++++++++-
 arch/powerpc/include/asm/immap_86xx.h |    4 +++-
 2 files changed, 11 insertions(+), 2 deletions(-)

arch/powerpc/cpu/mpc86xx/fdt.c +8 -1

index ff89ee5..3b96bf5 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License

@@ -14,6 +14,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_fixup_num_cores(void *blob);
+#ifdef CONFIG_SYS_HAS_SRIO
+extern void ft_srio_setup(void *blob);
+#endif
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {

@@ -58,4 +61,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 	ft_fixup_num_cores(blob);
 #endif
+
+#ifdef CONFIG_SYS_HAS_SRIO
+	ft_srio_setup(blob);
+#endif
 }

arch/powerpc/include/asm/immap_86xx.h +3 -1

index 4e60cbb..cc338e4 100644
@@ -1,7 +1,7 @@
 /*
  * MPC86xx Internal Memory Map
  *
- * Copyright 2004 Freescale Semiconductor
+ * Copyright 2004, 2011 Freescale Semiconductor
  * Jeff Brown (Jeffrey at freescale.com)
  * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
  *

@@ -1205,6 +1205,8 @@ typedef struct ccsr_gur {
 #define MPC86xx_DEVDISR_PCI1	0x80000000
 #define MPC86xx_DEVDISR_PCIE1	0x40000000
 #define MPC86xx_DEVDISR_PCIE2	0x20000000
+#define MPC86xx_DEVDISR_SRIO	0x00080000
+#define MPC86xx_DEVDISR_RMSG	0x00040000
 #define MPC86xx_DEVDISR_CPU0	0x00008000
 #define MPC86xx_DEVDISR_CPU1	0x00004000
 #define MPC86xx_RSTCR_HRST_REQ	0x00000002

Signature · 1 line

1.7.2.3

Kumar Gala

author

2011-01-06 16:58 UTC #8 lore raw

PATCH 6/7 powerpc/86xx: Convert MPC8641HPCN to use common SRIO init code

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8641hpcn/law.c |    5 +----
 include/configs/MPC8641HPCN.h     |   30 +++++++++++++-----------------
 2 files changed, 14 insertions(+), 21 deletions(-)

board/freescale/mpc8641hpcn/law.c +1 -4

index 30a7b70..08f1eb2 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -53,9 +53,6 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
-#if defined(CONFIG_RIO)
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-#endif
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };

include/configs/MPC8641HPCN.h +13 ~~-17~~

index fea0876..dc3b1d7 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2006, 2010 Freescale Semiconductor.
+ * Copyright 2006, 2010-2011 Freescale Semiconductor.
  *
  * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
  *

@@ -57,18 +57,14 @@
  */
 #define CONFIG_SYS_SCRATCH_VA	0xe0000000
 
-/*
- * set this to enable Rapid IO.  PCI and RIO are mutually exclusive
- */
-/*#define CONFIG_RIO		1*/
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
 
-#ifndef CONFIG_RIO			/* RIO/PCI are mutually exclusive */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-#endif
 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */

@@ -319,13 +315,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE	0x80000000	/* base address */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO_MEM_PHYS  0x0000000c00000000ULL
+#define CONFIG_SYS_SRIO1_MEM_PHYS  0x0000000c00000000ULL
 #else
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BASE
 #endif
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI

@@ -514,18 +510,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 #else /* CONFIG_RIO */
-#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \
 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
 				 BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \
 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 #endif

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 06:54 UTC #9 lore raw

PATCH 6/7 powerpc/86xx: Convert MPC8641HPCN to use common SRIO init code

Quoted 5 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8641hpcn/law.c | 5 +----
include/configs/MPC8641HPCN.h | 30 +++++++++++++-----------------
2 files changed, 14 insertions(+), 21 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-06 16:58 UTC #10 lore raw

PATCH 7/7 powerpc/86xx: Convert SBC8641 to use common SRIO init code

In reply to Kumar Gala

Signed-off-by Kumar Gala <[email protected]>

CC Paul Gortmaker <[email protected]>

---
 board/sbc8641d/law.c       |    1 -
 include/configs/sbc8641d.h |   15 +++++++++------
 2 files changed, 9 insertions(+), 7 deletions(-)

board/sbc8641d/law.c +0 -1

index a6f60ee..14259d6 100644
@@ -51,7 +51,6 @@ struct law_entry law_table[] = {
 #endif
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

include/configs/sbc8641d.h +9 -6

index 90d84eb..f425150 100644
@@ -57,6 +57,9 @@
  */
 #define CONFIG_SYS_SCRATCH_VA	0xe8000000
 
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		1	/* Enable PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */

@@ -297,9 +300,9 @@
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI

@@ -417,10 +420,10 @@
  * BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 
 /*

Signature · 1 line

1.7.2.3

Paul Gortmaker

2011-01-06 19:34 UTC #11 lore raw

PATCH 7/7 powerpc/86xx: Convert SBC8641 to use common SRIO init code

Quoted 2 lines · [[PATCH 7/7] powerpc/86xx: Convert SBC8641 to use common SRIO init code] On…

Signed-off-by Kumar Gala <[email protected]>
CC Paul Gortmaker <[email protected]>

Tested in conjuntion with the mpc85xx dev branch and Peter's patch.

For some reason flash erase doesn't work, but I'm guessing that is a completely unrelated regression that I'll need to track down.

Tested-by Paul Gortmaker <[email protected]>

Quoted 61 lines

---
 board/sbc8641d/law.c       |    1 -
 include/configs/sbc8641d.h |   15 +++++++++------
 2 files changed, 9 insertions(+), 7 deletions(-)

board/sbc8641d/law.c +0 -1

index a6f60ee..14259d6 100644
@@ -51,7 +51,6 @@ struct law_entry law_table[] = {
 #endif
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

include/configs/sbc8641d.h +9 -6

index 90d84eb..f425150 100644
@@ -57,6 +57,9 @@
  */
 #define CONFIG_SYS_SCRATCH_VA	0xe8000000
 
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		1	/* Enable PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */

@@ -297,9 +300,9 @@
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI

@@ -417,10 +420,10 @@
  * BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 
 /*

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 06:54 UTC #12 lore raw

PATCH 7/7 powerpc/86xx: Convert SBC8641 to use common SRIO init code

In reply to Kumar Gala

Quoted 6 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
CC Paul Gortmaker <[email protected]>
---
board/sbc8641d/law.c | 1 -
include/configs/sbc8641d.h | 15 +++++++++------
2 files changed, 9 insertions(+), 7 deletions(-)

applied to 85xx

- k

Sergei Shtylyov

2011-01-09 12:53 UTC #13 lore raw

PATCH 5/7 powerpc/86xx: Enable common SRIO init code

In reply to Kumar Gala

Hello.

Quoted 14 lines · Kumar Gala

Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.
Signed-off-by Kumar Gala<[email protected]>
---
  arch/powerpc/cpu/mpc86xx/fdt.c        |    9 ++++++++-
  arch/powerpc/include/asm/immap_86xx.h |    4 +++-
  2 files changed, 11 insertions(+), 2 deletions(-)
arch/powerpc/cpu/mpc86xx/fdt.c +0 -0
index ff89ee5..3b96bf5 100644

[...]

arch/powerpc/cpu/mpc86xx/fdt.c line 19

Quoted 7 lines

arch/powerpc/cpu/mpc86xx/fdt.c +3 -0

@@ -14,6 +14,9 @@
  DECLARE_GLOBAL_DATA_PTR;
 
  extern void ft_fixup_num_cores(void *blob);
+#ifdef CONFIG_SYS_HAS_SRIO
+extern void ft_srio_setup(void *blob);
+#endif

There's no need to enclose the *extern* declaration within #ifdef.

WBR, Sergei

Kumar Gala

author

2011-01-09 21:16 UTC #14 lore raw

PATCH v2 1/7 powerpc/8xxx: Refactor SRIO initialization into common code

In reply to Kumar Gala

Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.

We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.

We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.

Introduced the following standard defines for board config.h:

CONFIG_SYS_HAS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

[ These mimic what we have for PCI and PCIe controllers ]

Signed-off-by Kumar Gala <[email protected]>

---
* Removed ifdef protection around externs per Sergei

 arch/powerpc/cpu/mpc85xx/cpu_init.c     |    8 +++-
 arch/powerpc/cpu/mpc85xx/fdt.c          |    7 ++-
 arch/powerpc/cpu/mpc8xxx/Makefile       |    1 +
 arch/powerpc/cpu/mpc8xxx/fdt.c          |   21 ++++++++
 arch/powerpc/cpu/mpc8xxx/srio.c         |   86 +++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_law.h      |    1 +
 board/freescale/corenet_ds/corenet_ds.c |   44 ----------------
 include/configs/corenet_ds.h            |   17 +++---
 8 files changed, 131 insertions(+), 54 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c

arch/powerpc/cpu/mpc85xx/cpu_init.c +7 -1

index 4a6cc65..98c70e9 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Modified by Xianghua Xiao, X.Xiao at motorola.com

@@ -40,6 +40,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+extern void srio_init(void);
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,

@@ -384,6 +386,10 @@ int cpu_init_r(void)
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();
 
+#ifdef CONFIG_SYS_HAS_SRIO
+	srio_init();
+#endif
+
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif

arch/powerpc/cpu/mpc85xx/fdt.c +6 -1

index 53e0596..e7e6a67 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_qe_setup(void *blob);
 extern void ft_fixup_num_cores(void *blob);
+extern void ft_srio_setup(void *blob);
 
 #ifdef CONFIG_MP
 #include "mp.h"

@@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_qportals(blob);
 #endif
+
+#ifdef CONFIG_SYS_HAS_SRIO
+	ft_srio_setup(blob);
+#endif
 }

arch/powerpc/cpu/mpc8xxx/Makefile +1 -0

index 95c73be..99332e6 100644
@@ -16,6 +16,7 @@ endif
 
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
+COBJS-$(CONFIG_SYS_HAS_SRIO) += srio.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/cpu/mpc8xxx/fdt.c +21 -0

index 54e60bb..e9dbdc2 100644
@@ -28,6 +28,7 @@
 #include <fdt_support.h>
 #include <asm/mp.h>
 #include <asm/fsl_enet.h>
+#include <asm/fsl_serdes.h>
 
 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)

@@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
 	return fdt_setprop_string(blob, offset, "phy-connection-type",
 					 fsl_phy_enet_if_str[phyc]);
 }
+
+#ifdef CONFIG_SYS_HAS_SRIO
+void ft_srio_setup(void *blob)
+{
+#ifdef CONFIG_SRIO1
+	if (!is_serdes_configured(SRIO1)) {
+		fdt_del_node_and_alias(blob, "rio0");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio0");
+#endif
+#ifdef CONFIG_SRIO2
+	if (!is_serdes_configured(SRIO2)) {
+		fdt_del_node_and_alias(blob, "rio1");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio1");
+#endif
+}
+#endif

arch/powerpc/cpu/mpc8xxx/srio.c new file +86 -0

86 lines not on this page · raw message

arch/powerpc/include/asm/fsl_law.h +1 -0

index 0e255ff..6a4279c 100644
@@ -90,6 +90,7 @@ enum law_trgt_if {
 #define LAW_TRGT_IF_PCI_1	LAW_TRGT_IF_PCI
 #define LAW_TRGT_IF_PCIX	LAW_TRGT_IF_PCI
 #define LAW_TRGT_IF_PCIE_2	LAW_TRGT_IF_PCI_2
+#define LAW_TRGT_IF_RIO_1	LAW_TRGT_IF_RIO
 
 #ifdef CONFIG_MPC8641
 #define LAW_TRGT_IF_PCIE_1	LAW_TRGT_IF_PCI

board/freescale/corenet_ds/corenet_ds.c +0 ~~-44~~

66 lines not on this page · raw message

include/configs/corenet_ds.h +9 -8

index e1cd1b0..477ca09 100644
@@ -51,6 +51,7 @@
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
+#define CONFIG_SYS_HAS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */

@@ -265,21 +266,21 @@
 /*
  * RapidIO
  */
-#define CONFIG_SYS_RIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_RIO1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_RIO1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
 
-#define CONFIG_SYS_RIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #else
-#define CONFIG_SYS_RIO2_MEM_PHYS	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
 #endif
-#define CONFIG_SYS_RIO2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
  * General PCI

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 06:53 UTC #15 lore raw

PATCH v2 1/7 powerpc/8xxx: Refactor SRIO initialization into common code

Quoted 21 lines · Kumar Gala

Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)

Quoted 5 lines

[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by Kumar Gala <[email protected]>
---
* Removed ifdef protection around externs per Sergei

applied to 85xx

- k

Kumar Gala

author

2011-01-09 21:16 UTC #16 lore raw

PATCH v2 5/7 powerpc/86xx: Enable common SRIO init code

In reply to Kumar Gala

Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.

Signed-off-by Kumar Gala <[email protected]>

---
* Removed ifdef protection around extern per Sergei
* Added missing call to srio_init

 arch/powerpc/cpu/mpc86xx/cpu_init.c   |    7 ++++++-
 arch/powerpc/cpu/mpc86xx/fdt.c        |    7 ++++++-
 arch/powerpc/include/asm/immap_86xx.h |    4 +++-
 3 files changed, 15 insertions(+), 3 deletions(-)

arch/powerpc/cpu/mpc86xx/cpu_init.c +6 -1

index 1d35c0c..cf3e4d6 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004,2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
  * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
  *

@@ -34,6 +34,7 @@
 #include <asm/fsl_serdes.h>
 #include <asm/mp.h>
 
+extern void srio_init(void);
 void setup_bats(void);
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -80,6 +81,10 @@ int cpu_init_r(void)
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();
 
+#ifdef CONFIG_SYS_HAS_SRIO
+	srio_init();
+#endif
+
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif

arch/powerpc/cpu/mpc86xx/fdt.c +6 -1

index ff89ee5..c3cd062 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License

@@ -14,6 +14,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_fixup_num_cores(void *blob);
+extern void ft_srio_setup(void *blob);
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {

@@ -58,4 +59,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 	ft_fixup_num_cores(blob);
 #endif
+
+#ifdef CONFIG_SYS_HAS_SRIO
+	ft_srio_setup(blob);
+#endif
 }

arch/powerpc/include/asm/immap_86xx.h +3 -1

index 4e60cbb..cc338e4 100644
@@ -1,7 +1,7 @@
 /*
  * MPC86xx Internal Memory Map
  *
- * Copyright 2004 Freescale Semiconductor
+ * Copyright 2004, 2011 Freescale Semiconductor
  * Jeff Brown (Jeffrey at freescale.com)
  * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
  *

@@ -1205,6 +1205,8 @@ typedef struct ccsr_gur {
 #define MPC86xx_DEVDISR_PCI1	0x80000000
 #define MPC86xx_DEVDISR_PCIE1	0x40000000
 #define MPC86xx_DEVDISR_PCIE2	0x20000000
+#define MPC86xx_DEVDISR_SRIO	0x00080000
+#define MPC86xx_DEVDISR_RMSG	0x00040000
 #define MPC86xx_DEVDISR_CPU0	0x00008000
 #define MPC86xx_DEVDISR_CPU1	0x00004000
 #define MPC86xx_RSTCR_HRST_REQ	0x00000002

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 06:54 UTC #17 lore raw

PATCH v2 5/7 powerpc/86xx: Enable common SRIO init code

Quoted 5 lines · Kumar Gala

Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.
Signed-off-by Kumar Gala <[email protected]>

Quoted 8 lines

---
* Removed ifdef protection around extern per Sergei
* Added missing call to srio_init

arch/powerpc/cpu/mpc86xx/cpu_init.c   |    7 ++++++-
arch/powerpc/cpu/mpc86xx/fdt.c        |    7 ++++++-
arch/powerpc/include/asm/immap_86xx.h |    4 +++-
3 files changed, 15 insertions(+), 3 deletions(-)

applied to 85xx

- k

Wolfgang Denk

2011-01-11 07:09 UTC #18 lore raw

PATCH v2 1/7 powerpc/8xxx: Refactor SRIO initialization into common code

In reply to Kumar Gala

Dear Kumar Gala,

Quoted 7 lines · In message <[email protected]> you…

Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.

Quoted 6 lines

We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not

We don't use a "CONFIG_SYS_HAS_*" normally; can we use plain CONFIG_SYS_SRIO instead? (yes, I am aware of the CONFIG_SYS_HAS_SERDES precedent, which escaped my attantion during review - that should be fixed, too).

Quoted 7 lines

CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)

These need to be documented (README).

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Wagner's music is better than it sounds."               - Mark Twain

Kumar Gala

author

2011-01-11 08:11 UTC #19 lore raw

PATCH v2 1/7 powerpc/8xxx: Refactor SRIO initialization into common code

Quoted 25 lines · Wolfgang Denk

Dear Kumar Gala,
Quoted 7 lines · In message <[email protected]> you…
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
Quoted 6 lines
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not
We don't use a "CONFIG_SYS_HAS_*" normally; can we use plain CONFIG_SYS_SRIO instead? (yes, I am aware of the CONFIG_SYS_HAS_SERDES precedent, which escaped my attantion during review - that should be fixed, too).
Quoted 3 lines
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

Quoted 6 lines

Quoted 4 lines
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
These need to be documented (README).

Changes made, please ACK the first patch in the series.

- k

Kumar Gala

author

2011-01-11 08:10 UTC #20 lore raw

PATCH v3 1/8 powerpc/8xxx: Refactor SRIO initialization into common code

In reply to Kumar Gala

Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.

We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.

We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.

Introduced the following standard defines for board config.h:

CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available

[ These mimic what we have for PCI and PCIe controllers ]

Signed-off-by Kumar Gala <[email protected]>

---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
* Added defines to README

 README                                  |   18 +++++++
 arch/powerpc/cpu/mpc85xx/cpu_init.c     |    8 +++-
 arch/powerpc/cpu/mpc85xx/fdt.c          |    7 ++-
 arch/powerpc/cpu/mpc8xxx/Makefile       |    1 +
 arch/powerpc/cpu/mpc8xxx/fdt.c          |   23 ++++++++-
 arch/powerpc/cpu/mpc8xxx/srio.c         |   86 +++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_law.h      |    1 +
 board/freescale/corenet_ds/corenet_ds.c |   44 ----------------
 include/configs/corenet_ds.h            |   19 ++++---
 9 files changed, 151 insertions(+), 56 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c

README +18 -0

index 68f5fb0..b30df12 100644
@@ -2771,6 +2771,24 @@ Low Level (hardware related) configuration options:
 		Disable PCI-Express on systems where it is supported but not
 		required.
 
+- CONFIG_SYS_SRIO:
+		Chip has SRIO or not
+
+- CONFIG_SRIO1:
+		Board has SRIO 1 port available
+
+- CONFIG_SRIO2:
+		Board has SRIO 2 port available
+
+- CONFIG_SYS_SRIOn_MEM_VIRT:
+		Virtual Address of SRIO port 'n' memory region
+
+- CONFIG_SYS_SRIOn_MEM_PHYS:
+		Physical Address of SRIO port 'n' memory region
+
+- CONFIG_SYS_SRIOn_MEM_SIZE:
+		Size of SRIO port 'n' memory region
+
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs

arch/powerpc/cpu/mpc85xx/cpu_init.c +7 -1

index 4a6cc65..1d016c4 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Modified by Xianghua Xiao, X.Xiao at motorola.com

@@ -40,6 +40,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+extern void srio_init(void);
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,

@@ -384,6 +386,10 @@ int cpu_init_r(void)
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();
 
+#ifdef CONFIG_SYS_SRIO
+	srio_init();
+#endif
+
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif

arch/powerpc/cpu/mpc85xx/fdt.c +6 -1

index 53e0596..00fa752 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_qe_setup(void *blob);
 extern void ft_fixup_num_cores(void *blob);
+extern void ft_srio_setup(void *blob);
 
 #ifdef CONFIG_MP
 #include "mp.h"

@@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_qportals(blob);
 #endif
+
+#ifdef CONFIG_SYS_SRIO
+	ft_srio_setup(blob);
+#endif
 }

arch/powerpc/cpu/mpc8xxx/Makefile +1 -0

index 95c73be..5dfd65b 100644
@@ -16,6 +16,7 @@ endif
 
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
+COBJS-$(CONFIG_SYS_SRIO) += srio.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/cpu/mpc8xxx/fdt.c +22 -1

index 54e60bb..0c166fd 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains

@@ -28,6 +28,7 @@
 #include <fdt_support.h>
 #include <asm/mp.h>
 #include <asm/fsl_enet.h>
+#include <asm/fsl_serdes.h>
 
 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
 static int ft_del_cpuhandle(void *blob, int cpuhandle)

@@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
 	return fdt_setprop_string(blob, offset, "phy-connection-type",
 					 fsl_phy_enet_if_str[phyc]);
 }
+
+#ifdef CONFIG_SYS_SRIO
+void ft_srio_setup(void *blob)
+{
+#ifdef CONFIG_SRIO1
+	if (!is_serdes_configured(SRIO1)) {
+		fdt_del_node_and_alias(blob, "rio0");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio0");
+#endif
+#ifdef CONFIG_SRIO2
+	if (!is_serdes_configured(SRIO2)) {
+		fdt_del_node_and_alias(blob, "rio1");
+	}
+#else
+	fdt_del_node_and_alias(blob, "rio1");
+#endif
+}
+#endif

arch/powerpc/cpu/mpc8xxx/srio.c new file +86 -0

86 lines not on this page · raw message

arch/powerpc/include/asm/fsl_law.h +1 -0

index 0e255ff..6a4279c 100644
@@ -90,6 +90,7 @@ enum law_trgt_if {
 #define LAW_TRGT_IF_PCI_1	LAW_TRGT_IF_PCI
 #define LAW_TRGT_IF_PCIX	LAW_TRGT_IF_PCI
 #define LAW_TRGT_IF_PCIE_2	LAW_TRGT_IF_PCI_2
+#define LAW_TRGT_IF_RIO_1	LAW_TRGT_IF_RIO
 
 #ifdef CONFIG_MPC8641
 #define LAW_TRGT_IF_PCIE_1	LAW_TRGT_IF_PCI

board/freescale/corenet_ds/corenet_ds.c +0 ~~-44~~

66 lines not on this page · raw message

include/configs/corenet_ds.h +10 -9

index e1cd1b0..d1ac756 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -51,6 +51,7 @@
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
 
+#define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */

@@ -265,21 +266,21 @@
 /*
  * RapidIO
  */
-#define CONFIG_SYS_RIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_RIO1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_RIO1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
 
-#define CONFIG_SYS_RIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #else
-#define CONFIG_SYS_RIO2_MEM_PHYS	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
 #endif
-#define CONFIG_SYS_RIO2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
  * General PCI

Signature · 1 line

1.7.2.3

Kumar Gala

author

2011-01-11 08:10 UTC #21 lore raw

PATCH v3 2/8 powerpc/85xx: Convert MPC8548CDS to use common SRIO init code

Signed-off-by Kumar Gala <[email protected]>

---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO

 board/freescale/mpc8548cds/law.c |    5 +----
 board/freescale/mpc8548cds/tlb.c |    9 ++++-----
 include/configs/MPC8548CDS.h     |   15 ++++++++-------
 3 files changed, 13 insertions(+), 16 deletions(-)

board/freescale/mpc8548cds/law.c +1 -4

index e59fee8..5b6943d 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -57,9 +57,6 @@ struct law_entry law_table[] = {
 #endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_RIO_MEM_PHYS
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8548cds/tlb.c +4 -5

index 2267ad7..b2c1b31 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -58,21 +58,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1G, 1),
 
-#ifdef CONFIG_SYS_RIO_MEM_PHYS
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/*
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
-#endif
+
 	/*
 	 * TLB 5:	64M	Non-cacheable, guarded
 	 * 0xe000_0000	1M	CCSRBAR

include/configs/MPC8548CDS.h +8 -7

index 4c5b998..ececa38 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007, 2010 Freescale Semiconductor.
+ * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -40,10 +40,12 @@
 #define CONFIG_SYS_TEXT_BASE	0xfff80000
 #endif
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		/* enable any pci type devices */
 #define CONFIG_PCI1		/* PCI controller 1 */
 #define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
-#undef CONFIG_RIO
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */

@@ -364,14 +366,13 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
 #endif
 
-#ifdef CONFIG_RIO
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_VIRT	0xC0000000
-#define CONFIG_SYS_RIO_MEM_BUS	0xC0000000
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
-#endif
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
 #ifdef CONFIG_LEGACY
 #define BRIDGE_ID 17

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 14:13 UTC #22 lore raw

PATCH v3 2/8 powerpc/85xx: Convert MPC8548CDS to use common SRIO init code

Quoted 8 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8548cds/law.c |    5 +----
board/freescale/mpc8548cds/tlb.c |    9 ++++-----
include/configs/MPC8548CDS.h     |   15 ++++++++-------
3 files changed, 13 insertions(+), 16 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-11 08:10 UTC #23 lore raw

PATCH v3 3/8 powerpc/85xx: Convert MPC8568MDS to use common SRIO init code

In reply to Kumar Gala

Signed-off-by Kumar Gala <[email protected]>

---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO

 board/freescale/mpc8568mds/law.c |    3 +--
 include/configs/MPC8568MDS.h     |   12 ++++++++----
 2 files changed, 9 insertions(+), 6 deletions(-)

board/freescale/mpc8568mds/law.c +1 -2

index e24b72b..c5cf7ba 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -50,7 +50,6 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };

include/configs/MPC8568MDS.h +8 -4

index a491650..f684e79 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007, 2010 Freescale Semiconductor.
+ * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -35,6 +35,9 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xfff80000
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* PCI controller */
 #define CONFIG_PCIE1		1	/* PCIE controller */

@@ -303,9 +306,10 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 
-#define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_SRIO_MEM_BUS	0xc0000000
-#define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
 #ifdef CONFIG_QE
 /*

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 14:13 UTC #24 lore raw

PATCH v3 3/8 powerpc/85xx: Convert MPC8568MDS to use common SRIO init code

Quoted 7 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8568mds/law.c | 3 +--
include/configs/MPC8568MDS.h | 12 ++++++++----
2 files changed, 9 insertions(+), 6 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-11 08:10 UTC #25 lore raw

PATCH v3 4/8 powerpc/85xx: Convert MPC8569MDS to use common SRIO init code

In reply to Kumar Gala

Signed-off-by Kumar Gala <[email protected]>

---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO

 board/freescale/mpc8569mds/law.c |    3 +--
 include/configs/MPC8569MDS.h     |   12 ++++++++----
 2 files changed, 9 insertions(+), 6 deletions(-)

board/freescale/mpc8569mds/law.c +1 -2

index bcd0311..4f4a93b 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -52,7 +52,6 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
 #endif
 	SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

include/configs/MPC8569MDS.h +8 -4

index 814c175..3372d18 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -35,6 +35,9 @@
 
 #define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		1	/* Disable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */

@@ -355,9 +358,10 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
 
-#define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_SRIO_MEM_BUS		0xc0000000
-#define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
 #ifdef CONFIG_QE
 /*

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 14:13 UTC #26 lore raw

PATCH v3 4/8 powerpc/85xx: Convert MPC8569MDS to use common SRIO init code

Quoted 7 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8569mds/law.c | 3 +--
include/configs/MPC8569MDS.h | 12 ++++++++----
2 files changed, 9 insertions(+), 6 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-11 08:10 UTC #27 lore raw

PATCH v3 5/8 powerpc/86xx: Enable common SRIO init code

In reply to Kumar Gala

Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.

Signed-off-by Kumar Gala <[email protected]>

---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO

 arch/powerpc/cpu/mpc86xx/cpu_init.c   |    7 ++++++-
 arch/powerpc/cpu/mpc86xx/fdt.c        |    7 ++++++-
 arch/powerpc/include/asm/immap_86xx.h |    4 +++-
 3 files changed, 15 insertions(+), 3 deletions(-)

arch/powerpc/cpu/mpc86xx/cpu_init.c +6 -1

index 1d35c0c..8022024 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004,2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
  * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
  *

@@ -34,6 +34,7 @@
 #include <asm/fsl_serdes.h>
 #include <asm/mp.h>
 
+extern void srio_init(void);
 void setup_bats(void);
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -80,6 +81,10 @@ int cpu_init_r(void)
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();
 
+#ifdef CONFIG_SYS_SRIO
+	srio_init();
+#endif
+
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif

arch/powerpc/cpu/mpc86xx/fdt.c +6 -1

index ff89ee5..61f5110 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License

@@ -14,6 +14,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void ft_fixup_num_cores(void *blob);
+extern void ft_srio_setup(void *blob);
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {

@@ -58,4 +59,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 	ft_fixup_num_cores(blob);
 #endif
+
+#ifdef CONFIG_SYS_SRIO
+	ft_srio_setup(blob);
+#endif
 }

arch/powerpc/include/asm/immap_86xx.h +3 -1

index 4e60cbb..cc338e4 100644
@@ -1,7 +1,7 @@
 /*
  * MPC86xx Internal Memory Map
  *
- * Copyright 2004 Freescale Semiconductor
+ * Copyright 2004, 2011 Freescale Semiconductor
  * Jeff Brown (Jeffrey at freescale.com)
  * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
  *

@@ -1205,6 +1205,8 @@ typedef struct ccsr_gur {
 #define MPC86xx_DEVDISR_PCI1	0x80000000
 #define MPC86xx_DEVDISR_PCIE1	0x40000000
 #define MPC86xx_DEVDISR_PCIE2	0x20000000
+#define MPC86xx_DEVDISR_SRIO	0x00080000
+#define MPC86xx_DEVDISR_RMSG	0x00040000
 #define MPC86xx_DEVDISR_CPU0	0x00008000
 #define MPC86xx_DEVDISR_CPU1	0x00004000
 #define MPC86xx_RSTCR_HRST_REQ	0x00000002

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 14:13 UTC #28 lore raw

PATCH v3 5/8 powerpc/86xx: Enable common SRIO init code

Quoted 4 lines · Kumar Gala

Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board.

Quoted 8 lines

Signed-off-by Kumar Gala <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
arch/powerpc/cpu/mpc86xx/cpu_init.c   |    7 ++++++-
arch/powerpc/cpu/mpc86xx/fdt.c        |    7 ++++++-
arch/powerpc/include/asm/immap_86xx.h |    4 +++-
3 files changed, 15 insertions(+), 3 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-11 08:10 UTC #29 lore raw

PATCH v3 6/8 powerpc/86xx: Convert MPC8641HPCN to use common SRIO init code

In reply to Kumar Gala

Signed-off-by Kumar Gala <[email protected]>

---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO

 board/freescale/mpc8641hpcn/law.c |    5 +----
 include/configs/MPC8641HPCN.h     |   30 +++++++++++++-----------------
 2 files changed, 14 insertions(+), 21 deletions(-)

board/freescale/mpc8641hpcn/law.c +1 -4

index 30a7b70..08f1eb2 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -53,9 +53,6 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
-#if defined(CONFIG_RIO)
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-#endif
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
 };

include/configs/MPC8641HPCN.h +13 ~~-17~~

index fea0876..0cca603 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2006, 2010 Freescale Semiconductor.
+ * Copyright 2006, 2010-2011 Freescale Semiconductor.
  *
  * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
  *

@@ -57,18 +57,14 @@
  */
 #define CONFIG_SYS_SCRATCH_VA	0xe0000000
 
-/*
- * set this to enable Rapid IO.  PCI and RIO are mutually exclusive
- */
-/*#define CONFIG_RIO		1*/
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
 
-#ifndef CONFIG_RIO			/* RIO/PCI are mutually exclusive */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-#endif
 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */

@@ -319,13 +315,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE	0x80000000	/* base address */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO_MEM_PHYS  0x0000000c00000000ULL
+#define CONFIG_SYS_SRIO1_MEM_PHYS  0x0000000c00000000ULL
 #else
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BASE
 #endif
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI

@@ -514,18 +510,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 #else /* CONFIG_RIO */
-#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \
 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
 				 BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 				 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \
 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
 
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 #endif

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 14:14 UTC #30 lore raw

PATCH v3 6/8 powerpc/86xx: Convert MPC8641HPCN to use common SRIO init code

Quoted 7 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/freescale/mpc8641hpcn/law.c | 5 +----
include/configs/MPC8641HPCN.h | 30 +++++++++++++-----------------
2 files changed, 14 insertions(+), 21 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-11 08:10 UTC #31 lore raw

PATCH v3 7/8 powerpc/86xx: Convert SBC8641 to use common SRIO init code

In reply to Kumar Gala

Signed-off-by Kumar Gala <[email protected]>

Tested-by Paul Gortmaker <[email protected]>

---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO

 board/sbc8641d/law.c       |    1 -
 include/configs/sbc8641d.h |   15 +++++++++------
 2 files changed, 9 insertions(+), 7 deletions(-)

board/sbc8641d/law.c +0 -1

index a6f60ee..14259d6 100644
@@ -51,7 +51,6 @@ struct law_entry law_table[] = {
 #endif
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

include/configs/sbc8641d.h +9 -6

index 90d84eb..8d9f931 100644
@@ -57,6 +57,9 @@
  */
 #define CONFIG_SYS_SCRATCH_VA	0xe8000000
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		1	/* Enable PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */

@@ -297,9 +300,9 @@
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI

@@ -417,10 +420,10 @@
  * BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 
 /*

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 14:14 UTC #32 lore raw

PATCH v3 7/8 powerpc/86xx: Convert SBC8641 to use common SRIO init code

Quoted 8 lines · Kumar Gala

Signed-off-by Kumar Gala <[email protected]>
Tested-by Paul Gortmaker <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
board/sbc8641d/law.c | 1 -
include/configs/sbc8641d.h | 15 +++++++++------
2 files changed, 9 insertions(+), 7 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2011-01-11 08:10 UTC #33 lore raw

PATCH v3 8/8 powerpc/85xx: Add SRIO support to P2020DS

In reply to Kumar Gala

From: Li Yang <[email protected]>

The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code.

Signed-off-by Li Yang <[email protected]>

Signed-off-by Kumar Gala <[email protected]>

---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO

 include/configs/P2020DS.h |   24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)

include/configs/P2020DS.h +23 -1

index 24f2498..c2636af 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -45,6 +45,10 @@
 #define CONFIG_SYS_TEXT_BASE	0xeff80000
 #endif
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */

@@ -472,6 +476,24 @@
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 #endif
 
+/* SRIO1 uses the same window as PCIE2 mem window */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+/* SRIO2 uses the same window as PCIE1 mem window */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x20000000	/* 512M */
+
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */

Signature · 1 line

1.7.2.3

Kumar Gala

author Applied

2011-01-11 14:14 UTC #34 lore raw

PATCH v3 8/8 powerpc/85xx: Add SRIO support to P2020DS

Quoted 5 lines · Kumar Gala

From: Li Yang <[email protected]>
The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code.

Quoted 7 lines

Signed-off-by Li Yang <[email protected]>
Signed-off-by Kumar Gala <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
include/configs/P2020DS.h | 24 +++++++++++++++++++++++-
1 files changed, 23 insertions(+), 1 deletions(-)

applied to 85xx

- k

Wolfgang Denk

2011-01-11 09:46 UTC #35 lore raw

PATCH v3 1/8 powerpc/8xxx: Refactor SRIO initialization into common code

In reply to Kumar Gala

Dear Kumar Gala,

Quoted 28 lines · In message <[email protected]> you…

Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by Kumar Gala <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
* Added defines to README

Quoted 11 lines

 README                                  |   18 +++++++
 arch/powerpc/cpu/mpc85xx/cpu_init.c     |    8 +++-
 arch/powerpc/cpu/mpc85xx/fdt.c          |    7 ++-
 arch/powerpc/cpu/mpc8xxx/Makefile       |    1 +
 arch/powerpc/cpu/mpc8xxx/fdt.c          |   23 ++++++++-
 arch/powerpc/cpu/mpc8xxx/srio.c         |   86 +++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/fsl_law.h      |    1 +
 board/freescale/corenet_ds/corenet_ds.c |   44 ----------------
 include/configs/corenet_ds.h            |   19 ++++---
 9 files changed, 151 insertions(+), 56 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c

Acked-by Wolfgang Denk <[email protected]>

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Syntactic sugar causes cancer of the semicolon.
                - Epigrams in Programming, ACM SIGPLAN Sept. 1982

Kumar Gala

author Applied

2011-01-11 14:13 UTC #36 lore raw

PATCH v3 1/8 powerpc/8xxx: Refactor SRIO initialization into common code

Quoted 43 lines · Wolfgang Denk

Dear Kumar Gala,
Quoted 38 lines · In message <[email protected]> you…
Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by Kumar Gala <[email protected]>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
* Added defines to README
README                                  |   18 +++++++
arch/powerpc/cpu/mpc85xx/cpu_init.c     |    8 +++-
arch/powerpc/cpu/mpc85xx/fdt.c          |    7 ++-
arch/powerpc/cpu/mpc8xxx/Makefile       |    1 +
arch/powerpc/cpu/mpc8xxx/fdt.c          |   23 ++++++++-
arch/powerpc/cpu/mpc8xxx/srio.c         |   86 +++++++++++++++++++++++++++++++
arch/powerpc/include/asm/fsl_law.h      |    1 +
board/freescale/corenet_ds/corenet_ds.c |   44 ----------------
include/configs/corenet_ds.h            |   19 ++++---
9 files changed, 151 insertions(+), 56 deletions(-)
Quoted 1 line
create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c

Quoted 1 line

Acked-by Wolfgang Denk <[email protected]>

applied to 85xx

- k