powerpc/fsl-pci: Add generic code to setup PCIe controllers

PATCH New Kumar Gala 3 participants 38 messages Dec 17, 2010 – Jan 9, 2011

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PowerPC PCI

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Kumar Gala

author

2010-12-17 23:50 UTC #0 lore raw

PATCH 1/15 powerpc/fsl-pci: Add generic code to setup PCIe controllers

Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons.

We also provide a per controller (rather than all) for some systems that may have special requirements.

Finally, we refactor the code used by the P1022DS to utilize the new generic code.

Signed-off-by Kumar Gala <[email protected]>

---
 arch/powerpc/include/asm/fsl_pci.h |   10 +++
 board/freescale/p1022ds/p1022ds.c  |   67 +------------------
 drivers/pci/fsl_pci_init.c         |  127 ++++++++++++++++++++++++++++++++++++
 3 files changed, 139 insertions(+), 65 deletions(-)

arch/powerpc/include/asm/fsl_pci.h +10 -0

index 5cbe139..15ab50d 100644
@@ -22,6 +22,8 @@
 #define __FSL_PCI_H_
 
 #include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <pci.h>
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);

@@ -172,6 +174,9 @@ struct fsl_pci_info {
 
 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 				struct pci_controller *hose, int busno);
+int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
+			struct fsl_pci_info *pci_info);
+int fsl_pcie_init_board(int busno);
 
 #define SET_STD_PCI_INFO(x, num) \
 {			\

@@ -220,6 +225,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	FT_FSL_PCIE2_SETUP; \
 	FT_FSL_PCIE3_SETUP; \
 	FT_FSL_PCIE4_SETUP;
+#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
 #elif defined(CONFIG_MPC85xx)
 #define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
 #define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"

@@ -229,6 +235,10 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	FT_FSL_PCIE1_SETUP; \
 	FT_FSL_PCIE2_SETUP; \
 	FT_FSL_PCIE3_SETUP;
+#define FT_FSL_PCIE_SETUP \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP; \
+	FT_FSL_PCIE3_SETUP;
 #elif defined(CONFIG_MPC86xx)
 #define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
 #define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"

board/freescale/p1022ds/p1022ds.c +2 ~~-65~~

82 lines not on this page · raw message

drivers/pci/fsl_pci_init.c +127 -0

139 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:45 UTC #1 lore raw

PATCH 1/15 powerpc/fsl-pci: Add generic code to setup PCIe controllers

Quoted 12 lines · Kumar Gala

Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons.
We also provide a per controller (rather than all) for some systems that may have special requirements.
Finally, we refactor the code used by the P1022DS to utilize the new generic code.

Quoted 6 lines

Signed-off-by Kumar Gala <[email protected]>

---

arch/powerpc/include/asm/fsl_pci.h |   10 +++
board/freescale/p1022ds/p1022ds.c  |   67 +------------------
drivers/pci/fsl_pci_init.c         |  127 ++++++++++++++++++++++++++++++++++++
3 files changed, 139 insertions(+), 65 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2010-12-17 23:50 UTC #2 lore raw

PATCH 2/15 powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8572DS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8572ds/law.c       |    8 +--
 board/freescale/mpc8572ds/mpc8572ds.c |  100 ++++++--------------------------
 2 files changed, 20 insertions(+), 88 deletions(-)

board/freescale/mpc8572ds/law.c +1 -7

index e13bb53..7c63f84 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -29,12 +29,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };

board/freescale/mpc8572ds/mpc8572ds.c +19 ~~-81~~

126 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:46 UTC #3 lore raw

PATCH 2/15 powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in MPC8572DS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8572ds/law.c | 8 +--
board/freescale/mpc8572ds/mpc8572ds.c | 100 ++++++--------------------------
2 files changed, 20 insertions(+), 88 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

* added signed off by Chenhui Zhao <[email protected]>

- k

Kumar Gala

author

2010-12-17 23:50 UTC #4 lore raw

PATCH 3/15 powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in P2020DS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/p2020ds/law.c     |    8 +--
 board/freescale/p2020ds/p2020ds.c |  114 ++++---------------------------------
 2 files changed, 12 insertions(+), 110 deletions(-)

board/freescale/p2020ds/law.c +1 -7

index 28ed2ed..91642a9 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -29,12 +29,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };

board/freescale/p2020ds/p2020ds.c +11 ~~-103~~

124 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:46 UTC #5 lore raw

PATCH 3/15 powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in P2020DS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/p2020ds/law.c | 8 +--
board/freescale/p2020ds/p2020ds.c | 114 ++++---------------------------------
2 files changed, 12 insertions(+), 110 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

Added attribution to Leo Li's original P2020 DS serdes clean up patches.

- k

Kumar Gala

author

2010-12-17 23:50 UTC #6 lore raw

PATCH 4/15 powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8544DS board and utliize the common fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3 specially to setup the additional memory map region and we utilize a single LAW to cover the controller.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8544ds/law.c       |   10 +---
 board/freescale/mpc8544ds/mpc8544ds.c |  110 +++++++++++----------------------
 2 files changed, 37 insertions(+), 83 deletions(-)

board/freescale/mpc8544ds/law.c +1 -9

index 3d308c8..59e03fc 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -28,15 +28,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	/* contains both PCIE3 MEM & IO space */
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8544ds/mpc8544ds.c +36 ~~-74~~

170 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:47 UTC #7 lore raw

PATCH 4/15 powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe code

Quoted 8 lines · Kumar Gala

Remove duplicated code in MPC8544DS board and utliize the common fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3 specially to setup the additional memory map region and we utilize a single LAW to cover the controller.

Quoted 5 lines

Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8544ds/law.c | 10 +---
board/freescale/mpc8544ds/mpc8544ds.c | 110 +++++++++++----------------------
2 files changed, 37 insertions(+), 83 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #8 lore raw

PATCH 5/15 powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8536DS board and utliize the common fsl_pcie_init_board().

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8536ds/mpc8536ds.c |  125 ++++++--------------------------
 1 files changed, 24 insertions(+), 101 deletions(-)

board/freescale/mpc8536ds/mpc8536ds.c +24 ~~-101~~

index bd80cb7..c005ab7 100644
@@ -177,123 +177,46 @@ phys_size_t fixed_sdram (void)
 static struct pci_controller pci1_hose;
 #endif
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
+#ifdef CONFIG_PCI
+static const char *slot_names[] = {
+	[PCIE1] = "Slot 1",
+	[PCIE2] = "Slot 2",
+	[PCIE3] = "Slot 3",
+};
 
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
 
-#ifdef CONFIG_PCI
 void pci_init_board(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[4];
-	u32 devdisr, pordevsr, io_sel;
+	struct fsl_pci_info pci_info;
+	u32 devdisr, pordevsr;
 	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-	int first_free_busno = 0;
-	int num = 0;
+	int first_free_busno;
 
-	int pcie_ep, pcie_configured;
+	first_free_busno = fsl_pcie_init_board(0);
 
+#ifdef CONFIG_PCI1
 	devdisr = in_be32(&gur->devdisr);
 	pordevsr = in_be32(&gur->pordevsr);
 	porpllsr = in_be32(&gur->porpllsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
-	puts("\n");
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
-		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
-				LAW_TRGT_IF_PCIE_3);
-		set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
-				LAW_TRGT_IF_PCIE_3);
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-		printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
-				LAW_TRGT_IF_PCIE_1);
-		set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
-				LAW_TRGT_IF_PCIE_1);
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
-		set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
-				LAW_TRGT_IF_PCIE_2);
-		set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
-				LAW_TRGT_IF_PCIE_2);
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCI1
 	pci_speed = 66666000;
 	pci_32 = 1;
 	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
-				LAW_TRGT_IF_PCI);
-		set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
-				LAW_TRGT_IF_PCI);
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :

@@ -301,9 +224,9 @@ void pci_init_board(void)
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info[num].regs);
+			pci_info.regs);
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI: disabled\n");

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:47 UTC #9 lore raw

PATCH 5/15 powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe code

Quoted 7 lines · Kumar Gala

Remove duplicated code in MPC8536DS board and utliize the common fsl_pcie_init_board().
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8536ds/mpc8536ds.c | 125 ++++++--------------------------
1 files changed, 24 insertions(+), 101 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #10 lore raw

PATCH 6/15 powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8641HPCN board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8641hpcn/law.c         |    7 +---
 board/freescale/mpc8641hpcn/mpc8641hpcn.c |   56 +++++-----------------------
 2 files changed, 11 insertions(+), 52 deletions(-)

board/freescale/mpc8641hpcn/law.c +1 -6

index 8c8ce95..30a7b70 100644
@@ -53,12 +53,7 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
-#ifdef CONFIG_PCI
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
-#elif defined(CONFIG_RIO)
+#if defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),

board/freescale/mpc8641hpcn/mpc8641hpcn.c +10 ~~-46~~

74 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:48 UTC #11 lore raw

PATCH 6/15 powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in MPC8641HPCN board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8641hpcn/law.c | 7 +---
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 56 +++++-----------------------
2 files changed, 11 insertions(+), 52 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #12 lore raw

PATCH 7/15 powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8548CDS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8548cds/law.c        |   10 +------
 board/freescale/mpc8548cds/mpc8548cds.c |   46 ++++++++++---------------------
 2 files changed, 16 insertions(+), 40 deletions(-)

board/freescale/mpc8548cds/law.c +1 -9

index 98748aa..e59fee8 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -51,18 +51,10 @@
  */
 
 struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-#endif
 #ifdef CONFIG_SYS_PCI2_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
 #endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
-#endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_SYS_RIO_MEM_PHYS

board/freescale/mpc8548cds/mpc8548cds.c +15 ~~-31~~

78 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:48 UTC #13 lore raw

PATCH 7/15 powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in MPC8548CDS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8548cds/law.c        |   10 +------
board/freescale/mpc8548cds/mpc8548cds.c |   46 ++++++++++---------------------
2 files changed, 16 insertions(+), 40 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #14 lore raw

PATCH 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8572 DS board and utliize the common fsl_pcie_init_board().

Signed-off-by Kumar Gala <[email protected]>

CC Peter Tyser <[email protected]>

---
 board/xes/common/fsl_8xxx_pci.c |   82 ++++-----------------------------------
 board/xes/xpedite517x/law.c     |    8 ----
 board/xes/xpedite520x/law.c     |    4 --
 board/xes/xpedite537x/law.c     |   12 ------
 board/xes/xpedite550x/law.c     |   12 ------
 5 files changed, 8 insertions(+), 110 deletions(-)

board/xes/common/fsl_8xxx_pci.c +8 ~~-74~~

index 4135849..202520d 100644
@@ -34,15 +34,6 @@
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
 
 /*
  * 85xx and 86xx share naming conventions, but different layout.

@@ -69,22 +60,13 @@ static struct pci_controller pcie3_hose;
 
 void pci_init_board(void)
 {
-	struct fsl_pci_info pci_info[3];
 	int first_free_busno = 0;
-	int num = 0;
-	int pcie_ep;
-	__maybe_unused int pcie_configured;
 
-#if defined(CONFIG_MPC85xx)
+#ifdef CONFIG_PCI1
+	int pcie_ep;
+	struct fsl_pci_info pci_info;
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#elif defined(CONFIG_MPC86xx)
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-#endif
 	u32 devdisr = in_be32(&gur->devdisr);
-
-#ifdef CONFIG_PCI1
-	u32 pordevsr = in_be32(&gur->pordevsr);
 	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
 	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
 	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;

@@ -92,8 +74,8 @@ void pci_init_board(void)
 	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
 			pci_32 ? 32 : 64,
 			pcix ? "PCIX" : "PCI",

@@ -102,66 +84,18 @@ void pci_init_board(void)
 			pcie_ep ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter");
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI1: disabled\n");
 	}
 #elif defined CONFIG_MPC8548
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	/* PCI1 not present on MPC8572 */
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
 #endif
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
-#endif /* CONFIG_PCIE1 */
-
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
-#endif /* CONFIG_PCIE2 */
-
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-		printf("PCIE3: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
-#endif /* CONFIG_PCIE3 */
+	fsl_pcie_init_board(first_free_busno);
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)

board/xes/xpedite517x/law.c +0 -8

index 0b7d9ef..df23df1 100644
@@ -39,14 +39,6 @@ struct law_entry law_table[] = {
 	/* NAND LAW covers 2 NAND flashes */
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
 #endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/xes/xpedite520x/law.c +0 -4

index bbfcb9d..3afb3ae 100644
@@ -38,10 +38,6 @@ struct law_entry law_table[] = {
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#if CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
-#endif
 #if CONFIG_SYS_PCI2_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),

board/xes/xpedite537x/law.c +0 ~~-12~~

index daee676..54c28da 100644
@@ -37,18 +37,6 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/xes/xpedite550x/law.c +0 ~~-12~~

index 4d4445d..66f1cf9 100644
@@ -37,18 +37,6 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

Signature · 1 line

1.6.0.6

Kumar Gala

author

2010-12-17 23:50 UTC #15 lore raw

PATCH 9/15 powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe code

Remove duplicated code in TQM 85xx boards and utliize the common fsl_pcie_init_board().

Signed-off-by Kumar Gala <[email protected]>

CC wd at denx.de

---
 board/tqc/tqm85xx/law.c     |    9 +--------
 board/tqc/tqm85xx/tqm85xx.c |   41 ++++++++++++-----------------------------
 2 files changed, 13 insertions(+), 37 deletions(-)

board/tqc/tqm85xx/law.c +1 -8

index e684ba2..c596303 100644
@@ -67,20 +67,13 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-#ifdef CONFIG_PCIE1
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_BUS, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
-#else /* !CONFIG_PCIE1 */
+#ifndef CONFIG_PCIE1
 	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
 #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
 	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
-#ifdef CONFIG_PCIE1
-	SET_LAW(CONFIG_SYS_PCIE1_IO_BUS, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
-#endif /* CONFIG_PCIE */
 };
 
 int num_law_entries = ARRAY_SIZE (law_table);

board/tqc/tqm85xx/tqm85xx.c +12 ~~-29~~

72 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:49 UTC #16 lore raw

PATCH 9/15 powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in TQM 85xx boards and utliize the common fsl_pcie_init_board().
Signed-off-by Kumar Gala <[email protected]>
CC wd at denx.de
---
board/tqc/tqm85xx/law.c | 9 +--------
board/tqc/tqm85xx/tqm85xx.c | 41 ++++++++++++-----------------------------
2 files changed, 13 insertions(+), 37 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #17 lore raw

PATCH 10/15 powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8568MDS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8568mds/law.c        |    6 +---
 board/freescale/mpc8568mds/mpc8568mds.c |   52 +++++++++++--------------------
 2 files changed, 19 insertions(+), 39 deletions(-)

board/freescale/mpc8568mds/law.c +1 -5

index 3114e8a..e24b72b 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -50,10 +50,6 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),

board/freescale/mpc8568mds/mpc8568mds.c +18 ~~-34~~

94 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:49 UTC #18 lore raw

PATCH 10/15 powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in MPC8568MDS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8568mds/law.c | 6 +---
board/freescale/mpc8568mds/mpc8568mds.c | 52 +++++++++++--------------------
2 files changed, 19 insertions(+), 39 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #19 lore raw

PATCH 11/15 powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8569MDS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8569mds/law.c        |    4 +--
 board/freescale/mpc8569mds/mpc8569mds.c |   44 ++++--------------------------
 2 files changed, 7 insertions(+), 41 deletions(-)

board/freescale/mpc8569mds/law.c +1 -3

index 60eea45..bcd0311 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -51,8 +51,6 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };

board/freescale/mpc8569mds/mpc8569mds.c +6 ~~-38~~

57 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:49 UTC #20 lore raw

PATCH 11/15 powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in MPC8569MDS board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8569mds/law.c | 4 +--
board/freescale/mpc8569mds/mpc8569mds.c | 44 ++++--------------------------
2 files changed, 7 insertions(+), 41 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #21 lore raw

PATCH 12/15 powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in P1_P2_RDB boards and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/p1_p2_rdb/law.c |    6 +---
 board/freescale/p1_p2_rdb/pci.c |   64 +++++---------------------------------
 2 files changed, 10 insertions(+), 60 deletions(-)

board/freescale/p1_p2_rdb/law.c +1 -5

index 1320d5d..4c80fa6 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -26,10 +26,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };

board/freescale/p1_p2_rdb/pci.c +9 ~~-55~~

74 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:49 UTC #22 lore raw

PATCH 12/15 powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in P1_P2_RDB boards and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/p1_p2_rdb/law.c | 6 +---
board/freescale/p1_p2_rdb/pci.c | 64 +++++---------------------------------
2 files changed, 10 insertions(+), 60 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #23 lore raw

PATCH 13/15 powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8610HPCD board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

---
 board/freescale/mpc8610hpcd/law.c         |    8 +---
 board/freescale/mpc8610hpcd/mpc8610hpcd.c |   80 +++++++++--------------------
 2 files changed, 25 insertions(+), 63 deletions(-)

board/freescale/mpc8610hpcd/law.c +1 -7

index 0fc8384..26e41b6 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.

@@ -31,14 +31,8 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
 #endif
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8610hpcd/mpc8610hpcd.c +24 ~~-56~~

108 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:49 UTC #24 lore raw

PATCH 13/15 powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code

Quoted 9 lines · Kumar Gala

Remove duplicated code in MPC8610HPCD board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
---
board/freescale/mpc8610hpcd/law.c | 8 +---
board/freescale/mpc8610hpcd/mpc8610hpcd.c | 80 +++++++++--------------------
2 files changed, 25 insertions(+), 63 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #25 lore raw

PATCH 14/15 powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in SBC8641 board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

CC Paul Gortmaker <[email protected]>

---
 board/sbc8641d/law.c      |    4 ---
 board/sbc8641d/sbc8641d.c |   63 +-------------------------------------------
 2 files changed, 2 insertions(+), 65 deletions(-)

board/sbc8641d/law.c +0 -4

index 705e1c2..a6f60ee 100644
@@ -49,11 +49,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
 #endif
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };

board/sbc8641d/sbc8641d.c +2 ~~-61~~

72 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:49 UTC #26 lore raw

PATCH 14/15 powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code

Quoted 10 lines · Kumar Gala

Remove duplicated code in SBC8641 board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
CC Paul Gortmaker <[email protected]>
---
board/sbc8641d/law.c | 4 ---
board/sbc8641d/sbc8641d.c | 63 +-------------------------------------------
2 files changed, 2 insertions(+), 65 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Kumar Gala

author

2010-12-17 23:50 UTC #27 lore raw

PATCH 15/15 powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in SBC8548 board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.

Signed-off-by Kumar Gala <[email protected]>

CC Paul Gortmaker <[email protected]>

---
 board/sbc8548/law.c     |    8 -------
 board/sbc8548/sbc8548.c |   50 ++++++++++++----------------------------------
 2 files changed, 13 insertions(+), 45 deletions(-)

board/sbc8548/law.c +0 -8

index 6d1efc0..5fa9db0 100644
@@ -50,14 +50,6 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-#ifdef CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
-#endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };

board/sbc8548/sbc8548.c +13 ~~-37~~

76 lines not on this page · raw message

Signature · 1 line

1.6.0.6

Paul Gortmaker

2011-01-06 21:12 UTC #28 lore raw

PATCH 15/15 powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code

Quoted 6 lines · [[PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL…

Remove duplicated code in SBC8548 board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
CC Paul Gortmaker <[email protected]>

Tested-by Paul Gortmaker <[email protected]>

Tested with Peter's anti-NULL patch on top of the mpc85xx dev branch. Board has both PCI-X and PCI-e slots, with e1000 and skge respectively.

-----------------------

U-Boot 2010.12-00426-ged7ea8f (Jan 06 2011 - 15:43:08)

CPU:   8548E, Version: 2.0, (0x80390020)
Core:  E500, Version: 2.0, (0x80210020)
Clock Configuration:
       CPU0:990  MHz,
       CCB:396  MHz,
       DDR:198  MHz (396 MT/s data rate), LBC:99   MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: Wind River SBC8548 Rev. 0x2
I2C:   ready
DRAM:      SDRAM: 128 MiB
DDR: 256 MiB (DDR2, 64-bit, CL=4, ECC off)
       DDR Chip-Select Interleaving Mode: CS0+CS1
FLASH: 72 MiB
L2:    512 KB already enabled

*** Warning - bad CRC, using default environment

PCI: Host, 64 bit, 66 MHz, sync, arbiter
00:01.0 - 8086:1026 - Network controller
PCI1: Bus 00 - 00

PCIe1: Root Complex, x1, regs @ 0xe000a000
02:00.0 - 1148:9e00 - Network controller

PCIe1: Bus 01 - 02
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC0, eTSEC1
Hit any key to stop autoboot:  0

=> pci 0
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________

00.00.00   0x1057     0x0012     Processor               0x20
00.01.00   0x8086     0x1026     Network controller      0x00

=> pci 1
Scanning PCI devices on bus 1
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
01.00.00 0x1957 0x0012 Processor 0x20
=> pci 2
Scanning PCI devices on bus 2
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
02.00.00 0x1148 0x9e00 Network controller 0x00
=>

Kumar Gala

author Applied

2011-01-09 20:49 UTC #29 lore raw

PATCH 15/15 powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Quoted 10 lines · Kumar Gala

Remove duplicated code in SBC8548 board and utliize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by Kumar Gala <[email protected]>
CC Paul Gortmaker <[email protected]>
---
board/sbc8548/law.c | 8 -------
board/sbc8548/sbc8548.c | 50 ++++++++++++----------------------------------
2 files changed, 13 insertions(+), 45 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Peter Tyser

2010-12-20 16:49 UTC #30 lore raw

PATCH 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Thanks for the cleanup. What branch should this series be applied to? And are there prerequisites? I'm having issues applying them to test and review.

Quoted 2 lines · Kumar Gala

Remove duplicated code in MPC8572 DS board and utliize the common fsl_pcie_init_board().

Looks like a copy/paste from the MPC8572.

On all the patches in the series s/utliize/utilize/.

<snip>

board/xes/common/fsl_8xxx_pci.c line 36

Quoted 6 lines

board/xes/common/fsl_8xxx_pci.c +0 -0

@@ -34,15 +34,6 @@
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif

Is there a reason PCI1 wasn't changed over too? I see pci1_hose is still referenced below, but other boards with a PCI1 don't use similar code.

Quoted 9 lines

board/xes/common/fsl_8xxx_pci.c +0 -9

-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif

<snip>

Quoted 5 lines

board/xes/xpedite520x/law.c +0 -0
index bbfcb9d..3afb3ae 100644

board/xes/xpedite520x/law.c struct law_entry law_table[] = { · line 43

Quoted 10 lines

board/xes/xpedite520x/law.c +0 -4

@@ -38,10 +38,6 @@ struct law_entry law_table[] = {
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#if CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
-#endif
 #if CONFIG_SYS_PCI2_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),

The PCI2 law can be removed too. Its not currently used on any boards supported by mainline U-Boot.

Thanks,
Peter

Kumar Gala

author

2010-12-21 17:49 UTC #31 lore raw

PATCH 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

Quoted 5 lines · Peter Tyser

Thanks for the cleanup. What branch should this series be applied to? And are there prerequisites? I'm having issues applying them to test and review.
On Fri, 2010-12-17 at 17:50 -0600, Kumar Gala wrote:

Quoted 8 lines

Quoted 2 lines
Remove duplicated code in MPC8572 DS board and utliize the common fsl_pcie_init_board().
Looks like a copy/paste from the MPC8572.
On all the patches in the series s/utliize/utilize/.
<snip>

Will fix, oops ;)

Quoted 11 lines

board/xes/common/fsl_8xxx_pci.c line 36
Quoted 7 lines
board/xes/common/fsl_8xxx_pci.c +0 -0
@@ -34,15 +34,6 @@
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif
Is there a reason PCI1 wasn't changed over too? I see pci1_hose is still referenced below, but other boards with a PCI1 don't use similar code.

I was trying to limit how much clean up I did so left this to just PCIe interfaces. Normal PCI and PCI-X is something I might get around to but one thing at a time

Quoted 23 lines

Quoted 10 lines

board/xes/common/fsl_8xxx_pci.c +0 -9

-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif

<snip>

Quoted 10 lines

board/xes/xpedite520x/law.c +0 -2

index bbfcb9d..3afb3ae 100644
@@ -38,10 +38,6 @@ struct law_entry law_table[] = {
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#if CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),

Quoted 8 lines

board/xes/xpedite520x/law.c struct law_entry law_table[] = { · line 43
Quoted 5 lines
board/xes/xpedite520x/law.c +0 -2
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
-#endif
 #if CONFIG_SYS_PCI2_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
The PCI2 law can be removed too. Its not currently used on any boards supported by mainline U-Boot.

Ok, will remove in updated patch

- k

Peter Tyser

2010-12-21 20:23 UTC #32 lore raw

PATCH 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

Quoted 5 lines · Kumar Gala

Quoted 3 lines · Peter Tyser
Thanks for the cleanup. What branch should this series be applied to? And are there prerequisites? I'm having issues applying them to test and review.

Any direction on how these should be applied for testing?

<snip>

Quoted 11 lines

Quoted 10 lines
board/xes/common/fsl_8xxx_pci.c line 36
Quoted 6 lines
board/xes/common/fsl_8xxx_pci.c +0 -0
@@ -34,15 +34,6 @@
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif
Is there a reason PCI1 wasn't changed over too? I see pci1_hose is still referenced below, but other boards with a PCI1 don't use similar code.

Quoted 1 line

I was trying to limit how much clean up I did so left this to just PCIe interfaces. Normal PCI and PCI-X is something I might get around to but one thing at a time

Ah, OK. If we're removing the LAW entries for PCI1 in law.c below, how is a LAW being set for PCI1? It looks like PCIe laws are set in fsl_configure_pcie(), and PCI LAWs are set via set_next_law() in board-specific code? I'm not seeing the call to set_next_law() in X-ES board specific code after this change though.

Best,
Peter

Quoted 17 lines

<snip>

Quoted 15 lines

board/xes/xpedite520x/law.c +0 -4

index bbfcb9d..3afb3ae 100644
@@ -38,10 +38,6 @@ struct law_entry law_table[] = {
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#if CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
-#endif
 #if CONFIG_SYS_PCI2_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),

Kumar Gala

author

2010-12-23 18:30 UTC #33 lore raw

PATCH 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

Quoted 10 lines · Peter Tyser

Quoted 5 lines · Kumar Gala
Quoted 3 lines · Peter Tyser
Thanks for the cleanup. What branch should this series be applied to? And are there prerequisites? I'm having issues applying them to test and review.
Any direction on how these should be applied for testing?
<snip>

I've pushed a 'dev' branch on u-boot-85xx.git on denx.de with the current set of patches applied.

- k

Peter Tyser

2010-12-28 17:35 UTC #34 lore raw

PATCH 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

Quoted 6 lines

Quoted 4 lines
Any direction on how these should be applied for testing?
<snip>
I've pushed a 'dev' branch on u-boot-85xx.git on denx.de with the current set of patches applied.

Thanks. Things are much tidier now. I had a few comments. Let me know if you'd like me to submit patches to address any of them.

* There's a large chunk of defines that are no longer needed in the X-ES board code:

board/xes/common/fsl_8xxx_pci.c +0 ~~-23~~

@@ -35,29 +35,6 @@
 static struct pci_controller pci1_hose;
 #endif
 
-/*
- * 85xx and 86xx share naming conventions, but different layout.
- * Correlate names to CPU-specific values to share common
- * PCI code.
- */
-#if defined(CONFIG_MPC85xx)
-#define MPC8xxx_DEVDISR_PCIE1          MPC85xx_DEVDISR_PCIE
-#define MPC8xxx_DEVDISR_PCIE2          MPC85xx_DEVDISR_PCIE2
-#define MPC8xxx_DEVDISR_PCIE3          MPC85xx_DEVDISR_PCIE3
-#define MPC8xxx_PORDEVSR_IO_SEL                MPC85xx_PORDEVSR_IO_SEL
-#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT  MPC85xx_PORDEVSR_IO_SEL_SHIFT
-#define MPC8xxx_PORBMSR_HA             MPC85xx_PORBMSR_HA
-#define MPC8xxx_PORBMSR_HA_SHIFT       MPC85xx_PORBMSR_HA_SHIFT
-#elif defined(CONFIG_MPC86xx)
-#define MPC8xxx_DEVDISR_PCIE1          MPC86xx_DEVDISR_PCIEX1
-#define MPC8xxx_DEVDISR_PCIE2          MPC86xx_DEVDISR_PCIEX2
-#define MPC8xxx_DEVDISR_PCIE3          0       /* 8641 doesn't have PCIe3 */
-#define MPC8xxx_PORDEVSR_IO_SEL                MPC8641_PORDEVSR_IO_SEL
-#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT  MPC8641_PORDEVSR_IO_SEL_SHIFT
-#define MPC8xxx_PORBMSR_HA             MPC8641_PORBMSR_HA
-#define MPC8xxx_PORBMSR_HA_SHIFT       MPC8641_PORBMSR_HA_SHIFT
-#endif
-
 void pci_init_board(void)
 {
        int first_free_busno = 0;

* It'd be nice if boards didn't have to define board_serdes_name(), or at least a sane print statement was used if it wasn't. When I booted an X-ES board the first time I got:
PCIE1: connected to <NULL> as Endpoint (base addr ef008000)
PCIE1: Bus 00 - 00
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 01 - 01

Other boards will have the same issue. Something like the following?:

drivers/pci/fsl_pci_init.c +2 -2

@@ -526,8 +526,8 @@ int fsl_configure_pcie(struct fsl_pci_info *info,
        set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
        set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
        is_endpoint = fsl_setup_hose(hose, info->regs);
-       printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
-              info->pci_num, connected,
+       printf("PCIE%u: connected%s%s as %s (base addr %lx)\n",
+              info->pci_num, connected ? " to " : "", connected ? connected : "",
               is_endpoint ? "Endpoint" : "Root Complex", info->regs);
        return fsl_pci_init_port(info, hose, busno);
 }

* Lastly, what about using a new define to specify the PCIe port's name instead of making each board add a board_serdes_name() function? This reduces each board directory's clutter and makes it so all PCIe-related configuration and naming occurs in the board's config.h file. As an example that uses the xpedite517x and mpc8572ds:

board/freescale/mpc8572ds/mpc8572ds.c +0 ~~-11~~

@@ -149,17 +149,6 @@ phys_size_t fixed_sdram (void)
 #endif
 
 #ifdef CONFIG_PCI
-static const char *slot_names[] = {
-       [PCIE1] = "Slot 2",
-       [PCIE2] = "Slot 1",
-       [PCIE3] = "ULI",
-};
-
-const char *board_serdes_name(enum srds_prtcl device)
-{
-       return slot_names[device];
-}
-
 void pci_init_board(void)
 {
        struct pci_controller *hose;

drivers/pci/fsl_pci_init.c +20 -1

@@ -558,7 +558,26 @@ int fsl_configure_pcie(struct fsl_pci_info *info,
 /* Implement a dummy function for those platforms w/o SERDES */
 static const char *__board_serdes_name(enum srds_prtcl device)
 {
-       return NULL;
+       switch (device) {
+#ifdef CONFIG_SYS_PCIE1_NAME
+       case PCIE1:
+               return CONFIG_SYS_PCIE1_NAME;
+#endif
+#ifdef CONFIG_SYS_PCIE2_NAME
+       case PCIE2:
+               return CONFIG_SYS_PCIE2_NAME;
+#endif
+#ifdef CONFIG_SYS_PCIE3_NAME
+       case PCIE3:
+               return CONFIG_SYS_PCIE3_NAME;
+#endif
+#ifdef CONFIG_SYS_PCIE4_NAME
+       case PCIE4:
+               return CONFIG_SYS_PCIE4_NAME;
+#endif
+       default:
+               return NULL;
+       }
 }
 
 __attribute__((weak, alias("__board_serdes_name"))) const char *

include/configs/xpedite517x.h +2 -0

@@ -347,6 +347,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
+#define CONFIG_SYS_PCIE1_NAME          "PEX8518 Switch"
 
 /* PCIE2 - VPX P1 */
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000

@@ -355,6 +356,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe8800000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000      /* 8M */
+#define CONFIG_SYS_PCIE2_NAME          "VPX Fabric A"
 
 /*
  * Networking options

include/configs/MPC8572DS.h +3 -0

@@ -485,6 +485,7 @@
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xffc00000
 #endif
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE3_NAME          "ULI"
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000

@@ -504,6 +505,7 @@
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
 #endif
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE2_NAME          "Slot 1"
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000

@@ -523,6 +525,7 @@
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc20000
 #endif
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE1_NAME          "Slot 2"
 
 #if defined(CONFIG_PCI)

Best,
Peter

Kumar Gala

author

2011-01-09 20:54 UTC #35 lore raw

PATCH v2 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

In reply to Kumar Gala

Remove duplicated code in MPC8xxx XES boards and utilize the common fsl_pcie_init_board().

Signed-off-by Kumar Gala <[email protected]>

CC Peter Tyser <[email protected]>

---
* Fix commit message copy/paste issue per Peter T.
* Fixed utilize typo per Peter T.
* removed PCI2 on xpedite520x per Peter T.
* Removed duplicate/now unused MPC8xxx defines per Peter T.

 board/xes/common/fsl_8xxx_pci.c |  110 +++++----------------------------------
 board/xes/xpedite517x/law.c     |    8 ---
 board/xes/xpedite520x/law.c     |    8 ---
 board/xes/xpedite537x/law.c     |   12 ----
 board/xes/xpedite550x/law.c     |   12 ----
 5 files changed, 13 insertions(+), 137 deletions(-)

board/xes/common/fsl_8xxx_pci.c +13 ~~-97~~

index 4135849..28c83c7 100644
@@ -34,57 +34,16 @@
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
 #endif
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
-/*
- * 85xx and 86xx share naming conventions, but different layout.
- * Correlate names to CPU-specific values to share common
- * PCI code.
- */
-#if defined(CONFIG_MPC85xx)
-#define MPC8xxx_DEVDISR_PCIE1		MPC85xx_DEVDISR_PCIE
-#define MPC8xxx_DEVDISR_PCIE2		MPC85xx_DEVDISR_PCIE2
-#define MPC8xxx_DEVDISR_PCIE3		MPC85xx_DEVDISR_PCIE3
-#define MPC8xxx_PORDEVSR_IO_SEL		MPC85xx_PORDEVSR_IO_SEL
-#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT	MPC85xx_PORDEVSR_IO_SEL_SHIFT
-#define MPC8xxx_PORBMSR_HA		MPC85xx_PORBMSR_HA
-#define MPC8xxx_PORBMSR_HA_SHIFT	MPC85xx_PORBMSR_HA_SHIFT
-#elif defined(CONFIG_MPC86xx)
-#define MPC8xxx_DEVDISR_PCIE1		MPC86xx_DEVDISR_PCIEX1
-#define MPC8xxx_DEVDISR_PCIE2		MPC86xx_DEVDISR_PCIEX2
-#define MPC8xxx_DEVDISR_PCIE3	 	0	/* 8641 doesn't have PCIe3 */
-#define MPC8xxx_PORDEVSR_IO_SEL		MPC8641_PORDEVSR_IO_SEL
-#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT	MPC8641_PORDEVSR_IO_SEL_SHIFT
-#define MPC8xxx_PORBMSR_HA		MPC8641_PORBMSR_HA
-#define MPC8xxx_PORBMSR_HA_SHIFT	MPC8641_PORBMSR_HA_SHIFT
-#endif
 
 void pci_init_board(void)
 {
-	struct fsl_pci_info pci_info[3];
 	int first_free_busno = 0;
-	int num = 0;
-	int pcie_ep;
-	__maybe_unused int pcie_configured;
 
-#if defined(CONFIG_MPC85xx)
+#ifdef CONFIG_PCI1
+	int pcie_ep;
+	struct fsl_pci_info pci_info;
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#elif defined(CONFIG_MPC86xx)
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-#endif
 	u32 devdisr = in_be32(&gur->devdisr);
-
-#ifdef CONFIG_PCI1
-	u32 pordevsr = in_be32(&gur->pordevsr);
 	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
 	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
 	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;

@@ -92,8 +51,13 @@ void pci_init_board(void)
 	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
 			pci_32 ? 32 : 64,
 			pcix ? "PCIX" : "PCI",

@@ -102,66 +66,18 @@ void pci_init_board(void)
 			pcie_ep ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter");
 
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI1: disabled\n");
 	}
 #elif defined CONFIG_MPC8548
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	/* PCI1 not present on MPC8572 */
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
 #endif
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
-#endif /* CONFIG_PCIE1 */
-
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
-#endif /* CONFIG_PCIE2 */
-
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-		printf("PCIE3: connected as %s\n",
-			pcie_ep ? "Endpoint" : "Root Complex");
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
-#endif /* CONFIG_PCIE3 */
+	fsl_pcie_init_board(first_free_busno);
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)

board/xes/xpedite517x/law.c +0 -8

index 0b7d9ef..df23df1 100644
@@ -39,14 +39,6 @@ struct law_entry law_table[] = {
 	/* NAND LAW covers 2 NAND flashes */
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
 #endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/xes/xpedite520x/law.c +0 -8

index bbfcb9d..5c1fcd2 100644
@@ -38,14 +38,6 @@ struct law_entry law_table[] = {
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#if CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
-#endif
-#if CONFIG_SYS_PCI2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/xes/xpedite537x/law.c +0 ~~-12~~

index daee676..54c28da 100644
@@ -37,18 +37,6 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/xes/xpedite550x/law.c +0 ~~-12~~

index 4d4445d..66f1cf9 100644
@@ -37,18 +37,6 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
-#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
-#endif
-#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

Signature · 1 line

1.6.0.6

Kumar Gala

author Applied

2011-01-09 20:55 UTC #36 lore raw

PATCH v2 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

Quoted 11 lines · Kumar Gala

Remove duplicated code in MPC8xxx XES boards and utilize the common fsl_pcie_init_board().
Signed-off-by Kumar Gala <[email protected]>
CC Peter Tyser <[email protected]>
---
* Fix commit message copy/paste issue per Peter T.
* Fixed utilize typo per Peter T.
* removed PCI2 on xpedite520x per Peter T.
* Removed duplicate/now unused MPC8xxx defines per Peter T.

Quoted 6 lines

board/xes/common/fsl_8xxx_pci.c |  110 +++++----------------------------------
board/xes/xpedite517x/law.c     |    8 ---
board/xes/xpedite520x/law.c     |    8 ---
board/xes/xpedite537x/law.c     |   12 ----
board/xes/xpedite550x/law.c     |   12 ----
5 files changed, 13 insertions(+), 137 deletions(-)

applied to 85xx

- k

Kumar Gala

author

2010-12-23 18:35 UTC #37 lore raw

PATCH 8/15 powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

In reply to Peter Tyser

Quoted 9 lines · Peter Tyser

Ah, OK. If we're removing the LAW entries for PCI1 in law.c below, how is a LAW being set for PCI1? It looks like PCIe laws are set in fsl_configure_pcie(), and PCI LAWs are set via set_next_law() in board-specific code? I'm not seeing the call to set_next_law() in X-ES board specific code after this change though.
Best,
Peter

Yep, that was missing, will fix ;)

- k