amd iommu: Fix output and coding style
PATCH 1/1 amd iommu: Fix output and coding style
Keir,
This patch fixes a few debug output format and coding style issues, it also fixes a typo in iommu page fault handling. Other than that it should not break anything, please add it into 4.1.
Thanks,
Wei
Signed-off-by Wei Wang <[email protected]>
--
Advanced Micro Devices GmbH
Sitz: Dornach, Gemeinde Aschheim,
Landkreis München Registergericht München,
HRB Nr. 43632
WEEE-Reg-Nr: DE 12919551
Geschäftsführer:
Alberto Bozzo, Andrew Bowd
xen/drivers/passthrough/amd/iommu_acpi.c +28 -29
@@ -289,16 +289,16 @@ static int __init parse_ivmd_device_rang first_bdf = ivmd_block->header.dev_id;if ( first_bdf >= ivrs_bdf_entries ) { -AMD_IOMMU_DEBUG ( -"IVMD Error: Invalid Range_First Dev_Id 0x%x\n" , first_bdf); +AMD_IOMMU_DEBUG ("IVMD Error: " +"Invalid Range_First Dev_Id 0x%x\n" , first_bdf);return -ENODEV ; } last_bdf = ivmd_block->last_dev_id;if ( (last_bdf >= ivrs_bdf_entries) || (last_bdf <= first_bdf) ) { -AMD_IOMMU_DEBUG ( -"IVMD Error: Invalid Range_Last Dev_Id 0x%x\n" , last_bdf); +AMD_IOMMU_DEBUG ("IVMD Error: " +"Invalid Range_Last Dev_Id 0x%x\n" , last_bdf);return -ENODEV ; }
@@ -321,7 +321,7 @@ static int __init parse_ivmd_device_iommif ( !iommu ) {AMD_IOMMU_DEBUG ("IVMD Error: No IOMMU for Dev_Id 0x%x Cap 0x%x\n" , - ivmd_block->header.dev_id, ivmd_block->cap_offset); + ivmd_block->header.dev_id, ivmd_block->cap_offset);return -ENODEV ; }
@@ -441,24 +441,24 @@ static u16 __init parse_ivhd_device_rang AMD_IOMMU_ACPI_IVHD_DEV_RANGE_END ) {AMD_IOMMU_DEBUG ("IVHD Error: " -"Invalid Range: End_Type 0x%x\n" , - ivhd_device->range.trailer.type); +"Invalid Range: End_Type 0x%x\n" , + ivhd_device->range.trailer.type);return 0 ; } first_bdf = ivhd_device->header.dev_id;if ( first_bdf >= ivrs_bdf_entries ) { -AMD_IOMMU_DEBUG ( -"IVHD Error: Invalid Range: First Dev_Id 0x%x\n" , first_bdf); +AMD_IOMMU_DEBUG ("IVHD Error: " +"Invalid Range: First Dev_Id 0x%x\n" , first_bdf);return 0 ; } last_bdf = ivhd_device->range.trailer.dev_id;if ( (last_bdf >= ivrs_bdf_entries) || (last_bdf <= first_bdf) ) { -AMD_IOMMU_DEBUG ( -"IVHD Error: Invalid Range: Last Dev_Id 0x%x\n" , last_bdf); +AMD_IOMMU_DEBUG ("IVHD Error: " +"Invalid Range: Last Dev_Id 0x%x\n" , last_bdf);return 0 ; }
@@ -522,16 +522,16 @@ static u16 __init parse_ivhd_device_alia AMD_IOMMU_ACPI_IVHD_DEV_RANGE_END ) {AMD_IOMMU_DEBUG ("IVHD Error: " -"Invalid Range: End_Type 0x%x\n" , - ivhd_device->alias_range.trailer.type); +"Invalid Range: End_Type 0x%x\n" , + ivhd_device->alias_range.trailer.type);return 0 ; } first_bdf = ivhd_device->header.dev_id;if ( first_bdf >= ivrs_bdf_entries ) { -AMD_IOMMU_DEBUG ( -"IVHD Error: Invalid Range: First Dev_Id 0x%x\n" , first_bdf); +AMD_IOMMU_DEBUG ("IVHD Error: " +"Invalid Range: First Dev_Id 0x%x\n" , first_bdf);return 0 ; }
@@ -601,29 +601,29 @@ static u16 __init parse_ivhd_device_exte AMD_IOMMU_ACPI_IVHD_DEV_RANGE_END ) {AMD_IOMMU_DEBUG ("IVHD Error: " -"Invalid Range: End_Type 0x%x\n" , - ivhd_device->extended_range.trailer.type); +"Invalid Range: End_Type 0x%x\n" , + ivhd_device->extended_range.trailer.type);return 0 ; } first_bdf = ivhd_device->header.dev_id;if ( first_bdf >= ivrs_bdf_entries ) { -AMD_IOMMU_DEBUG ( -"IVHD Error: Invalid Range: First Dev_Id 0x%x\n" , first_bdf); +AMD_IOMMU_DEBUG ("IVHD Error: " +"Invalid Range: First Dev_Id 0x%x\n" , first_bdf);return 0 ; } last_bdf = ivhd_device->extended_range.trailer.dev_id;if ( (last_bdf >= ivrs_bdf_entries) || (last_bdf <= first_bdf) ) { -AMD_IOMMU_DEBUG ( -"IVHD Error: Invalid Range: Last Dev_Id 0x%x\n" , last_bdf); +AMD_IOMMU_DEBUG ("IVHD Error: " +"Invalid Range: Last Dev_Id 0x%x\n" , last_bdf);return 0 ; }AMD_IOMMU_DEBUG (" Dev_Id Range: 0x%x -> 0x%x\n" , - first_bdf, last_bdf); + first_bdf, last_bdf);for ( bdf = first_bdf; bdf <= last_bdf; bdf++ )add_ivrs_mapping_entry (bdf, bdf, ivhd_device->header.flags, iommu);
@@ -675,7 +675,7 @@ static int __init parse_ivhd_block(strucif ( !iommu ) {AMD_IOMMU_DEBUG ("IVHD Error: No IOMMU for Dev_Id 0x%x Cap 0x%x\n" , - ivhd_block->header.dev_id, ivhd_block->cap_offset); + ivhd_block->header.dev_id, ivhd_block->cap_offset);return -ENODEV ; }
@@ -809,7 +809,7 @@ static void __init dump_acpi_table_headeprintk ("\n" );AMD_IOMMU_DEBUG (" Creator_Revision 0x%x\n" , - table->asl_compiler_revision); + table->asl_compiler_revision); }
@@ -841,9 +841,9 @@ static int __init parse_ivrs_table(strucif ( table->length < (length + ivrs_block->length) ) {AMD_IOMMU_DEBUG ("IVRS Error: " -"Table Length Exceeded: 0x%x -> 0x%lx\n" , - table->length, - (length + ivrs_block->length)); +"Table Length Exceeded: 0x%x -> 0x%lx\n" , + table->length, + (length + ivrs_block->length));return -ENODEV ; }
@@ -869,8 +869,7 @@ static int __init detect_iommu_acpi(stru checksum += raw_table[i];if ( checksum ) { -AMD_IOMMU_DEBUG ("IVRS Error: " -"Invalid Checksum 0x%x\n" , checksum); +AMD_IOMMU_DEBUG ("IVRS Error: Invalid Checksum 0x%x\n" , checksum);return -ENODEV ; }
xen/drivers/passthrough/amd/iommu_init.c +14 -11
@@ -324,7 +324,7 @@ static void amd_iommu_reset_event_log(stif ( log_run ) {AMD_IOMMU_DEBUG ("Warning: EventLogRun bit is not cleared" -"before reset!\n" ); +"before reset!\n" );return ; }
@@ -357,7 +357,9 @@ static void iommu_msi_set_affinity(unsigu8 func =PCI_FUNC (iommu->bdf &0xff ); dest =set_desc_affinity (desc, &mask); -if (dest ==BAD_APICID ){ + +if ( dest ==BAD_APICID ) + {dprintk (XENLOG_ERR ,"Set iommu interrupt affinity error!\n" );return ; }
@@ -448,7 +450,7 @@ static void iommu_msi_end(unsigned int istatic hw_irq_controller iommu_msi_type = { - .typename ="AMD_IOV_MSI" , + .typename ="AMD-IOMMU-MSI" , .startup = iommu_msi_startup, .shutdown = iommu_msi_mask, .enable = iommu_msi_unmask,
@@ -464,7 +466,7 @@ static void parse_event_log_entry(u32 enu32 code;u64 *addr;char * event_str[] = {"ILLEGAL_DEV_TABLE_ENTRY" , -"IO_PAGE_FALT" , +"IO_PAGE_FAULT" ,"DEV_TABLE_HW_ERROR" ,"PAGE_TABLE_HW_ERROR" ,"ILLEGAL_COMMAND_ERROR" ,
@@ -482,7 +484,7 @@ static void parse_event_log_entry(u32 enreturn ; } -if ( code ==IOMMU_EVENT_IO_PAGE_FALT ) +if ( code ==IOMMU_EVENT_IO_PAGE_FAULT ) { device_id = get_field_from_reg_u32(entry[0], IOMMU_EVENT_DEVICE_ID_MASK,
@@ -491,9 +493,10 @@ static void parse_event_log_entry(u32 enIOMMU_EVENT_DOMAIN_ID_MASK , IOMMU_EVENT_DOMAIN_ID_SHIFT); addr= (u64 *) (entry +2 ); -printk (XENLOG_ERR "AMD_IOV: " -"%s: domain:%d, device id:0x%x, fault address:0x%" PRIx64"\n" , - event_str[code-1 ], domain_id, device_id, *addr); +printk (XENLOG_ERR "AMD-Vi: " +"%s: domain = %d, device id = 0x%04x, " +"fault address = 0x%" PRIx64"\n" , + event_str[code-1 ], domain_id, device_id, *addr); }else {
@@ -810,9 +813,9 @@ static int __init amd_iommu_setup_deviceamd_iommu_set_intremap_table ( dte, (u64 )virt_to_maddr (intr_tb), iommu_intremap); -AMD_IOMMU_DEBUG ("Add device table entry at DTE:0x%x, " -"intremap_table:%" PRIx64"\n" , bdf, - (u64 )virt_to_maddr (intr_tb)); +AMD_IOMMU_DEBUG ("Add device table entry: device id = 0x%04x, " +"interupt table = 0x%" PRIx64"\n" , bdf, + (u64 )virt_to_maddr (intr_tb)); } }
xen/drivers/passthrough/amd/iommu_intr.c +6 -7
@@ -183,8 +183,8 @@ int __init amd_iommu_setup_ioapic_remapp iommu =find_iommu_for_device (bdf);if ( !iommu ) { -AMD_IOMMU_DEBUG ( -"Fail to find iommu for ioapic device id = 0x%x\n" , bdf); +AMD_IOMMU_DEBUG ("Fail to find iommu for ioapic " +"device id = 0x%x\n" , bdf);continue ; }
@@ -233,8 +233,8 @@ void amd_iommu_ioapic_update_ire( iommu =find_iommu_for_device (bdf);if ( !iommu ) { -AMD_IOMMU_DEBUG ( -"Fail to find iommu for ioapic device id = 0x%x\n" , bdf); +AMD_IOMMU_DEBUG ("Fail to find iommu for ioapic device id = 0x%x\n" , + bdf);return ; }if ( rte_upper )
@@ -350,9 +350,8 @@ void amd_iommu_msi_msg_update_ire(if ( !iommu ) { -AMD_IOMMU_DEBUG ( -"Fail to find iommu for MSI device id = 0x%x\n" , - (pdev->bus <<8 ) | pdev->devfn); +AMD_IOMMU_DEBUG ("Fail to find iommu for MSI device id = 0x%x\n" , + (pdev->bus <<8 ) | pdev->devfn);return ; }
xen/drivers/passthrough/amd/iommu_map.c +1 -1
@@ -535,7 +535,7 @@ int amd_iommu_reserve_domain_unity_map( {spin_unlock (&hd->mapping_lock);AMD_IOMMU_DEBUG ("Invalid IO pagetable entry phys_addr = %lx\n" , - phys_addr); + phys_addr);domain_crash (domain);return -EFAULT ; }
xen/drivers/passthrough/amd/pci_amd_iommu.c +22 -19
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xen/include/asm-x86/hvm/svm/amd-iommu-defs.h +1 -1
@@ -256,7 +256,7 @@#define IOMMU_EVENT_CODE_MASK 0xF0000000#define IOMMU_EVENT_CODE_SHIFT 28#define IOMMU_EVENT_ILLEGAL_DEV_TABLE_ENTRY 0x1 -#define IOMMU_EVENT_IO_PAGE_FALT 0x2 +#define IOMMU_EVENT_IO_PAGE_FAULT 0x2#define IOMMU_EVENT_DEV_TABLE_HW_ERROR 0x3#define IOMMU_EVENT_PAGE_TABLE_HW_ERROR 0x4#define IOMMU_EVENT_ILLEGAL_COMMAND_ERROR 0x5
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