ppc4xx: Add DLVision-10G board support

index 2e218de..a33ca2f 100644
@@ -172,6 +172,9 @@ typedef	struct	global_data {
 #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
 	unsigned long kbd_status;
 #endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
+#endif
 #if defined(CONFIG_WD_MAX_RATE)
 	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
 #endif

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index 80877b6..0974019 100644
@@ -29,7 +29,7 @@
 
 #include <miiphy.h>
 
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
 
 #define PHYREG_CONTROL				0
 #define PHYREG_PAGE_ADDRESS			22

@@ -37,13 +37,6 @@
 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
 
 enum {
-	REG_VERSIONS = 0x0002,
-	REG_FPGA_FEATURES = 0x0004,
-	REG_FPGA_VERSION = 0x0006,
-	REG_QUAD_SERDES_RESET = 0x0012,
-};
-
-enum {
 	UNITTYPE_CCD_SWITCH = 1,
 };
 

@@ -94,10 +87,11 @@ err_out:
  */
 int checkboard(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_channels;

@@ -166,6 +160,7 @@ int checkboard(void)
  */
 int last_stage_init(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	unsigned int k;
 
 	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,

@@ -175,7 +170,7 @@ int last_stage_init(void)
 		configure_gbit_phy(k);
 
 	/* take fpga serdes blocks out of reset */
-	fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+	out_le16(&fpga->quad_serdes_reset, 0);
 
 	return 0;
 }

index ecd6cb2..20770e4 100644
@@ -27,14 +27,9 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
-#include "../common/fpga.h"
-#include "../common/osd.h"
+#include <gdsys_fpga.h>
 
-enum {
-	REG_VERSIONS = 0x0002,
-	REG_FPGA_VERSION = 0x0004,
-	REG_FPGA_FEATURES = 0x0006,
-};
+#include "../common/osd.h"
 
 enum {
 	UNITTYPE_MAIN_SERVER = 0,

@@ -74,10 +69,11 @@ enum {
  */
 int checkboard(void)
 {
+	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_compression;

@@ -214,7 +210,7 @@ int checkboard(void)
 
 int last_stage_init(void)
 {
-	return osd_probe();
+	return osd_probe(0);
 }
 
 /*

@@ -222,15 +218,15 @@ int last_stage_init(void)
  */
 void fpga_gpio_set(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
 }
 
 void fpga_gpio_clear(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
 }
 
 int fpga_gpio_get(int pin)
 {
-	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+	return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 }

deleted file mode 100644
index c1434e7..0000000
@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach at gdsys.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _FPGA_H_
-#define _FPGA_H_
-
-static inline u16 fpga_get_reg(unsigned reg)
-{
-	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
-}
-
-static inline void fpga_set_reg(unsigned reg, u16 val)
-{
-	return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
-}
-
-#endif

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index 4431cbc..c59d9c3 100644
@@ -24,6 +24,6 @@
 #ifndef _OSD_H_
 #define _OSD_H_
 
-int osd_probe(void);
+int osd_probe(unsigned screen);
 
 #endif

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index a66c704..9d2a87d 100644
@@ -229,13 +229,15 @@
 #define CONFIG_SYS_EBC_PB1CR		0x7f318000
 
 /* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02025080
 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 #define CONFIG_SYS_EBC_PB2CR		0x7f11a000
 
-#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH	0x3ffe
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
+
+#define CONFIG_SYS_FPGA_COUNT		1
 
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000

index 5e61b11..9fcc643 100644
@@ -131,6 +131,12 @@ int fpga_gpio_get(int pin);
 #define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
 
 /*
+ * OSD hardware
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+
+/*
  * FLASH organization
  */
 #define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/

@@ -231,13 +237,15 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_EBC_PB1AP		0x92015480
 #define CONFIG_SYS_EBC_PB1CR		0xFB858000
 
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+/* Memory Bank 2 (FPGA0) initialization */
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02825080
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x1a000)
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA0_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
 
-#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH	0x00fe
+#define CONFIG_SYS_FPGA_COUNT		1
 
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000

@@ -249,4 +257,11 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_LATCH1_RESET		0xffff
 #define CONFIG_SYS_LATCH1_BOOT		0xffff
 
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
+
 #endif	/* __CONFIG_H */

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