ARM: imx53: correct Silicon Revision definition following fuse map
Subsystems (2)
PATCH 1/1 ARM: imx53: correct Silicon Revision definition following fuse map
Signed-off-by Richard Zhao <[email protected]>
arch/arm/mach-mx5/cpu.c +18 -6
@@ -76,13 +76,25 @@ late_initcall(mx51_neon_fixup);static int get_mx53_srev (void ) {void __iomem *iim_base =MX51_IO_ADDRESS (MX53_IIM_BASE_ADDR ); -u32 rev =readl (iim_base +IIM_SREV ) &0xff ; +u32 reg =readl (iim_base +IIM_SREV ) &0xff ; +int rev; + +switch (reg) { +case 0x0 : + rev =IMX_CHIP_REVISION_1_0 ; +break ; +case 0x2 : + rev =IMX_CHIP_REVISION_2_0 ; +break ; +case 0x3 : + rev =IMX_CHIP_REVISION_2_1 ; +break ; +default : + rev =IMX_CHIP_REVISION_UNKNOWN ; +break ; + } -if (rev ==0x0 ) -return IMX_CHIP_REVISION_1_0 ; -else if (rev ==0x10 ) -return IMX_CHIP_REVISION_2_0 ; -return 0 ; +return rev; }/*
Signature · 1 line
1.7.1
PATCH 1/1 ARM: imx53: correct Silicon Revision definition following fuse map
Hi Richard,
Quoted 28 lines · Richard Zhao
Signed-off-by Richard Zhao <[email protected]>arch/arm/mach-mx5/cpu.c +17
-1@@ -76,13 +76,25 @@ late_initcall(mx51_neon_fixup);static int get_mx53_srev (void ) {void __iomem *iim_base =MX51_IO_ADDRESS (MX53_IIM_BASE_ADDR ); -u32 rev =readl (iim_base +IIM_SREV ) &0xff ; +u32 reg =readl (iim_base +IIM_SREV ) &0xff ; +int rev; + +switch (reg) { +case 0x0 : + rev =IMX_CHIP_REVISION_1_0 ; +break ; +case 0x2 : + rev =IMX_CHIP_REVISION_2_0 ; +break ; +case 0x3 : + rev =IMX_CHIP_REVISION_2_1 ; +break ; +default : + rev =IMX_CHIP_REVISION_UNKNOWN ; +break ; + }
arch/arm/mach-mx5/cpu.c late_initcall(mx51_neon_fixup); · line 100
Quoted 10 lines
arch/arm/mach-mx5/cpu.c +1
-5-if (rev ==0x0 ) -return IMX_CHIP_REVISION_1_0 ; -else if (rev ==0x10 ) -return IMX_CHIP_REVISION_2_0 ; -return 0 ; +return rev; }/*
I think the following code is shorter and more readable:
switch (reg) {
case 0x0:
return IMX_CHIP_REVISION_1_0;
case 0x2:
return IMX_CHIP_REVISION_2_0;
case 0x3:
return IMX_CHIP_REVISION_2_1;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}baruch
Signature · 3 lines
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -PATCH 1/1 ARM: imx53: correct Silicon Revision definition following fuse map
Hi Baruch,
Quoted 46 lines · Baruch Siach
Hi Richard,
Quoted 28 lines · Richard Zhao
Signed-off-by Richard Zhao <[email protected]>arch/arm/mach-mx5/cpu.c +17
-1@@ -76,13 +76,25 @@ late_initcall(mx51_neon_fixup);static int get_mx53_srev (void ) {void __iomem *iim_base =MX51_IO_ADDRESS (MX53_IIM_BASE_ADDR ); -u32 rev =readl (iim_base +IIM_SREV ) &0xff ; +u32 reg =readl (iim_base +IIM_SREV ) &0xff ; +int rev; + +switch (reg) { +case 0x0 : + rev =IMX_CHIP_REVISION_1_0 ; +break ; +case 0x2 : + rev =IMX_CHIP_REVISION_2_0 ; +break ; +case 0x3 : + rev =IMX_CHIP_REVISION_2_1 ; +break ; +default : + rev =IMX_CHIP_REVISION_UNKNOWN ; +break ; + }arch/arm/mach-mx5/cpu.c late_initcall(mx51_neon_fixup); · line 100
Quoted 10 lines
arch/arm/mach-mx5/cpu.c +1
-5-if (rev ==0x0 ) -return IMX_CHIP_REVISION_1_0 ; -else if (rev ==0x10 ) -return IMX_CHIP_REVISION_2_0 ; -return 0 ; +return rev; }/* I think the following code is shorter and more readable:
switch (reg) {
case0x0:
Quoted 8 lines
return IMX_CHIP_REVISION_1_0;
case 0x2:
return IMX_CHIP_REVISION_2_0;
case 0x3:
return IMX_CHIP_REVISION_2_1;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}Yes. I thought there would be compile warning, but not.
Thanks
Richard
Quoted 9 lines
baruch
Signature · 3 lines
~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -