Support for Netlogic XLR/XLS processors

PATCH In review Jayachandran C. 3 participants 5 messages Mar 12, 2011 – Mar 18, 2011 MIPS

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Jayachandran C.

author

2011-03-12 18:23 UTC #0 lore raw

PATCH 1/1 Support for Netlogic XLR/XLS processors

I would like to start the process of contributing support for Netlogic XLR/XLS and XLP processors into linux mips. Our linux code is currently maintained internally as a Software Development Kit distributed to customers, and the plan is to move to a more open model for Linux development. As part of this, I would like to extract relevant parts of the SDK, clean it up, re-base t and submit for inclusion in the linux-mips tree.

This is the very first (and self contained) patch), which adds basic support for Netlogic XLR and XLS processors. If all goes well, I would like to follow it up with patches for XLP processors, and patches for device support for both XLR/XLS and XLP processors.

The attached patch adds Netlogic XLR CPU support, support for platform UART, PIC, and SMP support. The code is licensed with a 2-clause BSD license which should be compatible with GPL2.

Please let me know your comments, the patches can be split up further if needed, and any comments on code, coding style oj better ways of implementation are welcome.

Even thought just the netlogic/xlr directory is present now, we will be adding a netlogic/xlp directory when the XLP processor support is added.

Regards,
JC.

Signature · 3 lines

Jayachandran C.
[email protected]              (Netlogic Processors India)
[email protected]                               (The FreeBSD Project)

Support for Netlogic XLR and XLS processors.

Add support for XLR and XLS families of multi-core MIPS64 SoCs from Netlogic Microsystems. The changes are:
* support for XLR/XLS in the kernel config and build
* support for XLR and XLS cpu types in MIPS cpu probe.
* XLR/XLS cache support with mm/c-netlogic.c.
* Platform UART and early printk support
* IRQs with XLR/XLS PIC
* SMP support for upto 32 processors (8 cores, 4 threads per core).

These changes enable us to boot linux-mips on Netlogic evaluation boards from the netlogic bootloader.

Signed-off-by Jayachandran C. <[email protected]>

arch/mips/Kconfig +42 -0

index d889835..a955ced 100644
@@ -735,6 +735,33 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
 		Hikari
 	  Say Y here for most Octeon reference boards.
 
+config NLM_XLR_BOARD
+	bool "Netlogic XLR/XLS based systems"
+	depends on EXPERIMENTAL
+	select BOOT_ELF32
+	select NLM_COMMON
+	select NLM_XLR
+	select SYS_HAS_CPU_XLR
+	select SYS_SUPPORTS_SMP
+	select HW_HAS_PCI
+	select SWAP_IO_SPACE
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select 64BIT_PHYS_ADDR
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select DMA_COHERENT
+	select NR_CPUS_DEFAULT_32
+	select CEVT_R4K
+	select CSRC_R4K
+	select IRQ_CPU
+	select ZONE_DMA if 64BIT
+	select SYNC_R4K
+	select SYS_HAS_EARLY_PRINTK
+	help
+	  Support for systems based on Netlogic XLR and XLS processors.
+	  Say Y here if you have a XLR or XLS based board.
+
 endchoice
 
 source "arch/mips/alchemy/Kconfig"

@@ -751,6 +778,7 @@ source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
 source "arch/mips/cavium-octeon/Kconfig"
 source "arch/mips/loongson/Kconfig"
+source "arch/mips/netlogic/Kconfig"
 
 endmenu

@@ -1417,6 +1445,17 @@ config CPU_BMIPS5000
 	help
 	  Broadcom BMIPS5000 processors.
 
+config CPU_XLR
+	bool "Netlogic XLR SoC"
+	depends on SYS_HAS_CPU_XLR
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select CPU_SUPPORTS_64BIT_KERNEL
+	select CPU_SUPPORTS_HIGHMEM
+	select WEAK_ORDERING
+	select WEAK_REORDERING_BEYOND_LLSC
+	select CPU_SUPPORTS_HUGEPAGES
+	help
+	  Netlogic Microsystems XLR/XLS processors.
 endchoice
 
 if CPU_LOONGSON2F

@@ -1547,6 +1586,9 @@ config SYS_HAS_CPU_BMIPS4380
 config SYS_HAS_CPU_BMIPS5000
 	bool
 
+config SYS_HAS_CPU_XLR
+	bool
+
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC

arch/mips/Makefile +12 -0

index 7c1102e..63182c9 100644
@@ -191,6 +191,18 @@ endif
 #
 include $(srctree)/arch/mips/Kbuild.platforms
 
+#
+# NETLOGIC SOC Common (common)
+#
+cflags-$(CONFIG_NLM_COMMON)		+= -I$(srctree)/arch/mips/include/asm/mach-netlogic
+cflags-$(CONFIG_NLM_COMMON)		+= -I$(srctree)/arch/mips/include/asm/netlogic
+
+#
+# NETLOGIC XLR/XLS SoC, Simulator and boards
+#
+core-$(CONFIG_NLM_XLR)      		+= arch/mips/netlogic/xlr/
+load-$(CONFIG_NLM_XLR_BOARD)		+= 0xffffffff84000000
+
 cflags-y			+= -I$(srctree)/arch/mips/include/asm/mach-generic
 drivers-$(CONFIG_PCI)		+= arch/mips/pci/

arch/mips/configs/nlm_xlr_defconfig new file +1700 -0

1,700 lines not on this page · raw message

arch/mips/include/asm/cpu-features.h +3 -0

index ca400f7..bbf8f35 100644
@@ -41,6 +41,9 @@
 #ifndef cpu_has_octeon_cache
 #define cpu_has_octeon_cache	0
 #endif
+#ifndef cpu_has_netlogic_cache
+#define cpu_has_netlogic_cache	0
+#endif
 #ifndef cpu_has_fpu
 #define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
 #define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)

arch/mips/include/asm/cpu.h +27 -0

index 8687753..34c0d3c 100644
@@ -33,6 +33,7 @@
 #define PRID_COMP_TOSHIBA	0x070000
 #define PRID_COMP_LSI		0x080000
 #define PRID_COMP_LEXRA		0x0b0000
+#define PRID_COMP_NETLOGIC	0x0c0000
 #define PRID_COMP_CAVIUM	0x0d0000
 #define PRID_COMP_INGENIC	0xd00000

@@ -142,6 +143,31 @@
 #define PRID_IMP_JZRISC        0x0200
 
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
+ */
+#define PRID_IMP_NETLOGIC_XLR732	0x0000
+#define PRID_IMP_NETLOGIC_XLR716	0x0200
+#define PRID_IMP_NETLOGIC_XLR532	0x0900
+#define PRID_IMP_NETLOGIC_XLR308	0x0600
+#define PRID_IMP_NETLOGIC_XLR532C	0x0800
+#define PRID_IMP_NETLOGIC_XLR516C	0x0a00
+#define PRID_IMP_NETLOGIC_XLR508C	0x0b00
+#define PRID_IMP_NETLOGIC_XLR308C	0x0f00
+#define PRID_IMP_NETLOGIC_XLS608	0x8000
+#define PRID_IMP_NETLOGIC_XLS408	0x8800
+#define PRID_IMP_NETLOGIC_XLS404	0x8c00
+#define PRID_IMP_NETLOGIC_XLS208	0x8e00
+#define PRID_IMP_NETLOGIC_XLS204	0x8f00
+#define PRID_IMP_NETLOGIC_XLS108	0xce00
+#define PRID_IMP_NETLOGIC_XLS104	0xcf00
+#define PRID_IMP_NETLOGIC_XLS616B	0x4000
+#define PRID_IMP_NETLOGIC_XLS608B	0x4a00
+#define PRID_IMP_NETLOGIC_XLS416B	0x4400
+#define PRID_IMP_NETLOGIC_XLS412B	0x4c00
+#define PRID_IMP_NETLOGIC_XLS408B	0x4e00
+#define PRID_IMP_NETLOGIC_XLS404B	0x4f00
+
+/*
  * Definitions for 7:0 on legacy processors
  */

@@ -234,6 +260,7 @@ enum cpu_type_enum {
 	 */
 	CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
 	CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
+	CPU_XLR,
 
 	CPU_LAST
 };

arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h new file +9 -0

new file mode 100644
index 0000000..7740401
@@ -0,0 +1,9 @@
+#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Most of the properties are in cpu->options
+ */
+#define cpu_has_netlogic_cache	1
+
+#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mach-netlogic/irq.h new file +14 -0

new file mode 100644
index 0000000..b590245
@@ -0,0 +1,14 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 Netlogic Microsystems.
+ */
+#ifndef __ASM_NETLOGIC_IRQ_H
+#define __ASM_NETLOGIC_IRQ_H
+
+#define NR_IRQS			64
+#define MIPS_CPU_IRQ_BASE	0
+
+#endif /* __ASM_NETLOGIC_IRQ_H */

arch/mips/include/asm/mach-netlogic/war.h new file +26 -0

new file mode 100644
index 0000000..22da893
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 Netlogic Microsystems.
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <[email protected]>
+ */
+#ifndef __ASM_MIPS_MACH_NLM_WAR_H
+#define __ASM_MIPS_MACH_NLM_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_NLM_WAR_H */

arch/mips/include/asm/module.h +2 -0

index d94085a..bc01a02 100644
@@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "LOONGSON2 "
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
 #define MODULE_PROC_FAMILY "OCTEON "
+#elif defined CONFIG_CPU_XLR
+#define MODULE_PROC_FAMILY "XLR "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif

arch/mips/include/asm/netlogic/interrupt.h new file +39 -0

new file mode 100644
index 0000000..433f7e2
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ASM_NLM_INTERRUPT_H
+#define _ASM_NLM_INTERRUPT_H
+
+/* Defines for the IRQ numbers */
+
+#define IRQ_IPI_SMP_FUNCTION	3
+#define IRQ_IPI_SMP_RESCHEDULE	4
+#define IRQ_MSGRING		6
+#define IRQ_TIMER		7
+
+#endif

arch/mips/include/asm/netlogic/mips-extns.h new file +69 -0

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arch/mips/include/asm/netlogic/psb-bootinfo.h new file +103 -0

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arch/mips/include/asm/netlogic/xlr/gpio.h new file +67 -0

67 lines not on this page · raw message

arch/mips/include/asm/netlogic/xlr/iomap.h new file +125 -0

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arch/mips/include/asm/netlogic/xlr/pic.h new file +225 -0

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arch/mips/include/asm/netlogic/xlr/xlr.h new file +20 -0

new file mode 100644
index 0000000..174bbdd
@@ -0,0 +1,20 @@
+#ifndef _ASM_NLM_XLR_H
+#define _ASM_NLM_XLR_H
+
+/* Platform UART functions */
+struct uart_port;
+unsigned int nlm_xlr_uart_in(struct uart_port *, int);
+void nlm_xlr_uart_out(struct uart_port *, int, int);
+
+/* SMP support functions */
+void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
+void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
+int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
+void nlm_smp_irq_init(void);
+void nlm_boot_smp_nmi(void);
+void prom_pre_boot_secondary_cpus(void);
+
+extern struct plat_smp_ops nlm_smp_ops;
+extern unsigned long nlm_common_ebase;
+
+#endif /* _ASM_NLM_XLR_H */

arch/mips/kernel/Makefile +1 -0

index cedee2b..83bba33 100644
@@ -52,6 +52,7 @@ obj-$(CONFIG_CPU_TX39XX)	+= r2300_fpu.o r2300_switch.o
 obj-$(CONFIG_CPU_TX49XX)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_VR41XX)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON)	+= octeon_switch.o
+obj-$(CONFIG_CPU_XLR)		+= r4k_fpu.o r4k_switch.o
 
 obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_SMP_UP)		+= smp-up.o

arch/mips/kernel/cpu-probe.c +55 -0

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arch/mips/lib/Makefile +1 -0

index 2adead5..b2cad4f 100644
@@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_TX39XX)	+= r3k_dump_tlb.o
 obj-$(CONFIG_CPU_TX49XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_VR41XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON)	+= dump_tlb.o
+obj-$(CONFIG_CPU_XLR)		+= dump_tlb.o
 
 # libgcc-style stuff needed in the kernel
 obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o

arch/mips/mm/Makefile +1 -0

index d679c77..7fea5ff 100644
@@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX39XX)	+= c-tx39.o tlb-r3k.o
 obj-$(CONFIG_CPU_TX49XX)	+= c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_VR41XX)	+= c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON)	+= c-octeon.o cex-oct.o tlb-r4k.o
+obj-$(CONFIG_CPU_XLR)		+= c-netlogic.o tlb-r4k.o cex-gen.o
 
 obj-$(CONFIG_IP22_CPU_SCACHE)	+= sc-ip22.o
 obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o

arch/mips/mm/c-netlogic.c new file +450 -0

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arch/mips/mm/cache.c +5 -0

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arch/mips/mm/tlbex.c +1 -0

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arch/mips/netlogic/Kconfig new file +6 -0

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arch/mips/netlogic/xlr/Makefile new file +5 -0

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arch/mips/netlogic/xlr/irq.c new file +281 -0

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arch/mips/netlogic/xlr/platform.c new file +99 -0

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arch/mips/netlogic/xlr/setup.c new file +181 -0

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arch/mips/netlogic/xlr/smp.c new file +219 -0

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arch/mips/netlogic/xlr/smpboot.S new file +88 -0

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arch/mips/netlogic/xlr/time.c new file +45 -0

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arch/mips/netlogic/xlr/xlr_console.c new file +40 -0

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wilbur.chan

2011-03-14 12:19 UTC #1 lore raw

Will kexec be supported on XLS/XLR/XLP ?

Jayachandran C.

author

2011-03-14 14:24 UTC #2 lore raw

Quoted 1 line · wilbur.chan

Will kexec be supported on XLS/XLR/XLP ?

The patches I have does not support it. I haven't really looked at what is needed in XLR platform code to support kexec, so I'm not sure what it takes to support it for XLR either. Any pointers?

JC.

Signature · 3 lines

Jayachandran C.
[email protected]                  (Netlogic Microsystems)
[email protected]                               (The FreeBSD Project)

wu zhangjin

2011-03-18 03:26 UTC #3 lore raw

Quoted 6 lines · Jayachandran C.

Quoted 1 line · wilbur.chan
Will kexec be supported on XLS/XLR/XLP ?
The patches I have does not support it. I haven't really looked at what is needed in XLR platform code to support kexec, so I'm not sure what it takes to support it for XLR either. Any pointers?

You can get some information here:

http://dev.lemote.com/code/linux-loongson-community/wiki/kexec-loongson

And here:

http://patchwork.linux-mips.org/project/linux-mips/list/?q=kexec

BTW: what about the cpu hotplug support for XL{R, S, P} ?

Regards,
Wu Zhangjin

Quoted 8 lines

JC.
--
Jayachandran C.
[email protected] (Netlogic Microsystems) [email protected] (The FreeBSD Project)

Jayachandran C.

author

2011-03-18 09:01 UTC #4 lore raw

Quoted 9 lines · wu zhangjin

Quoted 6 lines · Jayachandran C.
Quoted 1 line · wilbur.chan
Will kexec be supported on XLS/XLR/XLP ?
The patches I have does not support it. I haven't really looked at what is needed in XLR platform code to support kexec, so I'm not sure what it takes to support it for XLR either. Any pointers?

Quoted 7 lines

You can get some information here:
http://dev.lemote.com/code/linux-loongson-community/wiki/kexec-loongson
And here:
http://patchwork.linux-mips.org/project/linux-mips/list/?q=kexec

Will look at this.

Quoted 1 line

BTW: what about the cpu hotplug support for XL{R, S, P} ?

Not right now. My intial goal for Linux/MIPS is hardware support, i.e. processor support and then drivers. I can start thinking of feature support once we have reasonable hardware support in the kernel...

Signature · 3 lines

Jayachandran C.
[email protected]                  (Netlogic Microsystems)
[email protected]                               (The FreeBSD Project)