x86 fixes
Linus,
Please pull the latest x86-fixes-for-linus git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git x86-fixes-for-linus
out-of-topic modifications in x86-fixes-for-linus:
--------------------------------------------------include/linux/pci_ids.h # 41b2610: x86, amd: Extend AMD northbridge
Thanks,
Ingo
------------------>
Andreas Herrmann (2):
x86, amd: Normalize compute unit IDs on multi-node processors x86, quirk: Fix SB600 revision check
Boris Ostrovsky (1):
x86, AMD: Set ARAT feature on AMD processors
Borislav Petkov (2):
x86, amd: Initialize variable properly
x86, amd-nb: Misc cleanliness fixes
Hans Rosenfeld (3):
x86, amd: Enable L3 cache index disable on family 0x15
x86, amd: Extend AMD northbridge caching code to support "Link Control" devices
x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUsJan Beulich (1):
x86: Adjust section placement in AMD northbridge related code
Mathieu Desnoyers (1):
x86: stop_machine_text_poke() should issue sync_core()
arch/x86/include/asm/amd_nb.h | 16 +++-- arch/x86/kernel/alternative.c | 7 ++- arch/x86/kernel/amd_nb.c | 100 +++++++++++++++++++++++++++++---- arch/x86/kernel/cpu/amd.c | 14 ++++- arch/x86/kernel/cpu/intel_cacheinfo.c | 76 ++++++++++++++++++++----- arch/x86/kernel/early-quirks.c | 7 ++- arch/x86/kernel/smpboot.c | 1 + arch/x86/pci/amd_bus.c | 2 +- include/linux/pci_ids.h | 1 + 9 files changed, 185 insertions(+), 39 deletions(-)
arch/x86/include/asm/amd_nb.h +10 -6
@@ -9,15 +9,17 @@ struct amd_nb_bus_dev_range {u8 dev_limit; }; -extern struct pci_device_id amd_nb_misc_ids[]; +extern const struct pci_device_id amd_nb_misc_ids[];extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];struct bootnode ; -extern int early_is_amd_nb (u32 value); +extern bool early_is_amd_nb (u32 value);extern int amd_cache_northbridges (void );extern void amd_flush_garts (void );extern int amd_numa_init (unsigned long start_pfn,unsigned long end_pfn);extern int amd_scan_nodes (void ); +extern int amd_get_subcaches (int ); +extern int amd_set_subcaches (int ,int );#ifdef CONFIG_NUMA_EMU extern void amd_fake_nodes (const struct bootnode *nodes,int nr_nodes);
@@ -26,6 +28,7 @@ extern void amd_get_nodes(struct bootnode *nodes);struct amd_northbridge {struct pci_dev *misc; +struct pci_dev *link; };struct amd_northbridge_info {
@@ -35,17 +38,18 @@ struct amd_northbridge_info { };extern struct amd_northbridge_info amd_northbridges; -#define AMD_NB_GART 0x1 -#define AMD_NB_L3_INDEX_DISABLE 0x2 +#define AMD_NB_GART BIT(0) +#define AMD_NB_L3_INDEX_DISABLE BIT(1) +#define AMD_NB_L3_PARTITIONING BIT(2)#ifdef CONFIG_AMD_NB -static inline int amd_nb_num (void ) +static inline u16 amd_nb_num (void ) {return amd_northbridges.num; } -static inline int amd_nb_has_feature (int feature) +static inline bool amd_nb_has_feature (unsigned feature) {return ((amd_northbridges.flags & feature) == feature); }
arch/x86/kernel/alternative.c +6 -1
@@ -620,7 +620,12 @@ static int __kprobes stop_machine_text_poke(void *data)flush_icache_range ((unsigned long )p->addr, (unsigned long )p->addr + p->len); } - +/* +* Intel Archiecture Software Developer's Manual section 7.1.3 specifies +* that a core serializing instruction such as "cpuid" should be +* executed on _each_ core before the new instruction is made visible. +*/ +sync_core ();return 0 ; }
arch/x86/kernel/amd_nb.c +88 -12
153 lines not on this page · raw message
arch/x86/kernel/cpu/amd.c +11 -3
@@ -261,7 +261,7 @@ static int __cpuinit nearby_node(int apicid)#ifdef CONFIG_X86_HT static void __cpuinit amd_get_topology (struct cpuinfo_x86 *c) { -u32 nodes; +u32 nodes, cores_per_cu =1 ;u8 node_id;int cpu =smp_processor_id ();
@@ -276,6 +276,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)/* get compute unit information */ smp_num_siblings = ((ebx >>8 ) &3 ) +1 ; c->compute_unit_id = ebx &0xff ; + cores_per_cu += ((ebx >>8 ) &3 ); }else if (cpu_has (c,X86_FEATURE_NODEID_MSR )) {u64 value;
@@ -288,15 +289,18 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)/* fixup multi-node processor information */ if (nodes >1 ) {u32 cores_per_node; +u32 cus_per_node;set_cpu_cap (c,X86_FEATURE_AMD_DCM ); cores_per_node = c->x86_max_cores / nodes; + cus_per_node = cores_per_node / cores_per_cu;/* store NodeID, use llc_shared_map to store sibling info */ per_cpu (cpu_llc_id, cpu) = node_id; -/* core id to be in range from 0 to (cores_per_node - 1) */ - c->cpu_core_id = c->cpu_core_id % cores_per_node; +/* core id has to be in the [0 .. cores_per_node - 1] range */ + c->cpu_core_id %= cores_per_node; + c->compute_unit_id %= cus_per_node; } }#endif
@@ -594,6 +598,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) } }#endif + +/* As a rule processors have APIC timer running in deep C states */ +if (c->x86 >=0xf && !cpu_has_amd_erratum (amd_erratum_400)) +set_cpu_cap (c,X86_FEATURE_ARAT ); }#ifdef CONFIG_X86_32
arch/x86/kernel/cpu/intel_cacheinfo.c +61 -15
156 lines not on this page · raw message
arch/x86/kernel/early-quirks.c +6 -1
@@ -159,7 +159,12 @@ static void __init ati_bugs_contd(int num, int slot, int func)if (rev >=0x40 ) acpi_fix_pin2_polarity =1 ; -if (rev >0x13 ) +/* +* SB600: revisions 0x11, 0x12, 0x13, 0x14, ... +* SB700: revisions 0x39, 0x3a, ... +* SB800: revisions 0x40, 0x41, ... +*/ +if (rev >=0x39 )return ;if (acpi_use_timer_override)
arch/x86/kernel/smpboot.c +1 -0
@@ -414,6 +414,7 @@ void __cpuinit set_cpu_sibling_map(int cpu)if (cpu_has (c,X86_FEATURE_TOPOEXT )) {if (c->phys_proc_id == o->phys_proc_id && +per_cpu (cpu_llc_id, cpu) ==per_cpu (cpu_llc_id, i) && c->compute_unit_id == o->compute_unit_id)link_thread_siblings (cpu, i); } else if (c->phys_proc_id == o->phys_proc_id &&
arch/x86/pci/amd_bus.c +1 -1
@@ -350,7 +350,7 @@ static int __init early_fill_mp_bus_info(void)#define ENABLE_CF8_EXT_CFG (1ULL << 46) -static void enable_pci_io_ecs (void *unused) +static void __cpuinit enable_pci_io_ecs (void *unused) {u64 reg;rdmsrl (MSR_AMD64_NB_CFG , reg);
include/linux/pci_ids.h +1 -0
@@ -518,6 +518,7 @@#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603 +#define PCI_DEVICE_ID_AMD_15H_NB_LINK 0x1604#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703#define PCI_DEVICE_ID_AMD_LANCE 0x2000#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001