TS-7800 port for U-Boot
Subsystems (8)
cover TS-7800 port for U-Boot
The TS-7800 is an Orion5x implementation by Technologic Systems.
Albert, Wolfgang -
Thanks for reviewing my patch series and sorry for the delay in updating it.
Changelog:
- Fixed all checkpatch errors.
- Updated copyright year.
- Renamed CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT and introduced new CONFIG_SKIP_LOWLEVEL_INIT that skips only lowlevel_init.
- Documented machine type ID workaround in the README.
- Removed "ddr" from name of orion5x_ddr_addr_decode_registers.
- Allow the environment to override the MAC even if CONFIG_PRESERVE_LOCAL_MAC is set.
Michael Spang (9):
arm926ej-s: Invalidate instruction cache in flush_cache
mvgbe: Support preserving the existing MAC address
orion5x: Increase maximum bank size to 128M
orion5x: Fix wrong address in orion5x_sdram_bar
ARM: Rename CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT
ARM: Implement CONFIG_SKIP_LOWLEVEL_INIT for arm926ej-s Add board support for TS-7800
Add NAND support for TS-7800
Add README for TS-7800
MAKEALL | 1 + Makefile | 2 +- README | 8 +- arch/arm/cpu/arm1136/start.S | 6 +- arch/arm/cpu/arm720t/start.S | 2 +- arch/arm/cpu/arm920t/at91/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/start.S | 6 +- arch/arm/cpu/arm925t/start.S | 2 +- arch/arm/cpu/arm926ejs/at91/Makefile | 2 + arch/arm/cpu/arm926ejs/davinci/Makefile | 2 + arch/arm/cpu/arm926ejs/orion5x/Makefile | 2 + arch/arm/cpu/arm926ejs/orion5x/dram.c | 6 +- arch/arm/cpu/arm926ejs/start.S | 9 +- arch/arm/cpu/arm946es/start.S | 4 +- arch/arm/cpu/arm_intcm/start.S | 4 +- arch/arm/cpu/armv7/start.S | 2 +- arch/arm/cpu/lh7a40x/start.S | 2 +- arch/arm/cpu/s3c44b0/start.S | 2 +- arch/arm/cpu/sa1100/start.S | 2 +- arch/arm/include/asm/arch-orion5x/cpu.h | 2 +- arch/arm/include/asm/arch-orion5x/orion5x.h | 3 +- arch/arm/lib/cache.c | 2 + board/ns9750dev/lowlevel_init.S | 6 +- board/technologic/ts7800/Makefile | 46 ++++++ board/technologic/ts7800/ts7800.c | 36 +++++ boards.cfg | 1 + doc/README.ts7800 | 84 ++++++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ts7800_nand.c | 68 ++++++++ drivers/net/mvgbe.c | 20 +++ include/common.h | 2 +- include/configs/SMN42.h | 2 +- include/configs/a320evb.h | 2 +- include/configs/afeb9260.h | 2 +- include/configs/armadillo.h | 2 +- include/configs/aspenite.h | 2 +- include/configs/at91cap9adk.h | 2 +- include/configs/at91rm9200dk.h | 12 +- include/configs/at91rm9200ek.h | 6 +- include/configs/at91sam9260ek.h | 2 +- include/configs/at91sam9261ek.h | 2 +- include/configs/at91sam9263ek.h | 4 +- include/configs/at91sam9m10g45ek.h | 2 +- include/configs/at91sam9rlek.h | 2 +- include/configs/cmc_pu2.h | 4 +- include/configs/colibri_pxa270.h | 2 +- include/configs/cpuat91.h | 6 +- include/configs/csb637.h | 4 +- include/configs/da830evm.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/davinci_dm355evm.h | 2 +- include/configs/davinci_dm355leopard.h | 2 +- include/configs/davinci_dm365evm.h | 2 +- include/configs/davinci_dm6467evm.h | 2 +- include/configs/davinci_dvevm.h | 6 +- include/configs/davinci_schmoogie.h | 2 +- include/configs/davinci_sffsdr.h | 2 +- include/configs/davinci_sonata.h | 6 +- include/configs/dkb.h | 2 +- include/configs/dnp1110.h | 2 +- include/configs/dockstar.h | 2 +- include/configs/ea20.h | 2 +- include/configs/evb4510.h | 2 +- include/configs/gcplus.h | 4 +- include/configs/guruplug.h | 2 +- include/configs/hawkboard.h | 2 +- include/configs/integratorap.h | 2 +- include/configs/integratorcp.h | 6 +- include/configs/kb9202.h | 2 +- include/configs/km_arm.h | 2 +- include/configs/lpc2292sodimm.h | 2 +- include/configs/meesc.h | 2 +- include/configs/mp2usb.h | 4 +- include/configs/mv88f6281gtw_ge.h | 2 +- include/configs/mx31pdk.h | 2 +- include/configs/nhk8815.h | 2 +- include/configs/openrd_base.h | 2 +- include/configs/otc570.h | 2 +- include/configs/pm9261.h | 2 +- include/configs/pm9263.h | 2 +- include/configs/pm9g45.h | 2 +- include/configs/pxa255_idp.h | 2 +- include/configs/rd6281a.h | 2 +- include/configs/sbc2410x.h | 2 +- include/configs/sbc35_a9g20.h | 2 +- include/configs/shannon.h | 2 +- include/configs/sheevaplug.h | 2 +- include/configs/tegra2-common.h | 2 +- include/configs/tny_a9260.h | 2 +- include/configs/top9000.h | 2 +- include/configs/ts7800.h | 193 +++++++++++++++++++++++ include/configs/tx25.h | 2 +- include/configs/zipitz2.h | 2 +- 95 files changed, 585 insertions(+), 117 deletions(-) create mode 100644 board/technologic/ts7800/Makefile create mode 100644 board/technologic/ts7800/ts7800.c create mode 100644 doc/README.ts7800 create mode 100644 drivers/mtd/nand/ts7800_nand.c create mode 100644 include/configs/ts7800.h
Signature · 1 line
1.7.2.3
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
--- arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/lib/cache.c +2 -0
@@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : :"memory" );/* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : :"r" (0 )); +/* invalidate icache for coherence with cleaned dcache */ + asm("mcr p15, 0, %0, c7, c5, 0" : :"r" (0 ));#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all (void );
Signature · 1 line
1.7.2.3
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Hi Michael,
Curiously, have any idea how to test cache stuff?
2011/3/18 Michael Spang <[email protected]>:
Quoted 31 lines
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by Michael Spang <[email protected]>---
?arch/arm/lib/cache.c | ? ?2 ++
?1 files changed, 2 insertions(+), 0 deletions(-)arch/arm/lib/cache.c +0
-0@@ -37,6 +37,8 @@ void ?flush_cache (unsigned long dummy1, unsigned long dummy2) ? ? ? ?asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");? ? ? ?/* disable write buffer as well (page 2-22) */
? ? ? ?asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ ? ? ? /* invalidate icache for coherence with cleaned dcache */
+ ? ? ?asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); ?#endif
?#ifdefCONFIG_OMAP34XX
? ? ? ?voidv7_flush_cache_all(void);
--
1.7.2.3_______________________________________________
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Signature · 2 lines
cheers, jay
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Quoted 2 lines · arden jay
Hi Michael,
Curiously, have any idea how to test cache stuff?
I don't have any good suggestions for testing cache stuff in general, but this one is pretty easy to test if you have the board in question. Because U-Boot is loaded *as if it were linux* by the manufacturer's bootloader, the initial location of U-Boot is the same as where we ultimately load the Linux kernel. Without this patch the symptom is the failure of Linux to start from U-Boot.
Michael
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache.
It then should have cache miss, and forces to reload the instruction from memory?
Why it will have problem while U-boot & Kernel at the same memory location?
2011/3/20 Michael Spang <[email protected]>:
Quoted 13 lines · arden jay
Quoted 2 lines
Hi Michael,
Curiously, have any idea how to test cache stuff?I don't have any good suggestions for testing cache stuff in general, but this one is pretty easy to test if you have the board in question. Because U-Boot is loaded *as if it were linux* by the manufacturer's bootloader, the initial location of U-Boot is the same as where we ultimately load the Linux kernel. Without this patch the symptom is the failure of Linux to start from U-Boot.
Michael
Signature · 2 lines
cheers, jay
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Le 03/20/11 06:36, arden jay a ?crit :
Quoted 8 lines
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache.
It then should have cache miss, and forces to reload the instruction from memory?
Why it will have problem while U-boot& Kernel at the same memory location?
The error in your assumption is the "it then should have cache miss". A cache won't have a cache miss if it has already been fetched and not yet been invalidated, and the i-cache won't magically invalidate just because you do data writes at the location where the i-cache was fetched from; you end up with an i-cache that pretends to be valid but no longer matches the main memory content.
Amicalement,
Signature · 1 line
Albert.
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Hi Albert,
I got it, thanks your explaination.
2011/3/20 Albert ARIBAUD <[email protected]>:
Quoted 23 lines
Le 03/20/11 06:36, arden jay a ?crit :
Quoted 10 lines
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache.
It then should have cache miss, and forces to reload the instruction from memory?
Why it will have problem while U-boot& ?Kernel at the same memory location?The error in your assumption is the "it then should have cache miss". A cache won't have a cache miss if it has already been fetched and not yet been invalidated, and the i-cache won't magically invalidate just because you do data writes at the location where the i-cache was fetched from; you end up with an i-cache that pretends to be valid but no longer matches the main memory content.
Amicalement,
--
Albert.
Signature · 2 lines
cheers, jay
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
In reply to arden jayQuoted 9 lines · arden jay
Hi Michael,
I still have question. :)
When ARM fetch instruction, it firstly try cache.
It then should have cache miss, and forces to reload the instruction from memory?Why it will have problem while U-boot & Kernel at the same memory location?
If the instruction fetch misses the cache, then it works fine. That's why invalidating solves the problem. The problem is that it hits, but returns the wrong instructions. The code from U-Boot is loaded into the icache when U-Boot is started (before it is relocated) and some of it is still in the icache when we execute linux. So the CPU ends up fetching the wrong instructions.
On ARM if code is stored to RAM, then the modified addresses must be manually invalidated in the instruction cache. The hardware does not do this for us.
Michael
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
In reply to arden jayHi Arden,
Quoted 2 lines · arden jay
Hi Michael,
Curiously, have any idea how to test cache stuff?
Recently I did some cache testing. Here is the technique I used for data-cache:
To test flush:
* Write a known pattern to a region of memory
* Flush the region
* Invalidate the region
* Read back the region and see if you get the original pattern. If the flush was effective you will see the original data.
To test Invalidate:
* Write a known pattern to a region of memory
* Invalidate the region immediately
* Read back the region and see if you get the original pattern. You should *not* be seeing the expected pattern for the entire region if the invalidate was successful.
Similar tests can be done for the I-cache, but maybe a little more tedious.
I agree that these tests may not be 100% fool-proof - for instance what if both invalidate and flush didn't work in the first case. But these should at least catch very obvious errors and can be used in combination with other techniques to make sure that your cache operations are indeed working.
Additionally, there was a JTAG debugger technique that I found quite useful. If your processor supports a technique called DAP(Debug Access Port or Dual Access Port, I am not sure) then a debugger like Lauterbach can view memory in two modes, one the normal or CPU mode and the other DAP mode. In normal mode the memory is dumped as if it is viewed from the CPU, so it goes through the cache and you see the cache contents if the area in question is in cache. In DAP mode the real memory contents are dumped. Comparing these two you can see whether cache and memory are coherent for a given area. It worked quite well with Lauterbach and OMAP4.
br,
Aneesh
Quoted 36 lines
2011/3/18 Michael Spang<[email protected]>:
Quoted 31 lines
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by Michael Spang<[email protected]>--- arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)arch/arm/lib/cache.c +2
-1@@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : :"memory" );/* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : :"r" (0 )); +/* invalidate icache for coherence with cleaned dcache */ + asm("mcr p15, 0, %0, c7, c5, 0" : :"r" (0 ));#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all (void ); --1.7.2.3
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PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Hi Michael,
Thanks, it is the key point:
"The problem is that it hits, but returns the wrong instructions."
Hi Aneesh,
Thanks for your sharing, it makes sense to check that way.
2011/3/21 Aneesh V <[email protected]>:
Quoted 87 lines
Hi Arden,
Quoted 3 lines · arden jay
Hi Michael,
Curiously, have any idea how to test cache stuff?Recently I did some cache testing. Here is the technique I used for data-cache:
To test flush:
* Write a known pattern to a region of memory
* Flush the region
* Invalidate the region
* Read back the region and see if you get the original pattern. If the flush was effective you will see the original data.To test Invalidate:
* Write a known pattern to a region of memory
* Invalidate the region immediately
* Read back the region and see if you get the original pattern. You should *not* be seeing the expected pattern for the entire region if the invalidate was successful.Similar tests can be done for the I-cache, but maybe a little more tedious.
I agree that these tests may not be 100% fool-proof - for instance what if both invalidate and flush didn't work in the first case. But these should at least catch very obvious errors and can be used in combination with other techniques to make sure that your cache operations are indeed working.
Additionally, there was a JTAG debugger technique that I found quite useful. If your processor supports a technique called
DAP(Debug Access Port or Dual Access Port, I am not sure)then a debugger like Lauterbach can view memory in two modes, one the normal or CPU mode and the other DAP mode. In normal mode the memory is dumped as if it is viewed from the CPU, so it goes through the cache and you see the cache contents if the area in question is in cache. In DAP mode the real memory contents are dumped. Comparing these two you can see whether cache and memory are coherent for a given area. It worked quite well with Lauterbach and OMAP4.br,
AneeshQuoted 39 lines
2011/3/18 Michael Spang<[email protected]>:
Quoted 34 lines
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by Michael Spang<[email protected]>---
?arch/arm/lib/cache.c | ? ?2 ++
?1 files changed, 2 insertions(+), 0 deletions(-)arch/arm/lib/cache.c +0
-0@@ -37,6 +37,8 @@ void ?flush_cache (unsigned long dummy1, unsigned long dummy2)? ? ? ?asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : :
"memory");
? ? ? ?/* disable write buffer as well (page 2-22) */
? ? ? ?asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ ? ? ? /* invalidate icache for coherence with cleaned dcache */
+ ? ? ?asm("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); ?#endif
?#ifdefCONFIG_OMAP34XX
? ? ? ?voidv7_flush_cache_all(void);
--
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Signature · 2 lines
cheers, jay
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
In reply to Michael Spang(although this patch is more than two *years* old, it never got properly answered to. I am doing so here to make sure future readers know why it was not applied and won't be.)
Hi Michael,
Quoted 15 lines · Michael Spang
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by Michael Spang <[email protected]>--- arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)arch/arm/lib/cache.c +0
-0
arch/arm/lib/cache.c void flush_cache (unsigned long dummy1, unsigned long dummy2) · line 44
Quoted 8 lines
arch/arm/lib/cache.c +2
-0@@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : :"memory" );/* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : :"r" (0 )); +/* invalidate icache for coherence with cleaned dcache */ + asm("mcr p15, 0, %0, c7, c5, 0" : :"r" (0 ));#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all (void );
This patch has obviously not been applied, and won't be, because of two reasons: i) overwriting part of U-Boot when loading the kernel is a bug which should not be papered over, and ii) if we had to do this anyway, the right place to do it would have been where the issue might occur, that is, in the OS boot sequence, not in the cache handling functions.
Apologies for not properly answering in due time.
Amicalement,
Signature · 1 line
Albert.
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Albert,
That's not a correct characterization of the bug.
The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot.
Michael
Quoted 45 lines · Albert ARIBAUD
(although this patch is more than two *years* old, it never got properly answered to. I am doing so here to make sure future readers know why it was not applied and won't be.)
Hi Michael,
Quoted 15 lines · Michael Spang
If U-Boot is loaded from RAM and the OS is loaded into an overlapping region, the instruction cache is not coherent when that OS is started. We must therefore invalidate the instruction cache in addition to cleaning the data cache.
Signed-off-by Michael Spang <[email protected]>--- arch/arm/lib/cache.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)arch/arm/lib/cache.c +0
-0arch/arm/lib/cache.c void flush_cache (unsigned long dummy1, unsigned long dummy2) · line 44
Quoted 8 lines
arch/arm/lib/cache.c +2
-0@@ -37,6 +37,8 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : :"memory" );/* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : :"r" (0 )); +/* invalidate icache for coherence with cleaned dcache */ + asm("mcr p15, 0, %0, c7, c5, 0" : :"r" (0 ));#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all (void );This patch has obviously not been applied, and won't be, because of two reasons: i) overwriting part of U-Boot when loading the kernel is a bug which should not be papered over, and ii) if we had to do this anyway, the right place to do it would have been where the issue might occur, that is, in the OS boot sequence, not in the cache handling functions.
Apologies for not properly answering in due time.
Amicalement,
--
Albert.
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Hi Michael,
Quoted 7 lines · Michael Spang
Albert,
That's not a correct characterization of the bug.
The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot.
Thanks for this pointing out this scenario, which is correct, although it was not raised in the original bug description.
I begs however the question whether anything from re-relocation can survive in the icache from between the moment the relocation starts and the moment the OS is given transfer to. IOW, was this issue actually met?
Anyway I stand by my statement that even if there is an issue to fix, this patch fixes it in the wrong place.
Quoted 1 line
Michael
Amicalement,
Signature · 1 line
Albert.
PATCH 1/9 arm926ej-s: Invalidate instruction cache in flush_cache
Quoted 13 lines · Albert ARIBAUD
Hi Michael,
Quoted 7 lines · Michael Spang
Albert,
That's not a correct characterization of the bug.
The incoherent cache lines are from before the relocation stage. If U-Boot is relocating from RAM, and later copies the OS there without invalidating those lines, then that's a bug in U-Boot.
Quoted 7 lines
Thanks for this pointing out this scenario, which is correct, although it was not raised in the original bug description.
I begs however the question whether anything from re-relocation can survive in the icache from between the moment the relocation starts and the moment the OS is given transfer to. IOW, was this issue actually met?
Yes, I had boot failures without this patch on the device I was porting to (TS-7800). It happened consistently.
Quoted 3 lines
Anyway I stand by my statement that even if there is an issue to fix, this patch fixes it in the wrong place.
Ok, that's fair. I was hoping to repost this series someday and will take that into account.
Michael
PATCH 2/9 mvgbe: Support preserving the existing MAC address
In reply to Michael SpangThe MVGBE driver either gets the MAC from the environment, or invents one. This allows the driver to leave the existing address alone in case it is initialized before U-Boot starts.
--- drivers/net/mvgbe.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-)
drivers/net/mvgbe.c +20 -0
@@ -380,6 +380,22 @@ static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr) }/* +* port_uc_addr_get - This function gets the port unicast address. +*/ +static void port_uc_addr_get (struct mvgbe_registers *regs,u8 * p_addr) +{ +u32 mac_l =MVGBE_REG_RD (regs->macal); +u32 mac_h =MVGBE_REG_RD (regs->macah); + + p_addr[0 ] = (mac_h >>24 ); + p_addr[1 ] = (mac_h >>16 ); + p_addr[2 ] = (mac_h >>8 ); + p_addr[3 ] = (mac_h >>0 ); + p_addr[4 ] = (mac_l >>8 ); + p_addr[5 ] = (mac_l >>0 ); +} + +/* * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. */ static void mvgbe_init_rx_desc_ring (struct mvgbe_device *dmvgbe)
@@ -719,6 +735,9 @@ error1: }while (!eth_getenv_enetaddr (s, dev->enetaddr)) { +#if defined(CONFIG_PRESERVE_LOCAL_MAC ) +port_uc_addr_get (dmvgbe->regs, dmvgbe->dev.enetaddr); +#else /* Generate Private MAC addr if not set */ dev->enetaddr[0 ] =0x02 ; dev->enetaddr[1 ] =0x50 ;
@@ -734,6 +753,7 @@ error1: dev->enetaddr[4 ] =get_random_hex (); dev->enetaddr[5 ] =get_random_hex ();#endif +#endif eth_setenv_enetaddr (s, dev->enetaddr); }
Signature · 1 line
1.7.2.3
PATCH 2/9 mvgbe: Support preserving the existing MAC address
Dear Michael Spang,
Quoted 3 lines · In message <[email protected]> you…
The MVGBE driver either gets the MAC from the environment, or invents one. This allows the driver to leave the existing address alone in case it is initialized before U-Boot starts.
Who or what would be doing that?
drivers/net/mvgbe.c error1: · line 740
Quoted 4 lines
drivers/net/mvgbe.c +3
-0while (!eth_getenv_enetaddr (s, dev->enetaddr)) { +#if defined(CONFIG_PRESERVE_LOCAL_MAC ) +port_uc_addr_get (dmvgbe->regs, dmvgbe->dev.enetaddr); +#else
For consistency, should this not be
port_uc_addr_get(dmvgbe->regs, dev->enetaddr);
?
drivers/net/mvgbe.c error1: · line 758
Quoted 10 lines
drivers/net/mvgbe.c +1
-0/* Generate Private MAC addr if not set */ dev->enetaddr[0 ] =0x02 ; dev->enetaddr[1 ] =0x50 ;@@ -734,6 +753,7 @@ error1: dev->enetaddr[4 ] =get_random_hex (); dev->enetaddr[5 ] =get_random_hex ();#endif +#endif eth_setenv_enetaddr (s, dev->enetaddr); }
And please add documentation for the new CONFIG_PRESERVE_LOCAL_MAC to the README.
Best regards,
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Q: What do you get when you cross an ethernet with an income statement? A: A local area networth.
PATCH 2/9 mvgbe: Support preserving the existing MAC address
Quoted 2 lines · Wolfgang Denk
And please add documentation for the new
CONFIG_PRESERVE_LOCAL_MACto the README.
We have something similar already on Freescale parts, but it does sometimes cause problems. If the environment ethaddr is already set, it is left alone. Otherwise, the MAC address is read from EEPROM.
So we could use CONFIG_PRESERVE_LOCAL_MAC to alter this behavior (i.e. always use the EEPROM). However, the current default is already CONFIG_PRESERVE_LOCAL_MAC, so can we change this to something like CONFIG_OVERRIDE_LOCAL_MAC?
Signature · 2 lines
Timur Tabi Linux kernel developer at Freescale
PATCH 2/9 mvgbe: Support preserving the existing MAC address
Quoted 5 lines · On Mon, Apr 25, 2011 at 7:37 AM, Tabi Timur-B04825 <[email protected]> wrote:
Quoted 2 lines · Wolfgang Denk
And please add documentation for the new
CONFIG_PRESERVE_LOCAL_MACto the README.
Quoted 8 lines
We have something similar already on Freescale parts, but it does sometimes cause problems. ?If the environment ethaddr is already set, it is left alone. ?Otherwise, the MAC address is read from EEPROM.
So we could use
CONFIG_PRESERVE_LOCAL_MACto alter this behavior (i.e. always use the EEPROM). ?However, the current default is alreadyCONFIG_PRESERVE_LOCAL_MAC, so can we change this to something likeCONFIG_OVERRIDE_LOCAL_MAC?
I don't think the option you want is the same. If there's a MAC in the environment, I want to use it. Otherwise, I want U-Boot to leave the MAC alone because the manufacturer assigned MAC was written to the interface's registers before U-Boot started.
Michael
PATCH 2/9 mvgbe: Support preserving the existing MAC address
Quoted 14 lines · On Tuesday, April 26, 2011 00:23:47 Michael Spang wrote:
Quoted 4 lines · On Mon, Apr 25, 2011 at 7:37 AM, Tabi Timur-B04825 wrote:
Quoted 2 lines · Wolfgang Denk
And please add documentation for the new
CONFIG_PRESERVE_LOCAL_MACto the README.Quoted 8 lines
We have something similar already on Freescale parts, but it does sometimes cause problems. If the environment ethaddr is already set, it is left alone. Otherwise, the MAC address is read from EEPROM.
So we could use
CONFIG_PRESERVE_LOCAL_MACto alter this behavior (i.e. always use the EEPROM). However, the current default is alreadyCONFIG_PRESERVE_LOCAL_MAC, so can we change this to something likeCONFIG_OVERRIDE_LOCAL_MAC?
Quoted 4 lines
I don't think the option you want is the same. If there's a MAC in the environment, I want to use it. Otherwise, I want U-Boot to leave the MAC alone because the manufacturer assigned MAC was written to the interface's registers before U-Boot started.
so implement this in your board file in misc_init_r or board_eth_init. have the code do something like:
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
/* ... read current MAC out of the driver's registers ... */
eth_setenv_enetaddr("ethaddr", enetaddr);
}then you dont need ugly config hacks in random drivers
-mike
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PATCH 2/9 mvgbe: Support preserving the existing MAC address
Quoted 9 lines · Mike Frysinger
so implement this in your board file in
misc_init_rorboard_eth_init. have the code do something like:uchar enetaddr[6]; if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { /* ... read current MAC out of the driver's registers ... */ eth_setenv_enetaddr("ethaddr", enetaddr); }then you dont need ugly config hacks in random drivers
This is a feature that could be applied to the e1000 drivers. The current situation is a mess. Some drivers ignore the environment, some of them always use it. This should probably be standardized.
Signature · 2 lines
Timur Tabi Linux kernel developer at Freescale
PATCH 2/9 mvgbe: Support preserving the existing MAC address
Quoted 9 lines · On Sat, Apr 30, 2011 at 10:34, Tabi Timur-B04825 wrote:
Quoted 8 lines · Mike Frysinger
so implement this in your board file in
misc_init_rorboard_eth_init. ?have the code do something like:
? ? ? uchar enetaddr[6];
? ? ? if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
? ? ? ? ? ? ? /* ... read current MAC out of the driver's registers ... */ ? ? ? ? ? ? ?eth_setenv_enetaddr("ethaddr", enetaddr);
? ? ? }
Quoted 3 lines
Quoted 1 line
then you dont need ugly config hacks in random drivers
This is a feature that could be applied to the e1000 drivers. ?The current situation is a mess. ?Some drivers ignore the environment, some of them always use it. ?This should probably be standardized.
it is standardized already. no driver should be touching the environment. it should only ever use its own eth_device->enetaddr. the common eth code already takes care of syncing the env and that member.
also, please fix your e-mailer to properly wrap long lines. -mike
PATCH 2/9 mvgbe: Support preserving the existing MAC address
In reply to Wolfgang DenkQuoted 8 lines · Wolfgang Denk
Dear Michael Spang,
Quoted 3 lines · In message <[email protected]> you…
The MVGBE driver either gets the MAC from the environment, or invents one. This allows the driver to leave the existing address alone in case it is initialized before U-Boot starts.
Who or what would be doing that?
The manufacturer's bootloader runs first, and cannot easily be replaced. So U-Boot is loaded second, after the MAC is already set.
Quoted 11 lines
drivers/net/mvgbe.c error1: · line 740
Quoted 5 lines
? ? ? ? ? ? ? while (!eth_getenv_enetaddr(s,
dev->enetaddr)) {drivers/net/mvgbe.c +3
-0+#if defined(CONFIG_PRESERVE_LOCAL_MAC ) + ? ? ? ? ? ? ? ? ? ? port_uc_addr_get(dmvgbe->regs, dmvgbe->dev.enetaddr); +#else For consistency, should this not be
? ? ? ?port_uc_addr_get(dmvgbe->regs,
dev->enetaddr);?
Yes.
Quoted 15 lines
Quoted 8 lines
? ? ? ? ? ? ? ? ? ? ? /* Generate Private MAC addr if not set */ ? ? ? ? ? ? ? ? ? ? ? dev->enetaddr[0] =
0x02;
? ? ? ? ? ? ? ? ? ? ? dev->enetaddr[1] =0x50;(quoted diff) +0
-0@@ -734,6 +753,7 @@ error1: ? ? ? ? ? ? ? ? ? ? ? dev->enetaddr[4] = get_random_hex(); ? ? ? ? ? ? ? ? ? ? ? dev->enetaddr[5] = get_random_hex();Quoted 4 lines
?#endif
+#endif
? ? ? ? ? ? ? ? ? ? ?eth_setenv_enetaddr(s, dev->enetaddr); ? ? ? ? ? ? ? }And please add documentation for the new
CONFIG_PRESERVE_LOCAL_MACto the README.
Ok I'll add:
CONFIG_PRESERVE_LOCAL_MAC
If no MAC address is set in the environment, then preserve the ethernet interface's current MAC address. Used if the MAC is configured before U-Boot is loaded.
Thanks,
Michael
PATCH 2/9 mvgbe: Support preserving the existing MAC address
In reply to Michael SpangQuoted 1 line · On Thursday, March 17, 2011 15:46:56 Michael Spang wrote:
while (!eth_getenv_enetaddr(s,
dev->enetaddr)) {
this logic in the mvgbe is plain broken. it should not be touching the env at all. if there is no eeprom to read, then the mvgbe driver should leave dev-
Quoted 1 line
enetaddr alone. let the boards take care of setting things up.
i.e. this patch:
drivers/net/mvgbe.c +5 -28
@@ -645,7 +645,6 @@ int mvgbe_initialize(bd_t *bis)struct mvgbe_device *dmvgbe;struct eth_device *dev;int devnum; -char *s;u8 used_ports[MAX_MVGBE_DEVS ] =CONFIG_MVGBE_PORTS ;for (devnum =0 ; devnum <MAX_MVGBE_DEVS ; devnum++) {
@@ -700,16 +699,13 @@ error1:/* must be less than NAMESIZE (16) */ sprintf (dev->name,"egiga%d" , devnum); -/* Extract the MAC address from the environment */ switch (devnum) {case 0 : dmvgbe->regs = (void *)MVGBE0_BASE ; - s ="ethaddr" ;break ;#if defined(MVGBE1_BASE )case 1 : dmvgbe->regs = (void *)MVGBE1_BASE ; - s ="eth1addr" ;break ;#endif default :/* this should never happen */
@@ -718,30 +714,11 @@ error1:return -1 ; } -while (!eth_getenv_enetaddr (s, dev->enetaddr)) { -/* Generate Private MAC addr if not set */ - dev->enetaddr[0 ] =0x02 ; - dev->enetaddr[1 ] =0x50 ; - dev->enetaddr[2 ] =0x43 ; -#if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION ) -/* Generate fixed lower MAC half using devnum */ - dev->enetaddr[3 ] =0 ; - dev->enetaddr[4 ] =0 ; - dev->enetaddr[5 ] = devnum; -#else -/* Generate random lower MAC half */ - dev->enetaddr[3 ] =get_random_hex (); - dev->enetaddr[4 ] =get_random_hex (); - dev->enetaddr[5 ] =get_random_hex (); -#endif -eth_setenv_enetaddr (s, dev->enetaddr); - } - - dev->init = (void *)mvgbe_init; - dev->halt = (void *)mvgbe_halt; - dev->send = (void *)mvgbe_send; - dev->recv = (void *)mvgbe_recv; - dev->write_hwaddr = (void *)mvgbe_write_hwaddr; + dev->init = mvgbe_init; + dev->halt = mvgbe_halt; + dev->send = mvgbe_send; + dev->recv = mvgbe_recv; + dev->write_hwaddr = mvgbe_write_hwaddr;eth_register (dev);
-mike
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PATCH 3/9 orion5x: Increase maximum bank size to 128M
In reply to Michael SpangThe TS-7800 has one 128M RAM bank, so the maximum must be increased.
--- arch/arm/include/asm/arch-orion5x/orion5x.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/include/asm/arch-orion5x/orion5x.h +1 -1
@@ -63,7 +63,7 @@#define MAX_MVGBE_DEVS 1#define MVGBE0_BASE ORION5X_EGIGA_BASE -#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) +#define CONFIG_MAX_RAM_BANK_SIZE (128*1024*1024)/* include here SoC variants. 5181, 5281, 6183 should go here when adding support for them, and this comment should then be updated. */
Signature · 1 line
1.7.2.3
PATCH 4/9 orion5x: Fix wrong address in orion5x_sdram_bar
In reply to Michael SpangThis code intends to read the SDRAM controller base address registers but is instead reading the CPU window base address registers. Also, remove "ddr" from the name of struct orion5x_addr_decode_registers, since it also applies to other decode registers.
--- arch/arm/cpu/arm926ejs/orion5x/dram.c | 6 +++--- arch/arm/include/asm/arch-orion5x/cpu.h | 2 +- arch/arm/include/asm/arch-orion5x/orion5x.h | 1 + 3 files changed, 5 insertions(+), 4 deletions(-)
arch/arm/cpu/arm926ejs/orion5x/dram.c +3 -3
@@ -36,9 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;*/ u32 orion5x_sdram_bar (enum memory_bank bank) { -struct orion5x_ddr_addr_decode_registers *winregs = - (struct orion5x_ddr_addr_decode_registers *) -ORION5X_CPU_WIN_BASE ; +struct orion5x_addr_decode_registers *winregs = + (struct orion5x_addr_decode_registers *) +ORION5X_SDRAM_CTRL_BASE ;u32 result =0 ;u32 enable =0x01 & winregs[bank].size;
arch/arm/include/asm/arch-orion5x/cpu.h +1 -1
@@ -243,7 +243,7 @@ struct orion5x_cpu_registers {* DDR SDRAM Controller Address Decode Registers * Source: 88F5182 User Manual, Appendix A, section A.5.1 */ -struct orion5x_ddr_addr_decode_registers { +struct orion5x_addr_decode_registers {u32 base;u32 size; };
arch/arm/include/asm/arch-orion5x/orion5x.h +1 -0
@@ -42,6 +42,7 @@#define ORION5X_REGISTER (x) (ORION5X_REGS_PHY_BASE + x)/* Documented registers */ +#define ORION5X_SDRAM_CTRL_BASE (ORION5X_REGISTER(0x01500))#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
Signature · 1 line
1.7.2.3
PATCH 5/9 ARM: Rename CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT
In reply to Michael SpangFor ARM, the CONFIG_SKIP_LOWLEVEL_INIT option implies that the cpu_init_crit and lowlevel_init assembly functions are skipped. We may want to skip only lowlevel_init, so rename the option that skips both to CONFIG_SKIP_CPU_INIT_CRIT. The MIPS option of the same name is not renamed.
--- Makefile | 2 +- README | 8 +++++++- arch/arm/cpu/arm1136/start.S | 6 +++--- arch/arm/cpu/arm720t/start.S | 2 +- arch/arm/cpu/arm920t/at91/lowlevel_init.S | 4 ++-- arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S | 4 ++-- arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 4 ++-- arch/arm/cpu/arm920t/start.S | 6 +++--- arch/arm/cpu/arm925t/start.S | 2 +- arch/arm/cpu/arm926ejs/at91/Makefile | 2 +- arch/arm/cpu/arm926ejs/davinci/Makefile | 2 +- arch/arm/cpu/arm926ejs/orion5x/Makefile | 2 +- arch/arm/cpu/arm926ejs/start.S | 6 +++--- arch/arm/cpu/arm946es/start.S | 4 ++-- arch/arm/cpu/arm_intcm/start.S | 4 ++-- arch/arm/cpu/armv7/start.S | 2 +- arch/arm/cpu/lh7a40x/start.S | 2 +- arch/arm/cpu/s3c44b0/start.S | 2 +- arch/arm/cpu/sa1100/start.S | 2 +- board/ns9750dev/lowlevel_init.S | 6 +++--- include/common.h | 2 +- include/configs/SMN42.h | 2 +- include/configs/a320evb.h | 2 +- include/configs/afeb9260.h | 2 +- include/configs/armadillo.h | 2 +- include/configs/aspenite.h | 2 +- include/configs/at91cap9adk.h | 2 +- include/configs/at91rm9200dk.h | 12 ++++++------ include/configs/at91rm9200ek.h | 6 +++--- include/configs/at91sam9260ek.h | 2 +- include/configs/at91sam9261ek.h | 2 +- include/configs/at91sam9263ek.h | 4 ++-- include/configs/at91sam9m10g45ek.h | 2 +- include/configs/at91sam9rlek.h | 2 +- include/configs/cmc_pu2.h | 4 ++-- include/configs/colibri_pxa270.h | 2 +- include/configs/cpuat91.h | 6 +++--- include/configs/csb637.h | 4 ++-- include/configs/da830evm.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/davinci_dm355evm.h | 2 +- include/configs/davinci_dm355leopard.h | 2 +- include/configs/davinci_dm365evm.h | 2 +- include/configs/davinci_dm6467evm.h | 2 +- include/configs/davinci_dvevm.h | 6 +++--- include/configs/davinci_schmoogie.h | 2 +- include/configs/davinci_sffsdr.h | 2 +- include/configs/davinci_sonata.h | 6 +++--- include/configs/dkb.h | 2 +- include/configs/dnp1110.h | 2 +- include/configs/dockstar.h | 2 +- include/configs/ea20.h | 2 +- include/configs/evb4510.h | 2 +- include/configs/gcplus.h | 4 ++-- include/configs/guruplug.h | 2 +- include/configs/hawkboard.h | 2 +- include/configs/integratorap.h | 2 +- include/configs/integratorcp.h | 6 +++--- include/configs/kb9202.h | 2 +- include/configs/km_arm.h | 2 +- include/configs/lpc2292sodimm.h | 2 +- include/configs/meesc.h | 2 +- include/configs/mp2usb.h | 4 ++-- include/configs/mv88f6281gtw_ge.h | 2 +- include/configs/mx31pdk.h | 2 +- include/configs/nhk8815.h | 2 +- include/configs/openrd_base.h | 2 +- include/configs/otc570.h | 2 +- include/configs/pm9261.h | 2 +- include/configs/pm9263.h | 2 +- include/configs/pm9g45.h | 2 +- include/configs/pxa255_idp.h | 2 +- include/configs/rd6281a.h | 2 +- include/configs/sbc2410x.h | 2 +- include/configs/sbc35_a9g20.h | 2 +- include/configs/shannon.h | 2 +- include/configs/sheevaplug.h | 2 +- include/configs/tegra2-common.h | 2 +- include/configs/tny_a9260.h | 2 +- include/configs/top9000.h | 2 +- include/configs/tx25.h | 2 +- include/configs/zipitz2.h | 2 +- 82 files changed, 121 insertions(+), 115 deletions(-)
Makefile +1 -1
@@ -1071,7 +1071,7 @@ mx31pdk_nand_config : unconfig @if [ -n "$(findstring _nand_,$@)" ]; then \ echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h; \ else \ - echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h; \ + echo "#define CONFIG_SKIP_CPU_INIT_CRIT" >> $(obj)include/config.h; \ fi @$(MKCONFIG) -n $@ -a mx31pdk arm arm1136 mx31pdk freescale mx31
README +7 -1
@@ -2892,7 +2892,7 @@ Low Level (hardware related) configuration options: globally (CONFIG_CMD_MEM). - CONFIG_SKIP_LOWLEVEL_INIT - [ARM only] If this variable is defined, then certain + If this variable is defined, then certain low level initializations (like setting up the memory controller) are omitted and/or U-Boot does not relocate itself into RAM.
@@ -2902,6 +2902,12 @@ Low Level (hardware related) configuration options: other boot loader or by a debugger which performs these initializations itself. +- CONFIG_SKIP_CPU_INIT_CRIT + [ARM only] If this variable is defined, then the CPU + is assumed to be initialized when U-Boot starts. For + most CPUs this also implies low level initialization + is skipped (see CONFIG_SKIP_LOWLEVEL_INIT). + - CONFIG_PRELOADER Modifies the behaviour of start.S when compiling a loader that is executed before the actual U-Boot. E.g. when
arch/arm/cpu/arm1136/start.S +3 -3
@@ -157,7 +157,7 @@ next: bl cpy_clk_code /* put dpll adjust code behind vectors */ #endif /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -300,7 +300,7 @@ _dynsym_start_ofs: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* * flush v4 I/D caches
@@ -327,7 +327,7 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ #ifndef CONFIG_PRELOADER /*
arch/arm/cpu/arm720t/start.S +1 -1
@@ -131,7 +131,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
arch/arm/cpu/arm920t/at91/lowlevel_init.S +2 -2
@@ -27,7 +27,7 @@ #include <config.h> -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #include <asm/arch/hardware.h> #include <asm/arch/at91_mc.h>
@@ -161,4 +161,4 @@ SMRDATA1: .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S +2 -2
@@ -30,7 +30,7 @@ #include <config.h> #include <version.h> -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT /* * some parameters for the board *
@@ -166,4 +166,4 @@ SMRDATA1: .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +2 -2
@@ -26,7 +26,7 @@ #include <version.h> #include <asm/arch/platform.h> -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT /* *************************************************************************
@@ -202,4 +202,4 @@ nobutton: add ip, ip, #0x02000000 /* this is a hack */ mov pc, lr /* all done, return */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
arch/arm/cpu/arm920t/start.S +3 -3
@@ -178,7 +178,7 @@ copyex: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -324,7 +324,7 @@ _dynsym_start_ofs: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* * flush v4 I/D caches
@@ -354,7 +354,7 @@ cpu_init_crit: mov lr, ip mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* *************************************************************************
arch/arm/cpu/arm925t/start.S +1 -1
@@ -172,7 +172,7 @@ poll1: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
arch/arm/cpu/arm926ejs/at91/Makefile +1 -1
@@ -41,7 +41,7 @@ COBJS-y += cpu.o COBJS-y += reset.o COBJS-y += timer.o -ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_SKIP_CPU_INIT_CRIT SOBJS-y := lowlevel_init.o endif
arch/arm/cpu/arm926ejs/davinci/Makefile +1 -1
@@ -36,7 +36,7 @@ COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o SOBJS = reset.o -ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_SKIP_CPU_INIT_CRIT SOBJS += lowlevel_init.o endif
arch/arm/cpu/arm926ejs/orion5x/Makefile +1 -1
@@ -33,7 +33,7 @@ COBJS-y = cpu.o COBJS-y += dram.o COBJS-y += timer.o -ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_SKIP_CPU_INIT_CRIT SOBJS := lowlevel_init.o endif
arch/arm/cpu/arm926ejs/start.S +3 -3
@@ -171,7 +171,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -315,7 +315,7 @@ _dynsym_start_ofs: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* * flush v4 I/D caches
@@ -341,7 +341,7 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ #ifndef CONFIG_PRELOADER /*
arch/arm/cpu/arm946es/start.S +2 -2
@@ -143,7 +143,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -284,7 +284,7 @@ _dynsym_start_ofs: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* * flush v4 I/D caches
arch/arm/cpu/arm_intcm/start.S +2 -2
@@ -139,7 +139,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
@@ -284,7 +284,7 @@ _dynsym_start_ofs: ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT cpu_init_crit: /* arm_int_generic assumes the ARM boot monitor, or user software, * has initialized the platform
arch/arm/cpu/armv7/start.S +1 -1
@@ -139,7 +139,7 @@ next: #endif /* NAND Boot */ #endif /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
arch/arm/cpu/lh7a40x/start.S +1 -1
@@ -152,7 +152,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
arch/arm/cpu/s3c44b0/start.S +1 -1
@@ -118,7 +118,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit /* * before relocating, we have to setup RAM timing
arch/arm/cpu/sa1100/start.S +1 -1
@@ -128,7 +128,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT bl cpu_init_crit #endif
board/ns9750dev/lowlevel_init.S +3 -3
@@ -34,7 +34,7 @@ #include <version.h> #if defined(CONFIG_NS9750DEV) -# ifndef CONFIG_SKIP_LOWLEVEL_INIT +# ifndef CONFIG_SKIP_CPU_INIT_CRIT # include <./ns9750_sys.h> # include <./ns9750_mem.h> # endif
@@ -74,7 +74,7 @@ _PHYS_FLASH: _CAS_LATENCY: .word 0x00022000 @ for CAS2 latency -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT .globl lowlevel_init lowlevel_init:
@@ -295,4 +295,4 @@ _AHB_MONITOR_START: NS9750_SYS_AHB_MON_BATC_GEN_IRQ) _AHB_MONITOR_END: -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */
include/common.h +1 -1
@@ -737,7 +737,7 @@ int cpu_release(int nr, int argc, char * const argv[]);#ifdef CONFIG_INIT_CRITICAL #error CONFIG_INIT_CRITICAL is deprecated! -#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. +#error Read section CONFIG_SKIP_CPU_INIT_CRIT in README.#endif #define ARRAY_SIZE (x) (sizeof(x) / sizeof((x)[0]))
include/configs/SMN42.h +1 -1
@@ -30,7 +30,7 @@* If we are developing, we might want to start u-boot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT/* * High Level Configuration Options
include/configs/a320evb.h +1 -1
@@ -29,7 +29,7 @@*/ #undef CONFIG_USE_IRQ/* we don't need IRQ/FIQ stuff */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT/*----------------------------------------------------------------------- * Timer
include/configs/afeb9260.h +1 -1
@@ -41,7 +41,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/armadillo.h +1 -1
@@ -34,7 +34,7 @@* If we are developing, we might want to start armboot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT/* * High Level Configuration Options
include/configs/aspenite.h +1 -1
@@ -38,7 +38,7 @@#define CONFIG_ARMADA100 1/* SOC Family Name */ #define CONFIG_ARMADA168 1/* SOC Used on this Board */ #define CONFIG_MACH_ASPENITE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ /* * There is no internal RAM in ARMADA100, using DRAM
include/configs/at91cap9adk.h +1 -1
@@ -43,7 +43,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/at91rm9200dk.h +6 -6
@@ -44,7 +44,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1/* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
@@ -69,7 +69,7 @@#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003/* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000/* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0/* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* * Size of malloc() pool */
@@ -160,19 +160,19 @@#define CONFIG_ENV_SIZE 0x2000/* 0x8000 */ #else #define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000)/* between boot.bin and u-boot.bin.gz */ #define CONFIG_ENV_SIZE 0x2000/* 0x8000 */ #else #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)/* after u-boot.bin */ #define CONFIG_ENV_SIZE 0x10000/* sectors are 64K here */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ #endif /* CONFIG_ENV_IS_IN_DATAFLASH */ #define CONFIG_SYS_LOAD_ADDR 0x21000000/* default load address */ -#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_BOOT_SIZE 0x6000/* 24 KBytes */ #define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)#define CONFIG_SYS_U_BOOT_SIZE 0x10000/* 64 KBytes */
@@ -180,7 +180,7 @@#define CONFIG_SYS_BOOT_SIZE 0x00/* 0 KBytes */ #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1#define CONFIG_SYS_U_BOOT_SIZE 0x60000/* 384 KBytes */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
include/configs/at91rm9200ek.h +3 -3
@@ -40,7 +40,7 @@* initialisation was done by some preloader */ #ifdef CONFIG_RAMBOOT -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_TEXT_BASE 0x20100000#else #define CONFIG_SYS_TEXT_BASE 0x10000000
@@ -87,7 +87,7 @@/* * LowLevel Init */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
@@ -113,7 +113,7 @@#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003/* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000/* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0/* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* * Hardware drivers
include/configs/at91sam9260ek.h +1 -1
@@ -48,7 +48,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/at91sam9261ek.h +1 -1
@@ -46,7 +46,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/at91sam9263ek.h +2 -2
@@ -42,7 +42,7 @@#define CONFIG_INITRD_TAG 1#ifndef CONFIG_SYS_USE_BOOT_NORFLASH -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #endif /*
@@ -144,7 +144,7 @@"cp.b ${load_addr} ${monitor_base} ${filesize};" \ "protect on ${monitor_base} +${filesize}\0" -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define MASTER_PLL_MUL 171#define MASTER_PLL_DIV 14#define MASTER_PLL_OUT 3
include/configs/at91sam9m10g45ek.h +1 -1
@@ -46,7 +46,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/at91sam9rlek.h +1 -1
@@ -43,7 +43,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/cmc_pu2.h +2 -2
@@ -43,7 +43,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1/* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
@@ -68,7 +68,7 @@#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003/* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000/* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0/* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* * Size of malloc() pool
include/configs/colibri_pxa270.h +1 -1
@@ -30,7 +30,7 @@#undef BOARD_LATE_INIT#undef CONFIG_USE_IRQ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT/* * Environment settings
include/configs/cpuat91.h +3 -3
@@ -27,7 +27,7 @@#define _CONFIG_CPUAT91_H#ifdef CONFIG_CPUAT91_RAM -#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SKIP_CPU_INIT_CRIT 1#else #define CONFIG_BOOTDELAY 1#endif
@@ -48,7 +48,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1/* flash */ #define CONFIG_SYS_MC_PUIA_VAL 0x00000000
@@ -78,7 +78,7 @@#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003/* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000/* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0/* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* define one of these to choose the DBGU, USART0 or USART1 as console */ #define CONFIG_AT91RM9200_USART 1
include/configs/csb637.h +2 -2
@@ -44,7 +44,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1/* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
@@ -69,7 +69,7 @@#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003/* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000/* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0/* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* * Size of malloc() pool */
include/configs/da830evm.h +1 -1
@@ -40,7 +40,7 @@#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)#define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_TEXT_BASE 0xc1080000/*
include/configs/da850evm.h +1 -1
@@ -40,7 +40,7 @@#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)#define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_TEXT_BASE 0xc1080000/*
include/configs/davinci_dm355evm.h +1 -1
@@ -23,7 +23,7 @@/* Spectrum Digital TMS320DM355 EVM board */ #define DAVINCI_DM355EVM -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is a 3rd stage loader */ #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_DISPLAY_CPUINFO
include/configs/davinci_dm355leopard.h +1 -1
@@ -22,7 +22,7 @@#define DAVINCI_DM355LEOPARD -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is a 3rd stage loader */ #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_DISPLAY_CPUINFO
include/configs/davinci_dm365evm.h +1 -1
@@ -23,7 +23,7 @@/* Spectrum Digital TMS320DM365 EVM board */ #define DAVINCI_DM365EVM -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is a 3rd stage loader */ #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ #define CONFIG_SYS_CONSOLE_INFO_QUIET
include/configs/davinci_dm6467evm.h +1 -1
@@ -26,7 +26,7 @@#define CONFIG_SYS_USE_NAND #define CONFIG_SYS_NAND_SMALLPAGE -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* SoC Configuration */ #define CONFIG_ARM926EJS /* arm926ejs CPU */
include/configs/davinci_dvevm.h +3 -3
@@ -133,7 +133,7 @@#define CONFIG_ENV_SECT_SIZE 2048/* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10)/* 128 KiB */ #endif -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SYS_NAND_BASE 0x02000000#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_HW_ECC
@@ -141,9 +141,9 @@#define CONFIG_ENV_OFFSET 0x0/* Block 0--not used by bootcode */ #elif defined(CONFIG_SYS_USE_NOR )#ifdef CONFIG_NOR_UART_BOOT -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #else -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT#endif #define CONFIG_ENV_IS_IN_FLASH #undef CONFIG_SYS_NO_FLASH
include/configs/davinci_schmoogie.h +1 -1
@@ -87,7 +87,7 @@#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048/* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10)/* 128 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SYS_NAND_BASE 0x02000000#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1/* Max number of NAND devices */
include/configs/davinci_sffsdr.h +1 -1
@@ -82,7 +82,7 @@#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048/* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10)/* 128 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SYS_NAND_BASE 0x02000000#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1/* Max number of NAND devices */
include/configs/davinci_sonata.h +3 -3
@@ -121,16 +121,16 @@#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 512/* Env sector Size */ #define CONFIG_ENV_SIZE (16 << 10)/* 16 KiB */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SYS_NAND_BASE 0x02000000#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1/* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0/* Block 0--not used by bootcode */ #elif defined(CONFIG_SYS_USE_NOR )#ifdef CONFIG_NOR_UART_BOOT -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* U-Boot is loaded by a bootloader */ #else -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT#endif #define CONFIG_ENV_IS_IN_FLASH #undef CONFIG_SYS_NO_FLASH
include/configs/dkb.h +1 -1
@@ -36,7 +36,7 @@#define CONFIG_SHEEVA_88SV331xV5 1/* CPU Core subversion */ #define CONFIG_PANTHEON 1/* SOC Family Name */ #define CONFIG_MACH_TTC_DKB 1/* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)#define CONFIG_NR_DRAM_BANKS_MAX 2
include/configs/dnp1110.h +1 -1
@@ -31,7 +31,7 @@* If we are developing, we might want to start armboot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SKIP_CPU_INIT_CRIT 1/* * High Level Configuration Options
include/configs/dockstar.h +1 -1
@@ -40,7 +40,7 @@#define CONFIG_KIRKWOOD 1/* SOC Family Name */ #define CONFIG_KW88F6281 1/* SOC Name */ #define CONFIG_MACH_DOCKSTAR /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ /* * Commands configuration
include/configs/ea20.h +1 -1
@@ -41,7 +41,7 @@#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)#define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_TEXT_BASE 0xc1080000/*
include/configs/evb4510.h +1 -1
@@ -32,7 +32,7 @@* * Also swap the flash1 and flash2 addresses during debug. * -* #define CONFIG_SKIP_LOWLEVEL_INIT +* #define CONFIG_SKIP_CPU_INIT_CRIT */ /*
include/configs/gcplus.h +2 -2
@@ -36,9 +36,9 @@* e.g. bootp/tftp download of the kernel is a far more convenient * when testing new kernels on this target. However the ADS GCPlus Linux * boot ROM leaves the MMU enabled when it passes control to U-Boot. So -* we use lowlevel_init (!CONFIG_SKIP_LOWLEVEL_INIT) to remedy that problem. +* we use lowlevel_init (!CONFIG_SKIP_CPU_INIT_CRIT) to remedy that problem. */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT/* * High Level Configuration Options
include/configs/guruplug.h +1 -1
@@ -37,7 +37,7 @@#define CONFIG_KIRKWOOD 1/* SOC Family Name */ #define CONFIG_KW88F6281 1/* SOC Name */ #define CONFIG_MACH_GURUPLUG /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ /* * Commands configuration
include/configs/hawkboard.h +1 -1
@@ -39,7 +39,7 @@#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)#define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_BOARD_EARLY_INIT_F #if defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_UART_U_BOOT )
include/configs/integratorap.h +1 -1
@@ -44,7 +44,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_MISC_INIT_R 1/* call misc_init_r during start up */ -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_CM_INIT 1#define CONFIG_CM_REMAP 1#undef CONFIG_CM_SPD_DETECT
include/configs/integratorcp.h +3 -3
@@ -206,12 +206,12 @@ SIB at Block62 End Block62 address 0x24f80000/* * The ARM boot monitor initializes the board. * However, the default U-Boot code also performs the initialization. -* If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT +* If desired, this can be prevented by defining SKIP_CPU_INIT_CRIT * - see documentation supplied with board for details of how to choose the * image to run at reset/power up * e.g. whether the ARM Boot Monitor runs before U-Boot -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT */
@@ -235,7 +235,7 @@ SIB@Block62 End Block62 address 0x24f80000#include "armcoremodule.h" /* -* If CONFIG_SKIP_LOWLEVEL_INIT is not defined & +* If CONFIG_SKIP_CPU_INIT_CRIT is not defined & * the core module has a CM_INIT register * then the U-Boot initialisation code will * e.g. ARM Boot Monitor or pre-loader is repeated once
include/configs/kb9202.h +1 -1
@@ -52,7 +52,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_LONGHELP
include/configs/km_arm.h +1 -1
@@ -46,7 +46,7 @@#undef CONFIG_BOOTCOUNT_LIMIT#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #undef CONFIG_KIRKWOOD_PCIE_INIT/* Disable PCIE Port0 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
include/configs/lpc2292sodimm.h +1 -1
@@ -30,7 +30,7 @@* If we are developing, we might want to start u-boot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT/* * High Level Configuration Options
include/configs/meesc.h +1 -1
@@ -47,7 +47,7 @@#define CONFIG_REVISION_TAG 1#undef CONFIG_USE_IRQ/* don't need IRQ/FIQ stuff */ -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_MISC_INIT_R /* Call misc_init_r */ #define CONFIG_ARCH_CPU_INIT
include/configs/mp2usb.h +2 -2
@@ -48,7 +48,7 @@#define CONFIG_INITRD_TAG 1#define CONFIG_SYS_ATMEL_PLL_INIT_BUG 1 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1/* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
@@ -73,7 +73,7 @@#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003/* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000/* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0/* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_SKIP_CPU_INIT_CRIT */ /* * Size of malloc() pool
include/configs/mv88f6281gtw_ge.h +1 -1
@@ -37,7 +37,7 @@#define CONFIG_KIRKWOOD 1/* SOC Family Name */ #define CONFIG_KW88F6281 1/* SOC Name */ #define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ /* * Commands configuration
include/configs/mx31pdk.h +1 -1
@@ -46,7 +46,7 @@#define CONFIG_INITRD_TAG 1#if defined(CONFIG_NAND_U_BOOT ) && !defined(CONFIG_NAND_SPL ) -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #endif /*
include/configs/nhk8815.h +1 -1
@@ -33,7 +33,7 @@#define CONFIG_NOMADIK_8815 /* cpu variant */ #define CONFIG_NOMADIK_NHK8815 /* board variant */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* we have already been loaded to RAM */ /* commands */ #include <config_cmd_default.h>
include/configs/openrd_base.h +1 -1
@@ -42,7 +42,7 @@#define CONFIG_KIRKWOOD 1/* SOC Family Name */ #define CONFIG_KW88F6281 1/* SOC Name */ #define CONFIG_MACH_OPENRD_BASE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ /* * Commands configuration
include/configs/otc570.h +1 -1
@@ -47,7 +47,7 @@#define CONFIG_REVISION_TAG 1#undef CONFIG_USE_IRQ/* don't need IRQ/FIQ stuff */ -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_MISC_INIT_R 1/* Call misc_init_r */ #define CONFIG_ARCH_CPU_INIT
include/configs/pm9261.h +1 -1
@@ -153,7 +153,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT/* * Hardware drivers
include/configs/pm9263.h +1 -1
@@ -162,7 +162,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT#define CONFIG_USER_LOWLEVEL_INIT 1/*
include/configs/pm9g45.h +1 -1
@@ -48,7 +48,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/pxa255_idp.h +1 -1
@@ -41,7 +41,7 @@* If we are developing, we might want to start U-Boot from RAM * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT/* define for developing */ +#undef CONFIG_SKIP_CPU_INIT_CRIT/* define for developing */ #define CONFIG_SYS_TEXT_BASE 0x0/*
include/configs/rd6281a.h +1 -1
@@ -37,7 +37,7 @@#define CONFIG_KIRKWOOD 1/* SOC Family Name */ #define CONFIG_KW88F6281 1/* SOC Name */ #define CONFIG_MACH_RD6281A /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ /* * Commands configuration
include/configs/sbc2410x.h +1 -1
@@ -37,7 +37,7 @@* If we are developing, we might want to start armboot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_SKIP_LOWLEVEL_INIT/* undef for developing */ +#undef CONFIG_SKIP_CPU_INIT_CRIT/* undef for developing */ /* * High Level Configuration Options
include/configs/sbc35_a9g20.h +1 -1
@@ -53,7 +53,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/shannon.h +1 -1
@@ -33,7 +33,7 @@* But U-Boot still relocates itself into RAM */ #define CONFIG_INFERNO /* we are using the inferno bootldr */ -#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SKIP_CPU_INIT_CRIT 1/* * High Level Configuration Options
include/configs/sheevaplug.h +1 -1
@@ -37,7 +37,7 @@#define CONFIG_KIRKWOOD 1/* SOC Family Name */ #define CONFIG_KW88F6281 1/* SOC Name */ #define CONFIG_MACH_SHEEVAPLUG /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SKIP_CPU_INIT_CRIT /* disable board lowlevel_init */ /* * Commands configuration
include/configs/tegra2-common.h +1 -1
@@ -42,7 +42,7 @@#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SKIP_RELOCATE_UBOOT -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
include/configs/tny_a9260.h +1 -1
@@ -62,7 +62,7 @@#define CONFIG_SETUP_MEMORY_TAGS 1#define CONFIG_INITRD_TAG 1 -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT /* * Hardware drivers
include/configs/top9000.h +1 -1
@@ -77,7 +77,7 @@#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO #define CONFIG_AT91RESET_EXTRST /* assert external reset */
include/configs/tx25.h +1 -1
@@ -51,7 +51,7 @@#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0#else -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_CPU_INIT_CRIT #endif #define CONFIG_DISPLAY_CPUINFO
include/configs/zipitz2.h +1 -1
@@ -31,7 +31,7 @@#undef BOARD_LATE_INIT#undef CONFIG_USE_IRQ -#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_CPU_INIT_CRIT/* * Environment settings
Signature · 1 line
1.7.2.3
PATCH 5/9 ARM: Rename CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT
Dear Michael Spang,
Quoted 5 lines · In message <[email protected]> you…
For ARM, the
CONFIG_SKIP_LOWLEVEL_INIToption implies that thecpu_init_critandlowlevel_initassembly functions are skipped. We may want to skip onlylowlevel_init, so rename the option that skips both toCONFIG_SKIP_CPU_INIT_CRIT. The MIPS option of the same name is not renamed.
This is an inconsistency between architectures which I dislike.
Also, what in case we should want to skip only cpu_init_crit and not lowlevel_init? If we need to handle these separately, then we need 2 CONFIG options.
Best regards,
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Plan to throw one away. You will anyway."
- Fred Brooks, "The Mythical Man Month"PATCH 5/9 ARM: Rename CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT
Quoted 9 lines · Wolfgang Denk
Dear Michael Spang,
Quoted 5 lines · In message <[email protected]> you…
For ARM, the
CONFIG_SKIP_LOWLEVEL_INIToption implies that thecpu_init_critandlowlevel_initassembly functions are skipped. We may want to skip onlylowlevel_init, so rename the option that skips both toCONFIG_SKIP_CPU_INIT_CRIT. The MIPS option of the same name is not renamed.
Quoted 5 lines
This is an inconsistency between architectures which I dislike.
Also, what in case we should want to skip only
cpu_init_critand notlowlevel_init? If we need to handle these separately, then we need 2 CONFIG options.
The CPU initialization is idempotent, so I can't think of a reason why it would be required to skip it. So, we might be able to change CONFIG_SKIP_CPU_INIT_CRIT to CONFIG_SKIP_LOWLEVEL_INIT in most cases. I'm just hesitant to do so because I don't have a variety of boards to test on.
Michael
PATCH 6/9 ARM: Implement CONFIG_SKIP_LOWLEVEL_INIT for arm926ej-s
In reply to Michael SpangThe TS-7800 needs to skip SDRAM initialization since it loads from RAM, but the CPU should still be initialized to the correct state. Thus we add an #ifdef around the call to the lowlevel_init function.
--- arch/arm/cpu/arm926ejs/at91/Makefile | 2 ++ arch/arm/cpu/arm926ejs/davinci/Makefile | 2 ++ arch/arm/cpu/arm926ejs/orion5x/Makefile | 2 ++ arch/arm/cpu/arm926ejs/start.S | 3 +++ 4 files changed, 9 insertions(+), 0 deletions(-)
arch/arm/cpu/arm926ejs/at91/Makefile +2 -0
@@ -42,8 +42,10 @@ COBJS-y += reset.o COBJS-y += timer.o ifndef CONFIG_SKIP_CPU_INIT_CRIT +ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS-y := lowlevel_init.o endif +endif SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
arch/arm/cpu/arm926ejs/davinci/Makefile +2 -0
@@ -37,8 +37,10 @@ COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o SOBJS = reset.o ifndef CONFIG_SKIP_CPU_INIT_CRIT +ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS += lowlevel_init.o endif +endif SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
arch/arm/cpu/arm926ejs/orion5x/Makefile +2 -0
@@ -34,8 +34,10 @@ COBJS-y += dram.o COBJS-y += timer.o ifndef CONFIG_SKIP_CPU_INIT_CRIT +ifndef CONFIG_SKIP_LOWLEVEL_INIT SOBJS := lowlevel_init.o endif +endif SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
arch/arm/cpu/arm926ejs/start.S +3 -0
@@ -334,12 +334,15 @@ cpu_init_crit: orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_CPU_INIT_CRIT */
Signature · 1 line
1.7.2.3
PATCH 6/9 ARM: Implement CONFIG_SKIP_LOWLEVEL_INIT for arm926ej-s
Dear Michael Spang,
Quoted 5 lines · In message <[email protected]> you…
The TS-7800 needs to skip SDRAM initialization since it loads from RAM, but the CPU should still be initialized to the correct state. Thus we add an #ifdef around the call to the
lowlevel_initfunction.Signed-off-by Michael Spang <[email protected]>
How can the SDRAM be initialized when the CPU is not?
Best regards,
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Work 8 hours, sleep 8 hours; but not the same 8 hours.
PATCH 6/9 ARM: Implement CONFIG_SKIP_LOWLEVEL_INIT for arm926ej-s
Hi Wolfgang et al.,
(replying both to 5/9 and 6/9 here)
Le 25/04/2011 01:55, Wolfgang Denk a ?crit :
Quoted 1 line
This is an inconsistency between architectures which I dislike.
Then these two config options could be defined for other architectures as well.
Quoted 3 lines
Also, what in case we should want to skip only
cpu_init_critand notlowlevel_init? If we need to handle these separately, then we need 2 CONFIG options.
Agreed this complete separation could be useful in case U-Boot is not the code executed on startup, and this startup code does the CPU initialization but leaves the rest to U-Boot for commodity.
Quoted 1 line
How can the SDRAM be initialized when the CPU is not?
Debugging sessions come to mind, where the debugger resets the target and initializes SDRAM to load the target code. I've also seen cases on multiple-core ICs where an ARM core starts with SDRAM access already working, but U-Boot was not involved.
The idea is that during board bring-up, rather than have people try and neutralize some code in assembly language startup files, they just temporarily define the configuration options CONFIG_SKIP_* in their board's config header file (and, for those boards that have an IPL of some sort before U-Boot, they keep the relevant CONFIG_SKIP_* there once debugged).
Quoted 3 lines
Best regards,
Wolfgang Denk
Amicalement,
Signature · 1 line
Albert.
PATCH 6/9 ARM: Implement CONFIG_SKIP_LOWLEVEL_INIT for arm926ej-s
In reply to Wolfgang DenkQuoted 10 lines · Wolfgang Denk
Dear Michael Spang,
Quoted 5 lines · In message <[email protected]> you…
The TS-7800 needs to skip SDRAM initialization since it loads from RAM, but the CPU should still be initialized to the correct state. Thus we add an #ifdef around the call to the
lowlevel_initfunction.Signed-off-by Michael Spang <[email protected]>How can the SDRAM be initialized when the CPU is not?
It is already initialized, but even if the state matches what U-Boot expects now, I'm not confident the desired settings will never change. So I think it is best to just run U-Boot's initialization anyway.
Michael
PATCH 7/9 Add board support for TS-7800
In reply to Michael SpangThe TS-7800 is an Orion5x implementation by Technologic Systems.
--- MAKEALL | 1 + board/technologic/ts7800/Makefile | 46 +++++++++++ board/technologic/ts7800/ts7800.c | 36 +++++++++ boards.cfg | 1 + include/configs/ts7800.h | 152 +++++++++++++++++++++++++++++++++++++ 5 files changed, 236 insertions(+), 0 deletions(-) create mode 100644 board/technologic/ts7800/Makefile create mode 100644 board/technologic/ts7800/ts7800.c create mode 100644 include/configs/ts7800.h
MAKEALL +1 -0
@@ -344,6 +344,7 @@ LIST_ARM9=" \ edb9315 \ edb9315a \ edminiv2 \ + ts7800 \ guruplug \ imx27lite \ jadecpu \
board/technologic/ts7800/Makefile new file +46 -0
46 lines not on this page · raw message
board/technologic/ts7800/ts7800.c new file +36 -0
@@ -0,0 +1,36 @@ +/* +* Copyright (C) 2010-2011 Michael Spang <[email protected]> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +* MA 02110-1301 USA +*/ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR ; + +int board_init (void ) +{ +/* Technologic's MBR uses machine type 526, however the mainline +machine type is 1652. Set the machtype environment variable +to 526 to boot Technologic kernels. */ + gd->bd->bi_arch_number =MACH_TYPE_TS78XX ; + gd->bd->bi_boot_params =0x100 ; + +return 0 ; +}
boards.cfg +1 -0
@@ -106,6 +106,7 @@ magnesium arm arm926ejs imx27lite logicpd omap5912osk arm arm926ejs - ti omap edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon +ts7800 arm arm926ejs - technologic orion5x ca9x4_ct_vxp arm armv7 vexpress armltd efikamx arm armv7 efikamx - mx5 mx51evk arm armv7 mx51evk freescale mx5
include/configs/ts7800.h new file +152 -0
152 lines not on this page · raw message
Signature · 1 line
1.7.2.3
PATCH 7/9 Add board support for TS-7800
Dear Michael Spang,
Quoted 19 lines · In message <[email protected]> you…
The TS-7800 is an Orion5x implementation by Technologic Systems.
Signed-off-by Michael Spang <[email protected]>--- MAKEALL | 1 + board/technologic/ts7800/Makefile | 46 +++++++++++ board/technologic/ts7800/ts7800.c | 36 +++++++++ boards.cfg | 1 + include/configs/ts7800.h | 152 +++++++++++++++++++++++++++++++++++++ 5 files changed, 236 insertions(+), 0 deletions(-) create mode 100644 board/technologic/ts7800/Makefile create mode 100644 board/technologic/ts7800/ts7800.c create mode 100644 include/configs/ts7800.hMAKEALL +0
-0
MAKEALL LIST_ARM9=" \ · line 350
Quoted 7 lines
MAKEALL +1
-0@@ -344,6 +344,7 @@ LIST_ARM9=" \ edb9315 \ edb9315a \ edminiv2 \ + ts7800 \ guruplug \ imx27lite \ jadecpu \
Boards don;t get added to MAKEALL any more; they will get picked automatically from boards.cfg.
...
Quoted 1 line
+#define
CONFIG_ENV_IS_NOWHERE1
Please remove the '1' from all defines that select a feature only, i. e. that don;t actually care abut a specific numeric value.
Best regards,
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Vulcans do not approve of violence. -- Spock, "Journey to Babel", stardate 3842.4
PATCH 7/9 Add board support for TS-7800
Quoted 33 lines · Wolfgang Denk
Dear Michael Spang,
Quoted 19 lines · In message <[email protected]> you…
The TS-7800 is an Orion5x implementation by Technologic Systems.
Signed-off-by Michael Spang <[email protected]>---
?MAKEALL ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?1 + ?board/technologic/ts7800/Makefile | ? 46 +++++++++++ ?board/technologic/ts7800/ts7800.c | ? 36 +++++++++ ?boards.cfg ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 + ?include/configs/ts7800.h ? ? ? ? ?| ?152 +++++++++++++++++++++++++++++++++++++?5 files changed, 236 insertions(+), 0 deletions(-) ?create mode 100644 board/technologic/ts7800/Makefile ?create mode 100644
board/technologic/ts7800/ts7800.c?create mode 100644include/configs/ts7800.hMAKEALL +0
-0MAKEALL LIST_ARM9=" ? ? ? ? ? ? ? ? ? ? ? \ · line 350
Quoted 7 lines
MAKEALL +1
-0@@ -344,6 +344,7 @@ LIST_ARM9=" ? ? ? ? ? ? ? ? ? ? ? \ ? ? ? edb9315 ? ? ? ? ? ? ? ? \ ? ? ? edb9315a ? ? ? ? ? ? ? ?\ ? ? ? edminiv2 ? ? ? ? ? ? ? ?\ + ? ? ts7800 ? ? ? ? ? ? ? ? ?\ ? ? ? guruplug ? ? ? ? ? ? ? ?\ ? ? ? imx27lite ? ? ? ? ? ? ? \ ? ? ? jadecpu ? ? ? ? ? ? ? ? \Boards don;t get added to MAKEALL any more; they will get picked automatically from boards.cfg.
Quoted 5 lines
...
Quoted 1 line
+#define
CONFIG_ENV_IS_NOWHERE? ? ? ?1Please remove the '1' from all defines that select a feature only, i. e. that don;t actually care abut a specific numeric value.
Ok I'll drop the change to MAKEALL and update the #defines.
Michael
PATCH 8/9 Add NAND support for TS-7800
In reply to Michael SpangThe NAND control functions were written by Alexander Clouter and copied here from Linux.
--- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ts7800_nand.c | 68 ++++++++++++++++++++++++++++++++++++++++ include/configs/ts7800.h | 47 ++++++++++++++++++++++++++-- 3 files changed, 113 insertions(+), 3 deletions(-) create mode 100644 drivers/mtd/nand/ts7800_nand.c
drivers/mtd/nand/Makefile +1 -0
@@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_TS7800) += ts7800_nand.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif
drivers/mtd/nand/ts7800_nand.c new file +68 -0
68 lines not on this page · raw message
include/configs/ts7800.h +44 -3
75 lines not on this page · raw message
Signature · 1 line
1.7.2.3
PATCH 8/9 Add NAND support for TS-7800
Quoted 10 lines · On Thu, 17 Mar 2011 15:47:02 -0400 Michael Spang <[email protected]>…
The NAND control functions were written by Alexander Clouter and copied here from Linux.
Signed-off-by Michael Spang <[email protected]>--- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ts7800_nand.c | 68 ++++++++++++++++++++++++++++++++++++++++ include/configs/ts7800.h | 47 ++++++++++++++++++++++++++-- 3 files changed, 113 insertions(+), 3 deletions(-) create mode 100644 drivers/mtd/nand/ts7800_nand.c
-Scott
PATCH 8/9 Add NAND support for TS-7800
In reply to Michael SpangDear Michael Spang,
Quoted 2 lines · In message <[email protected]> you…
The NAND control functions were written by Alexander Clouter and copied here from Linux.
Please provide exact reference, see bullet # 4 at
http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign
drivers/mtd/nand/Makefile COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o · line 54
Quoted 11 lines
drivers/mtd/nand/Makefile +1
-0@@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_TS7800) += ts7800_nand.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif
Please keep the list sorted.
Best regards,
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Given a choice between two theories, take the one which is funnier.
PATCH 8/9 Add NAND support for TS-7800
Quoted 8 lines · Wolfgang Denk
Dear Michael Spang,
Quoted 2 lines · In message <[email protected]> you…
The NAND control functions were written by Alexander Clouter and copied here from Linux.
Please provide exact reference, see bullet # 4 at
http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_Sign
Will add the following:
[upstream commit 75bb6b9aab3255f440ef4e72a31978d1681105d6]
Quoted 14 lines
Quoted 6 lines
drivers/mtd/nand/Makefile +0
-0@@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.oQuoted 6 lines
?COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
?COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
?COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
+COBJS-$(CONFIG_NAND_TS7800) += ts7800_nand.o
?COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
?endifPlease keep the list sorted.
Ok. The surrounding two are not correct either, not sure if I should fix them.
Michael
PATCH 8/9 Add NAND support for TS-7800
Dear Michael Spang,
Quoted 7 lines · In message <[email protected]> you wrote:
Quoted 3 lines
Please provide exact reference, see bullet # 4 at
http://www.denx.de/wiki/view/U-Boot/Patches#Attributing_Code_Copyrights_SignWill add the following:
[upstream commit
75bb6b9aab3255f440ef4e72a31978d1681105d6]
Please follow the example given.
Quoted 15 lines
Quoted 14 lines
Quoted 6 lines
drivers/mtd/nand/Makefile +0
-0@@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.oQuoted 6 lines
?COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
?COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
?COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
+COBJS-$(CONFIG_NAND_TS7800) += ts7800_nand.o
?COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
?endifPlease keep the list sorted.
Quoted 1 line
Ok. The surrounding two are not correct either, not sure if I should fix them.
Please do. Thanks.
Best regards,
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Often it is fatal to live too long. - Racine
PATCH 9/9 Add README for TS-7800
In reply to Michael Spang--- doc/README.ts7800 | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 doc/README.ts7800
doc/README.ts7800 new file +84 -0
@@ -0,0 +1,84 @@ +Booting +------- + +The TS-7800 boots initially from a proprietary bootloader on the FPGA +called TS-BOOTROM. TS-BOOTROM loads a small image from the MBR of the +onboard NAND or SD card into RAM, and executes it. The default MBR is +intended to boot a Linux kernel. + +The TS-7800 port of U-Boot takes the place of the Linux kernel in this +configuration, and is therefore loaded and executed by the MBR. The +MBR also creates an ATAG structure intended for Linux, but U-Boot +ignores it. + +NAND layout +----------- + +NAND support is not enabled by default because U-Boot will overwrite +part of it with its environment. To enable NAND support, enable +CONFIG_USE_NAND in include/configs/ts7800.h. + +The default NAND partition layout used by Technologic and Linux is: + + 128k(mbr),4m(linux),4m(initrd),-(rootfs) + +For U-Boot, we split the linux partition into a partition for the +U-Boot code and a partition for the U-Boot environment. The initrd +partition is not used, and is renamed to "linux". The new layout is: + + 128k(mbr),3m(uboot),1m(env),4m(linux),-(rootfs) + +When NAND support is enabled, this string is available in the U-Boot +default environment as the "mtdparts" variable. You may wish to use +this layout for Linux as well by adding it to the Linux command line. +For example: + + setenv bootargs console=ttyS0,115200n8 ${mtdparts} + +Installing U-Boot +----------------- + +To install U-Boot to the onboard flash, write u-boot.bin to the kernel +partition on the flash. From Linux this might be done as follows: + + flash_eraseall /dev/mtd1 + nandwrite --pad /dev/mtd1 u-boot.bin + +When running from onboard flash, you may wish to enable NAND support +as described in the previous section. The environment is not preserved +unless you enable NAND support. + +To install U-Boot to an SD card, write u-boot.bin to the kernel +partition on the card. + +Booting Technologic Kernels +--------------------------- + +Technologic's kernels use a different machine type ID than upstream +kernels. U-Boot uses the upstream ID, so Technologic kernels will +not boot from U-Boot without the following workaround: + + setenv machid 0x20e + +The following commands will convert a Technologic kernel image +into U-Boot format: + + mkimage -A arm -O linux -T kernel -C none -a 0x8000 \ + -d kernel-image-latest.dd uImage + + mkimage -A arm -O linux -T ramdisk -C none -a 0x1000000 \ + -d initrd-busybox-rootfs-latest.dd initrd + +Then pass both images to the bootm command to boot. Note that with +U-Boot installed there is only one partition available for the kernel +and initrd. To use both changing the NAND partitioning may be +required. To do so you can use the mtdparts command in U-Boot and pass +${mtdparts} to linux. + +TS-7800 Wiki +------------ + +A useful resource about the TS-7800 is the TS-7800 wiki [1], +maintained by Alexander Clouter. + +[1] http://www.digriz.org.uk/ts78xx
Signature · 1 line
1.7.2.3
PATCH 9/9 Add README for TS-7800
Dear Michael Spang,
Quoted 5 lines · In message <[email protected]> you…
Signed-off-by Michael Spang <[email protected]>--- doc/README.ts7800 | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 doc/README.ts7800
This should be added together with the original board support in a single patch.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de You've no idea of what a poor opinion I have of myself, and how
little I deserve it. - W. S. Gilbert
PATCH 9/9 Add README for TS-7800
Quoted 11 lines · Wolfgang Denk
Dear Michael Spang,
Quoted 5 lines · In message <[email protected]> you…
Signed-off-by Michael Spang <[email protected]>---
?doc/README.ts7800 | ? 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ?1 files changed, 84 insertions(+), 0 deletions(-)
?create mode 100644 doc/README.ts7800This should be added together with the original board support in a single patch.
Ok will squash them.
Michael
cover TS-7800 port for U-Boot
In reply to Michael SpangQuoted 7 lines · Michael Spang
The TS-7800 is an Orion5x implementation by Technologic Systems.
Albert, Wolfgang -
Thanks for reviewing my patch series and sorry for the delay in updating it.
Quoted 10 lines
Changelog:
?- Fixed all checkpatch errors.
?- Updated copyright year.
?- RenamedCONFIG_SKIP_LOWLEVEL_INITtoCONFIG_SKIP_CPU_INIT_CRIT? and introduced newCONFIG_SKIP_LOWLEVEL_INITthat skips only ?lowlevel_init.
?- Documented machine type ID workaround in the README. ?- Removed "ddr" from name oforion5x_ddr_addr_decode_registers. ?- Allow the environment to override the MAC even if
?CONFIG_PRESERVE_LOCAL_MACis set.
This is version 2 of this series. I forgot to update the subject line.
Michael
cover TS-7800 port for U-Boot
In reply to Michael SpangLe 17/03/2011 20:46, Michael Spang a ?crit :
Quoted 6 lines
The TS-7800 is an Orion5x implementation by Technologic Systems.
Albert, Wolfgang -
Thanks for reviewing my patch series and sorry for the delay in updating it.
Hi Michael,
In return, sorry in advance for the delay in reviewing this new patch set -- I will do during the week-end, especially as I want to test on ED Mini V2 for regression.
Amicalement,
Signature · 1 line
Albert.