ARM: OMAP2+: gpmc warning fixes

PATCH New Balaji T K 2 participants 5 messages Mar 17, 2011 – Mar 18, 2011

Subsystems (5)

Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP power management support +1 more subsystems

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Balaji T K

author

2011-03-17 15:56 UTC #0 lore raw

cover ARM: OMAP2+: gpmc warning fixes

Applies on omap-for-linus branch
Boot tested on OMAP4430 SDP and OMAP3630SDP

Balaji T K (3):
ARM: OMAP2+: correct GPMC IRQ
ARM: OMAP2+: GPMC set dummy irq chip
ARM: OMAP4: correct GPMC IRQ number

 arch/arm/mach-omap2/gpmc.c             |   13 ++++++++-----
 arch/arm/plat-omap/include/plat/irqs.h |    2 +-
 2 files changed, 9 insertions(+), 6 deletions(-)

Balaji T K

author

2011-03-17 15:56 UTC #1 lore raw

PATCH 1/3 ARM: OMAP2+: correct GPMC IRQ

GPMC: number of chip select is 8, CS0 to CS7 One less IRQ allocated throws below warning at boot

[    0.429290] Trying to install type control for IRQ409
[    0.429290] Trying to set irq flags for IRQ409

Signed-off-by Balaji T K <[email protected]>

---
 arch/arm/plat-omap/include/plat/irqs.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/plat-omap/include/plat/irqs.h +1 -1

index d779283..5a25098 100644
@@ -416,7 +416,7 @@
 
 /* GPMC related */
 #define OMAP_GPMC_IRQ_BASE	(TWL_IRQ_END)
-#define OMAP_GPMC_NR_IRQS	7
+#define OMAP_GPMC_NR_IRQS	8
 #define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)

Signature · 1 line

1.7.0.4

Balaji T K

author

2011-03-17 15:56 UTC #2 lore raw

PATCH 2/3 ARM: OMAP2+: GPMC set dummy irq chip

In reply to Balaji T K

Resolve following warning messages in boot when irq chip is not set

[    0.429229] Trying to install interrupt handler for IRQ402
[    0.429229] Trying to install interrupt handler for IRQ403
[    0.429229] Trying to install interrupt handler for IRQ404
[    0.429260] Trying to install interrupt handler for IRQ405
[    0.429260] Trying to install interrupt handler for IRQ406
[    0.429260] Trying to install interrupt handler for IRQ407
[    0.429290] Trying to install interrupt handler for IRQ408

Signed-off-by Balaji T K <[email protected]>

---
 arch/arm/mach-omap2/gpmc.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

arch/arm/mach-omap2/gpmc.c +2 -1

index 6741743..d81d536 100644
@@ -739,7 +739,8 @@ static int __init gpmc_init(void)
 	/* initalize the irq_chained */
 	irq = OMAP_GPMC_IRQ_BASE;
 	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-		set_irq_handler(irq, handle_simple_irq);
+		set_irq_chip_and_handler(irq, &dummy_irq_chip,
+						handle_simple_irq);
 		set_irq_flags(irq, IRQF_VALID);
 		irq++;
 	}

Signature · 1 line

1.7.0.4

Balaji T K

author

2011-03-17 15:56 UTC #3 lore raw

PATCH 3/3 ARM: OMAP4: correct GPMC IRQ number

In reply to Balaji T K

OMAP4 GPMC IRQ is not same as OMAP3 IRQ. Fix it.

Resolve following warning in OMAP4

[    0.429290] gpmc: irq-20 could not claim: err -22

Signed-off-by Balaji T K <[email protected]>

---
 arch/arm/mach-omap2/gpmc.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

arch/arm/mach-omap2/gpmc.c +6 -4

index d81d536..493505c 100644
@@ -693,6 +693,7 @@ static int __init gpmc_init(void)
 {
 	u32 l, irq;
 	int cs, ret = -EINVAL;
+	int gpmc_irq;
 	char *ck = NULL;
 
 	if (cpu_is_omap24xx()) {

@@ -701,12 +702,15 @@ static int __init gpmc_init(void)
 			l = OMAP2420_GPMC_BASE;
 		else
 			l = OMAP34XX_GPMC_BASE;
+		gpmc_irq = INT_34XX_GPMC_IRQ;
 	} else if (cpu_is_omap34xx()) {
 		ck = "gpmc_fck";
 		l = OMAP34XX_GPMC_BASE;
+		gpmc_irq = INT_34XX_GPMC_IRQ;
 	} else if (cpu_is_omap44xx()) {
 		ck = "gpmc_ck";
 		l = OMAP44XX_GPMC_BASE;
+		gpmc_irq = OMAP44XX_IRQ_GPMC;
 	}
 
 	if (WARN_ON(!ck))

@@ -745,11 +749,11 @@ static int __init gpmc_init(void)
 		irq++;
 	}
 
-	ret = request_irq(INT_34XX_GPMC_IRQ,
+	ret = request_irq(gpmc_irq,
 			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
 	if (ret)
 		pr_err("gpmc: irq-%d could not claim: err %d\n",
-						INT_34XX_GPMC_IRQ, ret);
+						gpmc_irq, ret);
 	return ret;
 }
 postcore_initcall(gpmc_init);

@@ -758,8 +762,6 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
 	u8 cs;
 
-	if (irq != INT_34XX_GPMC_IRQ)
-		return IRQ_HANDLED;
 	/* check cs to invoke the irq */
 	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
 	if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)

Signature · 1 line

1.7.0.4

Tony Lindgren

maintainer

2011-03-18 23:43 UTC #4 lore raw

cover ARM: OMAP2+: gpmc warning fixes

In reply to Balaji T K

Quoted 11 lines · Balaji T K

Applies on omap-for-linus branch
Boot tested on OMAP4430 SDP and OMAP3630SDP
Balaji T K (3):
ARM: OMAP2+: correct GPMC IRQ
ARM: OMAP2+: GPMC set dummy irq chip
ARM: OMAP4: correct GPMC IRQ number
 arch/arm/mach-omap2/gpmc.c             |   13 ++++++++-----
 arch/arm/plat-omap/include/plat/irqs.h |    2 +-
 2 files changed, 9 insertions(+), 6 deletions(-)

Thanks, I've squashed these into one patch and updated the comments. Will apply into fixes, updated patch below.

Regards,

Tony

From: Balaji T K <[email protected]>
Date: Fri, 18 Mar 2011 16:22:39 -0700
Subject: [PATCH] ARM: OMAP2+: Fix warnings for GPMC interrupt

Commit db97eb7dfe13f6c04f0a0e77c32e2691f563ab8b
(omap: gpmc: enable irq mode in gpmc) enabled interrupts for GPMC (General Purpose Memory Controller). However, looks like this patch only works on omap3. Fix the issues to avoid warnings on omap4 during the boot.

GPMC: number of chip select is 8, CS0 to CS7. One less IRQ allocated throws below warning at boot:

[    0.429290] Trying to install type control for IRQ409
[    0.429290] Trying to set irq flags for IRQ409

Resolve following warning messages in boot when irq chip is not set:

[    0.429229] Trying to install interrupt handler for IRQ402
[    0.429229] Trying to install interrupt handler for IRQ403
[    0.429229] Trying to install interrupt handler for IRQ404
[    0.429260] Trying to install interrupt handler for IRQ405
[    0.429260] Trying to install interrupt handler for IRQ406
[    0.429260] Trying to install interrupt handler for IRQ407
[    0.429290] Trying to install interrupt handler for IRQ408

Resolve following warning in OMAP4:

[    0.429290] gpmc: irq-20 could not claim: err -22

Signed-off-by Balaji T K <[email protected]>

[tony at atomide.com: combined patches into one, updated comments]

Signed-off-by Tony Lindgren <[email protected]>

arch/arm/mach-omap2/gpmc.c +8 -5

index 6741743..493505c 100644
@@ -693,6 +693,7 @@ static int __init gpmc_init(void)
 {
 	u32 l, irq;
 	int cs, ret = -EINVAL;
+	int gpmc_irq;
 	char *ck = NULL;
 
 	if (cpu_is_omap24xx()) {

@@ -701,12 +702,15 @@ static int __init gpmc_init(void)
 			l = OMAP2420_GPMC_BASE;
 		else
 			l = OMAP34XX_GPMC_BASE;
+		gpmc_irq = INT_34XX_GPMC_IRQ;
 	} else if (cpu_is_omap34xx()) {
 		ck = "gpmc_fck";
 		l = OMAP34XX_GPMC_BASE;
+		gpmc_irq = INT_34XX_GPMC_IRQ;
 	} else if (cpu_is_omap44xx()) {
 		ck = "gpmc_ck";
 		l = OMAP44XX_GPMC_BASE;
+		gpmc_irq = OMAP44XX_IRQ_GPMC;
 	}
 
 	if (WARN_ON(!ck))

@@ -739,16 +743,17 @@ static int __init gpmc_init(void)
 	/* initalize the irq_chained */
 	irq = OMAP_GPMC_IRQ_BASE;
 	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-		set_irq_handler(irq, handle_simple_irq);
+		set_irq_chip_and_handler(irq, &dummy_irq_chip,
+						handle_simple_irq);
 		set_irq_flags(irq, IRQF_VALID);
 		irq++;
 	}
 
-	ret = request_irq(INT_34XX_GPMC_IRQ,
+	ret = request_irq(gpmc_irq,
 			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
 	if (ret)
 		pr_err("gpmc: irq-%d could not claim: err %d\n",
-						INT_34XX_GPMC_IRQ, ret);
+						gpmc_irq, ret);
 	return ret;
 }
 postcore_initcall(gpmc_init);

@@ -757,8 +762,6 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
 	u8 cs;
 
-	if (irq != INT_34XX_GPMC_IRQ)
-		return IRQ_HANDLED;
 	/* check cs to invoke the irq */
 	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
 	if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)

arch/arm/plat-omap/include/plat/irqs.h +1 -1

index d779283..5a25098 100644
@@ -416,7 +416,7 @@
 
 /* GPMC related */
 #define OMAP_GPMC_IRQ_BASE	(TWL_IRQ_END)
-#define OMAP_GPMC_NR_IRQS	7
+#define OMAP_GPMC_NR_IRQS	8
 #define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)