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arm: Add Cortex A5 proc_info

PATCH New Pawel Moll 3 participants 14 messages May 17, 2011 – May 20, 2011 Arm (32-bit)

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Pawel Moll

author
#0 lore raw

PATCH 1/1 arm: Add Cortex A5 proc_info

This patch adds processor info for Cortex A5 (MPCore).

Sadly it's just a clone of A9, but it's impossible to simply extend the ID mask to cover all ARM Ltd. originating v7 implementations as A15 have slightly different SCU initialization procedure.

Signed-off-by Pawel Moll <[email protected]>
---
 arch/arm/mm/proc-v7.S |   43 +++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 41 insertions(+), 2 deletions(-)
arch/arm/mm/proc-v7.S +41 -2
index babfba0..5808d14 100644
@@ -270,11 +270,15 @@ cpu_resume_l1_flags:
  *	Harvard cache control instructions insead of the unified cache
  *	control instructions.
  *
- *	This should be able to cover all ARMv7 cores.
+ *	This should be able to cover all ARMv7 cores. Some MPCore
+ *	implementations require additional code when SMP is to be
+ *	enabled to activate Snoop Control Unit - this is done prior
+ *	to the __v7_setup.
  *
  *	It is assumed that:
  *	- cache type register is implemented
  */
+__v7_ca5mp_setup:
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)

@@ -436,6 +440,41 @@ cpu_elf_name:
 
 	.section ".proc.info.init", #alloc, #execinstr
 
+	/*
+	 * Match Cortex A5 MPcore
+	 */
+	.type   __v7_ca5mp_proc_info, #object
+__v7_ca5mp_proc_info:
+	.long	0x410fc050		@ Required ID value
+	.long	0xff0ffff0		@ Mask for ID
+	ALT_SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	ALT_UP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_UP)
+	.long   PMD_TYPE_SECT | \
+		PMD_SECT_XN | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ
+	W(b)	__v7_ca5mp_setup
+	.long	cpu_arch_name
+	.long	cpu_elf_name
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
+	.long	cpu_v7_name
+	.long	v7_processor_functions
+	.long	v7wbi_tlb_fns
+	.long	v6_user_fns
+	.long	v7_cache_fns
+	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
+
+	/*
+	 * Match Cortex A9 MPcore
+	 */
 	.type   __v7_ca9mp_proc_info, #object
 __v7_ca9mp_proc_info:
 	.long	0x410fc090		@ Required ID value

@@ -466,7 +505,7 @@ __v7_ca9mp_proc_info:
 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 
 	/*
-	 * Match any ARMv7 processor core.
+	 * Match any other ARMv7 processor core.
 	 */
 	.type	__v7_proc_info, #object
 __v7_proc_info:
Signature · 1 line
1.6.3.3
author
#1 lore raw

PATCH 1/1 arm: Add Cortex A5 proc_info

arch/arm/mm/proc-v7.S cpu_elf_name: · line 449

Quoted 2 lines
arch/arm/mm/proc-v7.S +2 -0
+	.long	0x410fc050		@ Required ID value
+	.long	0xff0ffff0		@ Mask for ID

Alternatively I could "reuse" current A9 proc_info and change ID value and mask to:

0x410fc010
0xff0fff30

This would:

* match Cortex A5 (part no. 0xc05) and A9 (0xc09)

* not match A8 (0xc08) and A15 (0xc0f)

Everything is fine so far, but also:

* match part no. 0xc01 and 0xc0d

Obviously no parts like that exist today, but somehow this "solution" doesn't appeal to me... Of course it would save 39 lines in diff stat ;-)

Any thoughts?

Pawe?

#2 lore raw

PATCH 1/1 arm: Add Cortex A5 proc_info

Quoted 15 lines · Pawel Moll

arch/arm/mm/proc-v7.S cpu_elf_name: · line 449

Quoted 2 lines
arch/arm/mm/proc-v7.S +2 -0
+	.long	0x410fc050		@ Required ID value
+	.long	0xff0ffff0		@ Mask for ID

Alternatively I could "reuse" current A9 proc_info and change ID value and mask to:

0x410fc010
0xff0fff30

This would:

* match Cortex A5 (part no. 0xc05) and A9 (0xc09)

* not match A8 (0xc08) and A15 (0xc0f)

Quoted 7 lines

Everything is fine so far, but also:

* match part no. 0xc01 and 0xc0d

Obviously no parts like that exist today, but somehow this "solution" doesn't appeal to me... Of course it would save 39 lines in diff stat ;-)

If we're worried about the ambiguity/duplication, maybe the proc_info structure format could be extended to allow multiple match specifications, or a level of indirection could be introduced.

Dunno whether it's worth it though. It partly depends on how often we expect this kind of duplication to occur.

The simplest solution might be to use a macro to avoid duplication in the source. This would still create diffstat noise, but it's not actually fragmentary, so it may be considered OK.

See what other people think, I guess.

---Dave

author
#3 lore raw

PATCH 1/1 arm: Add Cortex A5 proc_info

Quoted 3 lines

The simplest solution might be to use a macro to avoid duplication in the source. This would still create diffstat noise, but it's not actually fragmentary, so it may be considered OK.

Yeah, I like this idea. Macro would do here probably, especially that it could be used in future by A15 proc_info as well. Will give it a try.

Cheers!

Pawe?

author
#4 lore raw

PATCH v2 1/1 arm: Add Cortex A5 proc info

This patch adds processor info for Cortex A5 (MPCore).

To reduce code duplicating it converts existing A9 proc info into a macro and uses it to define A5 and A9 cores, allowing new similar parts (requiring different init function and MMU flags) in future.

Signed-off-by Pawel Moll <[email protected]>
---
 arch/arm/mm/proc-v7.S |   69 ++++++++++++++++++++++++++++--------------------
 1 files changed, 40 insertions(+), 29 deletions(-)
arch/arm/mm/proc-v7.S +40 -29
index babfba0..01256fa 100644
@@ -270,11 +270,15 @@ cpu_resume_l1_flags:
  *	Harvard cache control instructions insead of the unified cache
  *	control instructions.
  *
- *	This should be able to cover all ARMv7 cores.
+ *	This should be able to cover all ARMv7 cores. Some MPCore
+ *	implementations require additional code when SMP is to be
+ *	enabled to activate Snoop Control Unit - this is done prior
+ *	to the __v7_setup.
  *
  *	It is assumed that:
  *	- cache type register is implemented
  */
+__v7_ca5mp_setup:
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)

@@ -436,34 +440,41 @@ cpu_elf_name:
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type   __v7_ca9mp_proc_info, #object
-__v7_ca9mp_proc_info:
-	.long	0x410fc090		@ Required ID value
-	.long	0xff0ffff0		@ Mask for ID
-	ALT_SMP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_SMP)
-	ALT_UP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_UP)
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_XN | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	W(b)	__v7_ca9mp_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
-	.long	cpu_v7_name
-	.long	v7_processor_functions
-	.long	v7wbi_tlb_fns
-	.long	v6_user_fns
-	.long	v7_cache_fns
-	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+	/*
+	 * ARM Ltd. Cortex cores
+	 */
+#define __V7_CORTEX_PROC_INFO(_part, _mm_mmuflags, _io_mmuflags, _initfunc) \
+	.type   __v7_ca##_part##mp_proc_info, #object; \
+__v7_ca##_part##mp_proc_info:; \
+	.long	0x410fc0##_part##0; \
+	.long	0xff0ffff0; \
+	ALT_SMP(.long	_mm_mmuflags | PMD_FLAGS_SMP); \
+	ALT_UP(.long	_mm_mmuflags | PMD_FLAGS_UP); \
+	.long	_io_mmuflags; \
+	W(b)	_initfunc; \
+	.long	cpu_arch_name; \
+	.long	cpu_elf_name; \
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS; \
+	.long	cpu_v7_name; \
+	.long	v7_processor_functions; \
+	.long	v7wbi_tlb_fns; \
+	.long	v6_user_fns; \
+	.long	v7_cache_fns; \
+	.size	__v7_ca##_part##mp_proc_info, . - __v7_ca##_part##mp_proc_info
+
+__V7_CORTEX_PROC_INFO(
+	5, /* Cortex A5 */
+	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ,
+	PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ,
+	__v7_ca5mp_setup
+)
+
+__V7_CORTEX_PROC_INFO(
+	9, /* Cortex A9 */
+	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ,
+	PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ,
+	__v7_ca9mp_setup
+)
 
 	/*
 	 * Match any ARMv7 processor core.
Signature · 1 line
1.6.3.3
#5 lore raw

PATCH v2 1/1 arm: Add Cortex A5 proc info

Hi Pawel,

Quoted 93 lines

This patch adds processor info for Cortex A5 (MPCore).

To reduce code duplicating it converts existing A9 proc info into a macro and uses it to define A5 and A9 cores, allowing new similar parts (requiring different init function and MMU flags) in future.

Signed-off-by Pawel Moll <[email protected]>
---
 arch/arm/mm/proc-v7.S |   69 ++++++++++++++++++++++++++++--------------------
 1 files changed, 40 insertions(+), 29 deletions(-)
arch/arm/mm/proc-v7.S +33 -29
index babfba0..01256fa 100644
@@ -270,11 +270,15 @@ cpu_resume_l1_flags:
  *	Harvard cache control instructions insead of the unified cache
  *	control instructions.
  *
- *	This should be able to cover all ARMv7 cores.
+ *	This should be able to cover all ARMv7 cores. Some MPCore
+ *	implementations require additional code when SMP is to be
+ *	enabled to activate Snoop Control Unit - this is done prior
+ *	to the __v7_setup.
  *
  *	It is assumed that:
  *	- cache type register is implemented
  */
+__v7_ca5mp_setup:
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)

@@ -436,34 +440,41 @@ cpu_elf_name:
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type   __v7_ca9mp_proc_info, #object
-__v7_ca9mp_proc_info:
-	.long	0x410fc090		@ Required ID value
-	.long	0xff0ffff0		@ Mask for ID
-	ALT_SMP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_SMP)
-	ALT_UP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_UP)
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_XN | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	W(b)	__v7_ca9mp_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
-	.long	cpu_v7_name
-	.long	v7_processor_functions
-	.long	v7wbi_tlb_fns
-	.long	v6_user_fns
-	.long	v7_cache_fns
-	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+	/*
+	 * ARM Ltd. Cortex cores
+	 */
+#define __V7_CORTEX_PROC_INFO(_part, _mm_mmuflags, _io_mmuflags, _initfunc) \
+	.type   __v7_ca##_part##mp_proc_info, #object; \
+__v7_ca##_part##mp_proc_info:; \
+	.long	0x410fc0##_part##0; \
+	.long	0xff0ffff0; \
+	ALT_SMP(.long	_mm_mmuflags | PMD_FLAGS_SMP); \
+	ALT_UP(.long	_mm_mmuflags | PMD_FLAGS_UP); \
+	.long	_io_mmuflags; \
+	W(b)	_initfunc; \
+	.long	cpu_arch_name; \
+	.long	cpu_elf_name; \
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS; \
+	.long	cpu_v7_name; \
+	.long	v7_processor_functions; \
+	.long	v7wbi_tlb_fns; \
+	.long	v6_user_fns; \
+	.long	v7_cache_fns; \
+	.size	__v7_ca##_part##mp_proc_info, . - __v7_ca##_part##mp_proc_info
+
+__V7_CORTEX_PROC_INFO(
+	5, /* Cortex A5 */
+	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ,
+	PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ,
+	__v7_ca5mp_setup
+)

arch/arm/mm/proc-v7.S cpu_elf_name: · line 480

Quoted 10 lines
arch/arm/mm/proc-v7.S +7 -0
+
+__V7_CORTEX_PROC_INFO(
+	9, /* Cortex A9 */
+	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ,
+	PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ,
+	__v7_ca9mp_setup
+)
 
 	/*
 	 * Match any ARMv7 processor core.

Please can you do the same for the __v7_proc_info struct? On top of that, I think you should take optional, additional HWCAPs as arguments to the macro which get ORd with the base v7 HWCAPs. This might be useful for A15 where we have integer division.

Cheers,

Will

author
#6 lore raw

PATCH v2 1/1 arm: Add Cortex A5 proc info

Quoted 1 line

Please can you do the same for the __v7_proc_info struct?

Yeah, I could if we want to... The thing is that the macro will have to take full ID and mask value then. And a name for the structure. So extra 3 parameters. Not a big deal I suppose.

Quoted 2 lines

On top of that, I think you should take optional, additional HWCAPs as arguments to the macro which get ORd with the base v7 HWCAPs.

Em, the "optional" bit here is a problem. I can't just do

#define INFO(_a, _extra_hwcaps...) \
	.long HWCAP | _extra_hwcaps;

Because the output would be ".long HWCAP | ;" when no _extra_hwcaps are given... Unless I'm missing some preprocessor trick? :-)

Quoted 1 line

This might be useful for A15 where we have integer division.

What HWCAP would this be? I've checked Catalin's repo and the only difference I've spotted between A9 and A15 proc info were the mmu flags...

Cheers!

Pawe?

#7 lore raw

PATCH v2 1/1 arm: Add Cortex A5 proc info

Quoted 5 lines · Pawel Moll
Quoted 1 line

Please can you do the same for the __v7_proc_info struct?

Yeah, I could if we want to... The thing is that the macro will have to take full ID and mask value then. And a name for the structure. So extra 3 parameters. Not a big deal I suppose.

Optionally, you could just omit the label and mask/match words from the macro. Those are always at the start, so we don't need to cunningly insert them in the middle of the macro expansion.

By definition, they will be different per expansion, too. So it makes less sense to have these in the macro definition itself.

Similarly, you could just leave the .size directive out of the macro to avoid having to generlise it -- after all, it's not generalised for the other proc_info definitions so this makes the situation no worse.

Quoted 4 lines
Quoted 3 lines

On top of that, I think you should take optional, additional HWCAPs as arguments to the macro which get ORd with the base v7 HWCAPs.

Quoted 8 lines

Em, the "optional" bit here is a problem. I can't just do

#define INFO(_a, _extra_hwcaps...) \
	.long HWCAP | _extra_hwcaps;

Because the output would be ".long HWCAP | ;" when no _extra_hwcaps are given... Unless I'm missing some preprocessor trick? :-)

You could use an assembler macro instead.

.macro blarg insert_hwcaps=0

	/* blah */
	.long HWCAP_ALICE | HWCAP_BOB | HWCAP_CHARLIE | ( \insert_hwcaps )
	/* blah */

.endm

As an added bonus, this could substantially reduce the diffstat, because assembler macro definitions can have multiple lines, so you don't need all that awful semicolon-backslash line continuation stuff.

Not everyone likes assembler macros, though...

Quoted 6 lines
Quoted 2 lines

This might be useful for A15 where we have integer division.

What HWCAP would this be? I've checked Catalin's repo and the only difference I've spotted between A9 and A15 proc info were the mmu flags...

You could invent one, if none is defined yet. You probably want to check with Catalin or Will.

---Dave

#8 lore raw

PATCH v2 1/1 arm: Add Cortex A5 proc info

Quoted 19 lines
Quoted 4 lines
Quoted 3 lines

On top of that, I think you should take optional, additional HWCAPs as arguments to the macro which get ORd with the base v7 HWCAPs.

Quoted 8 lines

Em, the "optional" bit here is a problem. I can't just do

#define INFO(_a, _extra_hwcaps...) \
	.long HWCAP | _extra_hwcaps;

Because the output would be ".long HWCAP | ;" when no _extra_hwcaps are given... Unless I'm missing some preprocessor trick? :-)

You could use an assembler macro instead.

.macro blarg insert_hwcaps=0

	/* blah */
	.long HWCAP_ALICE | HWCAP_BOB | HWCAP_CHARLIE | ( \insert_hwcaps )
	/* blah */
Quoted 7 lines

.endm

As an added bonus, this could substantially reduce the diffstat, because assembler macro definitions can have multiple lines, so you don't need all that awful semicolon-backslash line continuation stuff.

Not everyone likes assembler macros, though...

I think that looks better and we are in an assembly file after all.

Quoted 9 lines
Quoted 6 lines
Quoted 2 lines

This might be useful for A15 where we have integer division.

What HWCAP would this be? I've checked Catalin's repo and the only difference I've spotted between A9 and A15 proc info were the mmu flags...

You could invent one, if none is defined yet. You probably want to check with Catalin or Will.

This is a separate patch and not one that we should rush out until we've spoken to the tools guys. Having the extensibility from the start makes sense though.

Will

author
#9 lore raw

PATCH v2 1/1 arm: Add Cortex A5 proc info

In reply to Dave Martin
Quoted 3 lines

You could use an assembler macro instead.

macro blarg insert_hwcaps=0

Awesome, I didn't know that assembler macro can take default values for parameters (every day we learn something new :-)

It's sorted then, v3 to follow in a jiffy.

Cheers!

Pawe?

author
#10 lore raw

PATCH v3 1/2 arm: Convert v7 proc infos into a common macro

As most of the proc info content is common across all v7 processors, this patch converts existing A9 and generic v7 descriptions into a macro (allowing extra flags in future).

Signed-off-by Pawel Moll <[email protected]>
---
 arch/arm/mm/proc-v7.S |   67 +++++++++++++++++-------------------------------
 1 files changed, 24 insertions(+), 43 deletions(-)
arch/arm/mm/proc-v7.S +24 -43
index babfba0..e5087aa 100644
@@ -436,33 +436,36 @@ cpu_elf_name:
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type   __v7_ca9mp_proc_info, #object
-__v7_ca9mp_proc_info:
-	.long	0x410fc090		@ Required ID value
-	.long	0xff0ffff0		@ Mask for ID
-	ALT_SMP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_SMP)
-	ALT_UP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_UP)
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_XN | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	W(b)	__v7_ca9mp_setup
+	/*
+	 * Standard v7 proc info content
+	 */
+.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
+	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
+			PMD_FLAGS_SMP | \mm_mmuflags)
+	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
+			PMD_FLAGS_UP | \mm_mmuflags)
+	.long	PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \io_mmuflags
+	W(b)	\initfunc
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
+	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
+		HWCAP_EDSP | HWCAP_TLS | \hwcaps
 	.long	cpu_v7_name
 	.long	v7_processor_functions
 	.long	v7wbi_tlb_fns
 	.long	v6_user_fns
 	.long	v7_cache_fns
+.endm
+
+	/*
+	 * ARM Ltd. Cortex A9 processor.
+	 */
+	.type   __v7_ca9mp_proc_info, #object
+__v7_ca9mp_proc_info:
+	.long	0x410fc090
+	.long	0xff0ffff0
+	__v7_proc __v7_ca9mp_setup
 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 
 	/*

@@ -472,27 +475,5 @@ __v7_ca9mp_proc_info:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	ALT_SMP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_SMP)
-	ALT_UP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_UP)
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_XN | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ
-	W(b)	__v7_setup
-	.long	cpu_arch_name
-	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
-	.long	cpu_v7_name
-	.long	v7_processor_functions
-	.long	v7wbi_tlb_fns
-	.long	v6_user_fns
-	.long	v7_cache_fns
+	__v7_proc __v7_setup
 	.size	__v7_proc_info, . - __v7_proc_info
Signature · 1 line
1.6.3.3
author
#11 lore raw

PATCH v3 2/2 arm: Add Cortex A5 proc info

This patch adds processor info for ARM Ltd. Cortex A5, which has SCU initialisation procedure identical to A9.

Signed-off-by Pawel Moll <[email protected]>
---
 arch/arm/mm/proc-v7.S |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)
arch/arm/mm/proc-v7.S +11 -0
index e5087aa..4a23638 100644
@@ -275,6 +275,7 @@ cpu_resume_l1_flags:
  *	It is assumed that:
  *	- cache type register is implemented
  */
+__v7_ca5mp_setup:
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)

@@ -459,6 +460,16 @@ cpu_elf_name:
 .endm
 
 	/*
+	 * ARM Ltd. Cortex A5 processor.
+	 */
+	.type   __v7_ca5mp_proc_info, #object
+__v7_ca5mp_proc_info:
+	.long	0x410fc050
+	.long	0xff0ffff0
+	__v7_proc __v7_ca5mp_setup
+	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
+
+	/*
 	 * ARM Ltd. Cortex A9 processor.
 	 */
 	.type   __v7_ca9mp_proc_info, #object
Signature · 1 line
1.6.3.3
#13 lore raw

PATCH v3 1/2 arm: Convert v7 proc infos into a common macro

In reply to Pawel Moll

Hello Pawel,

Quoted 25 lines
arch/arm/mm/proc-v7.S +0 -17
index babfba0..e5087aa 100644
@@ -436,33 +436,36 @@ cpu_elf_name:
 
 	.section ".proc.info.init", #alloc, #execinstr
 
-	.type   __v7_ca9mp_proc_info, #object
-__v7_ca9mp_proc_info:
-	.long	0x410fc090		@ Required ID value
-	.long	0xff0ffff0		@ Mask for ID
-	ALT_SMP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_SMP)
-	ALT_UP(.long \
-		PMD_TYPE_SECT | \
-		PMD_SECT_AP_WRITE | \
-		PMD_SECT_AP_READ | \
-		PMD_FLAGS_UP)
-	.long   PMD_TYPE_SECT | \
-		PMD_SECT_XN | \
-		PMD_SECT_AP_WRITE | \

arch/arm/mm/proc-v7.S cpu_elf_name: · line 446

Quoted 10 lines
arch/arm/mm/proc-v7.S +8 -2
-		PMD_SECT_AP_READ
-	W(b)	__v7_ca9mp_setup
+	/*
+	 * Standard v7 proc info content
+	 */
+.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
+	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
+			PMD_FLAGS_SMP | \mm_mmuflags)
+	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
+			PMD_FLAGS_UP | \mm_mmuflags)

My only minor gripe is the reformatting of the PMD_* here. Functionally, it looks fine.

Acked-by Will Deacon <[email protected]>

Will