timers/clockevents changes for v2.6.40
Subsystems (16)
Linus,
Please pull the latest timers-clockevents-for-linus git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git timers-clockevents-for-linus
Thanks,
Ingo
------------------>
John Stultz (7):
x86: Convert remaining x86 clocksources to clocksource_register_hz/khz
ia64: convert to clocksource_register_hz/khz
microblaze: convert to clocksource_register_hz/khz
alpha: convert to clocksource_register_hz
sparc: convert to clocksource_register_hz/khz
mips: convert to clocksource_register_hz/khz
blackfin: convert to clocksource_register_hz
Russell King (4):
clocksource: add common i8253 PIT clocksource
clocksource: convert footbridge to generic i8253 clocksource
clocksource: convert x86 to generic i8253 clocksource
clocksource: convert mips to generic i8253 clocksource
Russell King - ARM Linux (1):
Make clocksource name const
Thomas Gleixner (7):
clocksource: Restructure clocksource struct members
clocksource: Get rid of the hardcoded 5 seconds sleep time limit
clockevents: Restructure clock_event_device members
clockevents: Provide combined configure and register function
clockevents: Provide interface to reconfigure an active clock event device
x86: Convert PIT to clockevents_config_and_register()
x86: hpet: Cleanup the clockevents init and register code
arch/alpha/kernel/time.c | 3 +- arch/arm/include/asm/i8253.h | 15 ++++ arch/arm/mach-footbridge/Kconfig | 2 + arch/arm/mach-footbridge/isa-timer.c | 45 +----------- arch/blackfin/kernel/time-ts.c | 35 +--------- arch/ia64/kernel/cyclone.c | 6 +-- arch/ia64/kernel/time.c | 9 +-- arch/ia64/sn/kernel/sn2/timer.c | 6 +-- arch/microblaze/kernel/timer.c | 6 +-- arch/mips/Kconfig | 1 + arch/mips/alchemy/common/time.c | 3 +- arch/mips/cavium-octeon/csrc-octeon.c | 3 +- arch/mips/include/asm/i8253.h | 5 ++ arch/mips/include/asm/time.h | 6 -- arch/mips/jz4740/time.c | 3 +- arch/mips/kernel/cevt-txx9.c | 3 +- arch/mips/kernel/csrc-bcm1480.c | 3 +- arch/mips/kernel/csrc-ioasic.c | 4 +- arch/mips/kernel/csrc-powertv.c | 35 +-------- arch/mips/kernel/csrc-r4k.c | 4 +- arch/mips/kernel/csrc-sb1250.c | 3 +- arch/mips/kernel/i8253.c | 78 +-------------------- arch/mips/loongson/common/cs5536/cs5536_mfgpt.c | 5 +- arch/mips/sgi-ip27/ip27-timer.c | 3 +- arch/x86/Kconfig | 1 + arch/x86/include/asm/i8253.h | 2 + arch/x86/kernel/apb_timer.c | 10 +--- arch/x86/kernel/hpet.c | 72 ++++-------------- arch/x86/kernel/i8253.c | 86 +--------------------- arch/x86/kernel/kvmclock.c | 6 +-- arch/x86/lguest/boot.c | 4 +- arch/x86/platform/uv/uv_time.c | 6 +-- arch/x86/xen/time.c | 6 +-- drivers/Kconfig | 3 + drivers/char/hpet.c | 6 +-- drivers/clocksource/Kconfig | 2 + drivers/clocksource/Makefile | 1 + drivers/clocksource/cyclone.c | 10 +-- drivers/clocksource/i8253.c | 88 +++++++++++++++++++++++ include/linux/clockchips.h | 56 +++++++++------ include/linux/clocksource.h | 34 ++++----- kernel/time/clockevents.c | 64 ++++++++++++++++ kernel/time/clocksource.c | 38 +++++----- 43 files changed, 305 insertions(+), 476 deletions(-) create mode 100644 arch/arm/include/asm/i8253.h create mode 100644 drivers/clocksource/Kconfig create mode 100644 drivers/clocksource/i8253.c
arch/alpha/kernel/time.c +1 -2
@@ -375,8 +375,7 @@ static struct clocksource clocksource_rpcc = {static inline void register_rpcc_clocksource (long cycle_freq) { -clocksource_calc_mult_shift (&clocksource_rpcc, cycle_freq,4 ); -clocksource_register (&clocksource_rpcc); +clocksource_register_hz (&clocksource_rpcc, cycle_freq); }#else /* !CONFIG_SMP */ static inline void register_rpcc_clocksource (long cycle_freq)
arch/arm/include/asm/i8253.h new file +15 -0
@@ -0,0 +1,15 @@ +#ifndef __ASMARM_I8253_H +#define __ASMARM_I8253_H + +/* i8253A PIT registers */ +#define PIT_MODE 0x43 +#define PIT_CH0 0x40 + +#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) + +extern raw_spinlock_t i8253_lock; + +#define outb_pit outb_p +#define inb_pit inb_p + +#endif
arch/arm/mach-footbridge/Kconfig +2 -0
@@ -4,6 +4,7 @@ menu "Footbridge Implementations" config ARCH_CATS bool "CATS" + select CLKSRC_I8253 select FOOTBRIDGE_HOST select ISA select ISA_DMA
@@ -59,6 +60,7 @@ config ARCH_EBSA285_HOST config ARCH_NETWINDER bool "NetWinder" + select CLKSRC_I8253 select FOOTBRIDGE_HOST select ISA select ISA_DMA
arch/arm/mach-footbridge/isa-timer.c +4 -41
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arch/blackfin/kernel/time-ts.c +2 -33
@@ -23,29 +23,6 @@#include <asm/gptimers.h> #include <asm/nmi.h> -/* Accelerators for sched_clock() -* convert from cycles(64bits) => nanoseconds (64bits) -* basic equation: -* ns = cycles / (freq / ns_per_sec) -* ns = cycles * (ns_per_sec / freq) -* ns = cycles * (10^9 / (cpu_khz * 10^3)) -* ns = cycles * (10^6 / cpu_khz) -* -* Then we use scaling math (suggested by [email protected]) to get: -* ns = cycles * (10^6 * SC / cpu_khz) / SC -* ns = cycles * cyc2ns_scale / SC -* -* And since SC is a constant power of two, we can convert the div -* into a shift. -* -* We can use khz divisor instead of mhz to keep a better precision, since -* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. -* ([email protected]) -* -* [email protected] "math is hard, lets go shopping!" -*/ - -#define CYC2NS_SCALE_FACTOR 10/* 2^10, carefully chosen */ #if defined(CONFIG_CYCLES_CLOCKSOURCE )
@@ -63,7 +40,6 @@ static struct clocksource bfin_cs_cycles = { .rating = 400, .read = bfin_read_cycles, .mask = CLOCKSOURCE_MASK(64), - .shift = CYC2NS_SCALE_FACTOR, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -75,10 +51,7 @@ static inline unsigned long long bfin_cs_cycles_sched_clock(void)static int __init bfin_cs_cycles_init (void ) { - bfin_cs_cycles.mult = \ -clocksource_hz2mult (get_cclk (), bfin_cs_cycles.shift); - -if (clocksource_register (&bfin_cs_cycles)) +if (clocksource_register_hz (&bfin_cs_cycles,get_cclk ()))panic ("failed to register clocksource" );return 0 ;
@@ -111,7 +84,6 @@ static struct clocksource bfin_cs_gptimer0 = { .rating = 350, .read = bfin_read_gptimer0, .mask = CLOCKSOURCE_MASK(32), - .shift = CYC2NS_SCALE_FACTOR, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -125,10 +97,7 @@ static int __init bfin_cs_gptimer0_init(void) {setup_gptimer0 (); - bfin_cs_gptimer0.mult = \ -clocksource_hz2mult (get_sclk (), bfin_cs_gptimer0.shift); - -if (clocksource_register (&bfin_cs_gptimer0)) +if (clocksource_register_hz (&bfin_cs_gptimer0,get_sclk ()))panic ("failed to register clocksource" );return 0 ;
arch/ia64/kernel/cyclone.c +1 -5
@@ -31,8 +31,6 @@ static struct clocksource clocksource_cyclone = { .rating = 300, .read = read_cyclone, .mask = (1LL << 40) - 1, - .mult = 0, /*to be calculated*/ - .shift = 16, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -118,9 +116,7 @@ int __init init_cyclone_clock(void)/* initialize last tick */ cyclone_mc = cyclone_timer; clocksource_cyclone.fsys_mmio = cyclone_timer; - clocksource_cyclone.mult =clocksource_hz2mult (CYCLONE_TIMER_FREQ , - clocksource_cyclone.shift); -clocksource_register (&clocksource_cyclone); +clocksource_register_hz (&clocksource_cyclone,CYCLONE_TIMER_FREQ );return 0 ; }
arch/ia64/kernel/time.c +2 -7
@@ -73,8 +73,6 @@ static struct clocksource clocksource_itc = { .rating = 350, .read = itc_get_cycles, .mask = CLOCKSOURCE_MASK(64), - .mult = 0, /*to be calculated*/ - .shift = 16, .flags =CLOCK_SOURCE_IS_CONTINUOUS , #ifdef CONFIG_PARAVIRT .resume = paravirt_clocksource_resume,
@@ -365,11 +363,8 @@ ia64_init_itm (void)ia64_cpu_local_tick ();if (!itc_clocksource) { -/* Sort out mult/shift values: */ - clocksource_itc.mult = -clocksource_hz2mult (local_cpu_data->itc_freq, - clocksource_itc.shift); -clocksource_register (&clocksource_itc); +clocksource_register_hz (&clocksource_itc, + local_cpu_data->itc_freq); itc_clocksource = &clocksource_itc; } }
arch/ia64/sn/kernel/sn2/timer.c +1 -5
@@ -33,8 +33,6 @@ static struct clocksource clocksource_sn2 = { .rating = 450, .read = read_sn2, .mask = (1LL << 55) - 1, - .mult = 0, - .shift = 10, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -57,9 +55,7 @@ ia64_sn_udelay (unsigned long usecs)void __init sn_timer_init (void ) { clocksource_sn2.fsys_mmio =RTC_COUNTER_ADDR ; - clocksource_sn2.mult =clocksource_hz2mult (sn_rtc_cycles_per_second, - clocksource_sn2.shift); -clocksource_register (&clocksource_sn2); +clocksource_register_hz (&clocksource_sn2, sn_rtc_cycles_per_second); ia64_udelay = &ia64_sn_udelay; }
arch/microblaze/kernel/timer.c +1 -5
@@ -217,16 +217,12 @@ static struct clocksource clocksource_microblaze = { .rating = 300, .read = microblaze_read, .mask = CLOCKSOURCE_MASK(32), - .shift = 8, /* I can shift it */ .flags = CLOCK_SOURCE_IS_CONTINUOUS, };static int __init microblaze_clocksource_init (void ) { - clocksource_microblaze.mult = -clocksource_hz2mult (timer_clock_freq, - clocksource_microblaze.shift); -if (clocksource_register (&clocksource_microblaze)) +if (clocksource_register_hz (&clocksource_microblaze, timer_clock_freq))panic ("failed to register clocksource" );/* stop timer1 */
arch/mips/Kconfig +1 -0
@@ -2339,6 +2339,7 @@ config MMU config I8253 bool + select CLKSRC_I8253 select MIPS_EXTERNAL_TIMER config ZONE_DMA32
arch/mips/alchemy/common/time.c +1 -2
@@ -141,8 +141,7 @@ static int __init alchemy_time_init(unsigned int m2int) goto cntr_err;/* register counter1 clocksource and event device */ -clocksource_set_clock (&au1x_counter1_clocksource,32768 ); -clocksource_register (&au1x_counter1_clocksource); +clocksource_register_hz (&au1x_counter1_clocksource,32768 ); cd->shift =32 ; cd->mult =div_sc (32768 ,NSEC_PER_SEC , cd->shift);
arch/mips/cavium-octeon/csrc-octeon.c +1 -2
@@ -105,8 +105,7 @@ unsigned long long notrace sched_clock(void)void __init plat_time_init (void ) { clocksource_mips.rating =300 ; -clocksource_set_clock (&clocksource_mips,octeon_get_clock_rate ()); -clocksource_register (&clocksource_mips); +clocksource_register_hz (&clocksource_mips,octeon_get_clock_rate ()); }static u64 octeon_udelay_factor;
arch/mips/include/asm/i8253.h +5 -0
@@ -12,8 +12,13 @@#define PIT_CH0 0x40#define PIT_CH2 0x42 +#define PIT_LATCH LATCH +extern raw_spinlock_t i8253_lock;extern void setup_pit_timer (void ); +#define inb_pit inb_p +#define outb_pit outb_p +#endif /* __ASM_I8253_H */
arch/mips/include/asm/time.h +0 -6
@@ -84,12 +84,6 @@ static inline int init_mips_clocksource(void)#endif } -static inline void clocksource_set_clock (struct clocksource *cs, -unsigned int clock) -{ -clocksource_calc_mult_shift (cs, clock,4 ); -} -static inline void clockevent_set_clock (struct clock_event_device *cd,unsigned int clock) {
arch/mips/jz4740/time.c +1 -2
@@ -121,8 +121,7 @@ void __init plat_time_init(void)clockevents_register_device (&jz4740_clockevent); -clocksource_set_clock (&jz4740_clocksource, clk_rate); - ret =clocksource_register (&jz4740_clocksource); + ret =clocksource_register_hz (&jz4740_clocksource, clk_rate);if (ret)printk (KERN_ERR "Failed to register clocksource: %d\n" , ret);
arch/mips/kernel/cevt-txx9.c +1 -2
@@ -51,8 +51,7 @@ void __init txx9_clocksource_init(unsigned long baseaddr, {struct txx9_tmr_reg __iomem *tmrptr; -clocksource_set_clock (&txx9_clocksource.cs,TIMER_CLK (imbusclk)); -clocksource_register (&txx9_clocksource.cs); +clocksource_register_hz (&txx9_clocksource.cs,TIMER_CLK (imbusclk)); tmrptr =ioremap (baseaddr,sizeof (struct txx9_tmr_reg ));__raw_writel (TCR_BASE , &tmrptr->tcr);
arch/mips/kernel/csrc-bcm1480.c +1 -2
@@ -49,6 +49,5 @@ void __init sb1480_clocksource_init(void) plldiv =G_BCM1480_SYS_PLL_DIV (__raw_readq (IOADDR (A_SCD_SYSTEM_CFG ))); zbbus = ((plldiv >>1 ) *50000000 ) + ((plldiv &1 ) *25000000 ); -clocksource_set_clock (cs, zbbus); -clocksource_register (cs); +clocksource_register_hz (cs, zbbus); }
arch/mips/kernel/csrc-ioasic.c +1 -3
@@ -59,7 +59,5 @@ void __init dec_ioasic_clocksource_init(void)printk (KERN_INFO "I/O ASIC clock frequency %dHz\n" , freq); clocksource_dec.rating =200 + freq /10000000 ; -clocksource_set_clock (&clocksource_dec, freq); - -clocksource_register (&clocksource_dec); +clocksource_register_hz (&clocksource_dec, freq); }
arch/mips/kernel/csrc-powertv.c +3 -32
@@ -78,9 +78,7 @@ static void __init powertv_c0_hpt_clocksource_init(void) clocksource_mips.rating =200 + mips_hpt_frequency /10000000 ; -clocksource_set_clock (&clocksource_mips, mips_hpt_frequency); - -clocksource_register (&clocksource_mips); +clocksource_register_hz (&clocksource_mips, mips_hpt_frequency); }/**
@@ -130,43 +128,16 @@ static struct clocksource clocksource_tim_c = {/** * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock * -* The hard part here is coming up with a constant k and shift s such that -* the 48-bit TIM_C value multiplied by k doesn't overflow and that value, -* when shifted right by s, yields the corresponding number of nanoseconds. * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to -* 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the -* number of nanoseconds. Since the TIM_C value has 48 bits and the math is -* done in 64 bits, avoiding an overflow means that k must be less than -* 64 - 48 = 16 bits. +* 1 / (27,000,000/8) seconds. */ static void __init powertv_tim_c_clocksource_init (void ) { -int prescale; -unsigned long dividend; -unsigned long k; -int s; -const int max_k_bits = (64 -48 ) -1 ; -const unsigned long billion =1000000000 ;const unsigned long counts_per_second =27000000 /8 ; - prescale =BITS_PER_LONG -ilog2 (billion) -1 ; - dividend = billion << prescale; - k = dividend / counts_per_second; - s =ilog2 (k) - max_k_bits; - -if (s <0 ) - s = prescale; - -else { - k >>= s; - s += prescale; - } - - clocksource_tim_c.mult = k; - clocksource_tim_c.shift = s; clocksource_tim_c.rating =200 ; -clocksource_register (&clocksource_tim_c); +clocksource_register_hz (&clocksource_tim_c, counts_per_second); tim_c = (struct tim_c *)asic_reg_addr (tim_ch); }
arch/mips/kernel/csrc-r4k.c +1 -3
@@ -30,9 +30,7 @@ int __init init_r4k_clocksource(void)/* Calculate a somewhat reasonable rating value */ clocksource_mips.rating =200 + mips_hpt_frequency /10000000 ; -clocksource_set_clock (&clocksource_mips, mips_hpt_frequency); - -clocksource_register (&clocksource_mips); +clocksource_register_hz (&clocksource_mips, mips_hpt_frequency);return 0 ; }
arch/mips/kernel/csrc-sb1250.c +1 -2
@@ -65,6 +65,5 @@ void __init sb1250_clocksource_init(void)IOADDR (A_SCD_TIMER_REGISTER (SB1250_HPT_NUM , R_SCD_TIMER_CFG))); -clocksource_set_clock (cs,V_SCD_TIMER_FREQ ); -clocksource_register (cs); +clocksource_register_hz (cs,V_SCD_TIMER_FREQ ); }
arch/mips/kernel/i8253.c +1 -77
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arch/mips/loongson/common/cs5536/cs5536_mfgpt.c +1 -4
@@ -201,8 +201,6 @@ static struct clocksource clocksource_mfgpt = { .rating = 120, /* Functional for real use, but not desired */ .read = mfgpt_read, .mask = CLOCKSOURCE_MASK(32), - .mult = 0, - .shift = 22, };int __init init_mfgpt_clocksource (void )
@@ -210,8 +208,7 @@ int __init init_mfgpt_clocksource(void)if (num_possible_cpus () >1 )/* MFGPT does not scale! */ return 0 ; - clocksource_mfgpt.mult =clocksource_hz2mult (MFGPT_TICK_RATE ,22 ); -return clocksource_register (&clocksource_mfgpt); +return clocksource_register_hz (&clocksource_mfgpt,MFGPT_TICK_RATE ); }arch_initcall (init_mfgpt_clocksource);
arch/mips/sgi-ip27/ip27-timer.c +1 -2
@@ -174,8 +174,7 @@ static void __init hub_rt_clocksource_init(void) {struct clocksource *cs = &hub_rt_clocksource; -clocksource_set_clock (cs,CYCLES_PER_SEC ); -clocksource_register (cs); +clocksource_register_hz (cs,CYCLES_PER_SEC ); }void __init plat_time_init (void )
arch/x86/Kconfig +1 -0
@@ -8,6 +8,7 @@ config 64BIT config X86_32 def_bool !64BIT + select CLKSRC_I8253 config X86_64 def_bool 64BIT
arch/x86/include/asm/i8253.h +2 -0
@@ -6,6 +6,8 @@#define PIT_CH0 0x40#define PIT_CH2 0x42 +#define PIT_LATCH LATCH +extern raw_spinlock_t i8253_lock;extern struct clock_event_device *global_clock_event;
arch/x86/kernel/apb_timer.c +1 -9
@@ -177,7 +177,6 @@ static struct clocksource clocksource_apbt = { .rating = APBT_CLOCKSOURCE_RATING, .read = apbt_read_clocksource, .mask = APBT_MASK, - .shift = APBT_SHIFT, .flags = CLOCK_SOURCE_IS_CONTINUOUS, .resume = apbt_restart_clocksource, };
@@ -543,14 +542,7 @@ static int apbt_clocksource_register(void)if (t1 ==apbt_read_clocksource (&clocksource_apbt))panic ("APBT counter not counting. APBT disabled\n" ); -/* -* initialize and register APBT clocksource -* convert that to ns/clock cycle -* mult = (ns/c) * 2^APBT_SHIFT -*/ - clocksource_apbt.mult =div_sc (MSEC_PER_SEC , - (unsigned long ) apbt_freq,APBT_SHIFT ); -clocksource_register (&clocksource_apbt); +clocksource_register_khz (&clocksource_apbt, (u32 )apbt_freq*1000 );return 0 ; }
arch/x86/kernel/hpet.c +16 -56
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arch/x86/kernel/i8253.c +2 -84
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arch/x86/kernel/kvmclock.c +1 -5
@@ -26,8 +26,6 @@#include <asm/x86_init.h> #include <asm/reboot.h> -#define KVM_SCALE 22 -static int kvmclock =1 ;static int msr_kvm_system_time =MSR_KVM_SYSTEM_TIME ;static int msr_kvm_wall_clock =MSR_KVM_WALL_CLOCK ;
@@ -120,8 +118,6 @@ static struct clocksource kvm_clock = { .read = kvm_clock_get_cycles, .rating = 400, .mask = CLOCKSOURCE_MASK(64), - .mult = 1 << KVM_SCALE, - .shift = KVM_SCALE, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -203,7 +199,7 @@ void __init kvmclock_init(void) machine_ops.crash_shutdown = kvm_crash_shutdown;#endif kvm_get_preset_lpj (); -clocksource_register (&kvm_clock); +clocksource_register_hz (&kvm_clock,NSEC_PER_SEC ); pv_info.paravirt_enabled =1 ; pv_info.name ="KVM" ;
arch/x86/lguest/boot.c +1 -3
@@ -913,8 +913,6 @@ static struct clocksource lguest_clock = { .rating = 200, .read = lguest_clock_read, .mask = CLOCKSOURCE_MASK(64), - .mult = 1 << 22, - .shift = 22, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -997,7 +995,7 @@ static void lguest_time_init(void)/* Set up the timer interrupt (0) to go to our simple timer routine */ irq_set_handler (0 , lguest_time_irq); -clocksource_register (&lguest_clock); +clocksource_register_hz (&lguest_clock,NSEC_PER_SEC );/* We can't set cpumask in the initializer: damn C limitations! Set it * here and register our timer device. */
arch/x86/platform/uv/uv_time.c +1 -5
@@ -40,7 +40,6 @@ static struct clocksource clocksource_uv = { .rating = 400, .read = uv_read_rtc, .mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK, - .shift = 10, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -372,14 +371,11 @@ static __init int uv_rtc_setup_clock(void)if (!is_uv_system ())return -ENODEV ; - clocksource_uv.mult =clocksource_hz2mult (sn_rtc_cycles_per_second, - clocksource_uv.shift); -/* If single blade, prefer tsc */ if (uv_num_possible_blades () ==1 ) clocksource_uv.rating =250 ; - rc =clocksource_register (&clocksource_uv); + rc =clocksource_register_hz (&clocksource_uv, sn_rtc_cycles_per_second);if (rc)printk (KERN_INFO "UV RTC clocksource failed rc %d\n" , rc);else
arch/x86/xen/time.c +1 -5
@@ -26,8 +26,6 @@#include "xen-ops.h" -#define XEN_SHIFT 22 -/* Xen may fire a timer up to this many ns early */ #define TIMER_SLOP 100000#define NS_PER_TICK (1000000000LL / HZ)
@@ -211,8 +209,6 @@ static struct clocksource xen_clocksource __read_mostly = { .rating = 400, .read = xen_clocksource_get_cycles, .mask = ~0, - .mult = 1<<XEN_SHIFT, /* time directly in nanoseconds */ - .shift = XEN_SHIFT, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -448,7 +444,7 @@ static __init void xen_time_init(void)int cpu =smp_processor_id ();struct timespec tp; -clocksource_register (&xen_clocksource); +clocksource_register_hz (&xen_clocksource,NSEC_PER_SEC );if (HYPERVISOR_vcpu_op (VCPUOP_stop_periodic_timer, cpu,NULL ) ==0 ) {/* Successfully turned off 100Hz tick, so we have the
drivers/Kconfig +3 -0
@@ -119,4 +119,7 @@ source "drivers/platform/Kconfig" source "drivers/clk/Kconfig" source "drivers/hwspinlock/Kconfig" + +source "drivers/clocksource/Kconfig" + endmenu
drivers/char/hpet.c +1 -5
@@ -84,8 +84,6 @@ static struct clocksource clocksource_hpet = { .rating = 250, .read = read_hpet, .mask = CLOCKSOURCE_MASK(64), - .mult = 0, /* to be calculated */ - .shift = 10, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };static struct clocksource *hpet_clocksource;
@@ -934,9 +932,7 @@ int hpet_alloc(struct hpet_data *hdp)if (!hpet_clocksource) { hpet_mctr = (void __iomem *)&hpetp->hp_hpet->hpet_mc;CLKSRC_FSYS_MMIO_SET (clocksource_hpet.fsys_mmio, hpet_mctr); - clocksource_hpet.mult =clocksource_hz2mult (hpetp->hp_tick_freq, - clocksource_hpet.shift); -clocksource_register (&clocksource_hpet); +clocksource_register_hz (&clocksource_hpet, hpetp->hp_tick_freq); hpetp->hp_clocksource = &clocksource_hpet; hpet_clocksource = &clocksource_hpet; }
drivers/clocksource/Kconfig new file +2 -0
@@ -0,0 +1,2 @@ +config CLKSRC_I8253 + bool
drivers/clocksource/Makefile +1 -0
@@ -6,3 +6,4 @@ obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o +obj-$(CONFIG_CLKSRC_I8253) += i8253.o
drivers/clocksource/cyclone.c +2 -8
@@ -29,8 +29,6 @@ static struct clocksource clocksource_cyclone = { .rating = 250, .read = read_cyclone, .mask = CYCLONE_TIMER_MASK, - .mult = 10, - .shift = 0, .flags = CLOCK_SOURCE_IS_CONTINUOUS, };
@@ -108,12 +106,8 @@ static int __init init_cyclone_clocksource(void) } cyclone_ptr = cyclone_timer; -/* sort out mult/shift values: */ - clocksource_cyclone.shift =22 ; - clocksource_cyclone.mult =clocksource_hz2mult (CYCLONE_TIMER_FREQ , - clocksource_cyclone.shift); - -return clocksource_register (&clocksource_cyclone); +return clocksource_register_hz (&clocksource_cyclone, +CYCLONE_TIMER_FREQ ); }arch_initcall (init_cyclone_clocksource);
drivers/clocksource/i8253.c new file +88 -0
88 lines not on this page · raw message
include/linux/clockchips.h +34 -22
86 lines not on this page · raw message
include/linux/clocksource.h +16 -18
@@ -159,42 +159,38 @@ extern u64 timecounter_cyc2time(struct timecounter *tc,*/ struct clocksource {/* -* First part of structure is read mostly +* Hotpath data, fits in a single cache line when the +* clocksource itself is cacheline aligned. */ -char *name; -struct list_head list; -int rating;cycle_t (*read)(struct clocksource *cs); -int (*enable)(struct clocksource *cs); -void (*disable)(struct clocksource *cs); +cycle_t cycle_last;cycle_t mask;u32 mult;u32 shift;u64 max_idle_ns; -unsigned long flags; -cycle_t (*vread)(void ); -void (*suspend)(struct clocksource *cs); -void (*resume)(struct clocksource *cs); +#ifdef CONFIG_IA64 void *fsys_mmio;/* used by fsyscall asm code */ #define CLKSRC_FSYS_MMIO_SET (mmio, addr) ((mmio) = (addr))#else #define CLKSRC_FSYS_MMIO_SET (mmio, addr) do { } while (0)#endif - -/* -* Second part is written at each timer interrupt -* Keep it in a different cache line to dirty no -* more than one cache line. -*/ -cycle_t cycle_last____cacheline_aligned_in_smp ; +const char *name; +struct list_head list; +int rating; +cycle_t (*vread)(void ); +int (*enable)(struct clocksource *cs); +void (*disable)(struct clocksource *cs); +unsigned long flags; +void (*suspend)(struct clocksource *cs); +void (*resume)(struct clocksource *cs);#ifdef CONFIG_CLOCKSOURCE_WATCHDOG /* Watchdog related data, used by the framework */ struct list_head wd_list;cycle_t wd_last;#endif -}; +}____cacheline_aligned ;/* * Clock source flags bits::
@@ -341,4 +337,6 @@ static inline void update_vsyscall_tz(void)extern void timekeeping_notify (struct clocksource *clock); +extern int clocksource_i8253_init (void ); +#endif /* _LINUX_CLOCKSOURCE_H */
kernel/time/clockevents.c +64 -0
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kernel/time/clocksource.c +19 -19
@@ -626,19 +626,6 @@ static void clocksource_enqueue(struct clocksource *cs)list_add (&cs->list, entry); } - -/* -* Maximum time we expect to go between ticks. This includes idle -* tickless time. It provides the trade off between selecting a -* mult/shift pair that is very precise but can only handle a short -* period of time, vs. a mult/shift pair that can handle long periods -* of time but isn't as precise. -* -* This is a subsystem constant, and actual hardware limitations -* may override it (ie: clocksources that wrap every 3 seconds). -*/ -#define MAX_UPDATE_LENGTH 5/* Seconds */ -/** * __clocksource_updatefreq_scale - Used update clocksource with new freq * @t: clocksource to be registered
@@ -652,15 +639,28 @@ static void clocksource_enqueue(struct clocksource *cs)*/ void __clocksource_updatefreq_scale (struct clocksource *cs,u32 scale,u32 freq) { +unsigned long sec; +/* -* Ideally we want to use some of the limits used in -* clocksource_max_deferment, to provide a more informed -* MAX_UPDATE_LENGTH. But for now this just gets the -* register interface working properly. +* Calc the maximum number of seconds which we can run before +* wrapping around. For clocksources which have a mask > 32bit +* we need to limit the max sleep time to have a good +* conversion precision. 10 minutes is still a reasonable +* amount. That results in a shift value of 24 for a +* clocksource with mask >= 40bit and f >= 4GHz. That maps to +* ~ 0.06ppm granularity for NTP. We apply the same 12.5% +* margin as we do in clocksource_max_deferment() */ + sec = (cs->mask - (cs->mask >>5 )); +do_div (sec, freq); +do_div (sec, scale); +if (!sec) + sec =1 ; +else if (sec >600 && cs->mask >UINT_MAX ) + sec =600 ; +clocks_calc_mult_shift (&cs->mult, &cs->shift, freq, -NSEC_PER_SEC /scale, -MAX_UPDATE_LENGTH *scale); +NSEC_PER_SEC / scale, sec * scale); cs->max_idle_ns =clocksource_max_deferment (cs); }EXPORT_SYMBOL_GPL (__clocksource_updatefreq_scale);