drxk: Add a fallback method for QAM parameter setting
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH 1/21 drxk: add drxk prefix to the errors
It is hard to identify the origin for those errors without a prefix to indicate which driver produced them:
[ 1390.220984] i2c_write error [ 1390.224133] I2C Write error [ 1391.284202] i2c_read error [ 1392.288685] i2c_read error
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +25 -24
@@ -317,7 +317,7 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) .addr = adr, .flags = 0, .buf = data, .len = len };if (i2c_transfer (adap, &msg,1 ) !=1 ) { -printk (KERN_ERR "i2c_write error\n" ); +printk (KERN_ERR "drxk: i2c write error at addr 0x%02x\n" , adr);return -1 ; }return 0 ;
@@ -332,7 +332,7 @@ static int i2c_read(struct i2c_adapter *adap, .buf = answ, .len = alen} };if (i2c_transfer (adap, msgs,2 ) !=2 ) { -printk (KERN_ERR "i2c_read error\n" ); +printk (KERN_ERR "drxk: i2c read error at addr 0x%02x\n" , adr);return -1 ; }return 0 ;
@@ -479,7 +479,8 @@ static int WriteBlock(struct drxk_state *state, u32 Address, status =i2c_write (state->i2c, state->demod_address, &state->Chunk[0 ], Chunk + AdrLength);if (status <0 ) { -printk (KERN_ERR "I2C Write error\n" ); +printk (KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n" , + __func__, Address);break ; } pBlock += Chunk;
@@ -505,7 +506,7 @@ int PowerUpDevice(struct drxk_state *state) data =0 ;if (i2c_write (state->i2c, state->demod_address, &data,1 ) <0 ) -printk (KERN_ERR "powerup failed\n" ); +printk (KERN_ERR "drxk: powerup failed\n" );msleep (10 ); retryCount++; } while (i2c_read1(state->i2c,
@@ -989,7 +990,7 @@ static int GetDeviceCapabilities(struct drxk_state *state) state->m_hasIRQN = false;break ;default : -printk (KERN_ERR "DeviceID not supported = %02x\n" , +printk (KERN_ERR "drxk: DeviceID not supported = %02x\n" , ((sioTopJtagidLo >>12 ) &0xFF )); status =-1 ;break ;
@@ -1256,7 +1257,7 @@ static int BLChainCmd(struct drxk_state *state, }while ((blStatus ==0x1 ) && ((time_is_after_jiffies (end))));if (blStatus ==0x1 ) { -printk (KERN_ERR "SIO not ready\n" ); +printk (KERN_ERR "drxk: SIO not ready\n" );mutex_unlock (&state->mutex);return -1 ; }
@@ -1344,7 +1345,7 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)break ; }while ((data != desiredStatus) && ((time_is_after_jiffies (end))));if (data != desiredStatus) { -printk (KERN_ERR "SIO not ready\n" ); +printk (KERN_ERR "drxk: SIO not ready\n" );return -1 ; }return status;
@@ -1419,7 +1420,7 @@ static int scu_command(struct drxk_state *state, }while (!(curCmd ==DRX_SCU_READY ) && (time_is_after_jiffies (end)));if (curCmd !=DRX_SCU_READY ) { -printk (KERN_ERR "SCU not ready\n" ); +printk (KERN_ERR "drxk: SCU not ready\n" );mutex_unlock (&state->mutex);return -1 ; }
@@ -1439,18 +1440,18 @@ static int scu_command(struct drxk_state *state,/* check a few fixed error codes */ if (err ==SCU_RESULT_UNKSTD ) { -printk (KERN_ERR "SCU_RESULT_UNKSTD\n" ); +printk (KERN_ERR "drxk: SCU_RESULT_UNKSTD\n" );mutex_unlock (&state->mutex);return -1 ; }else if (err ==SCU_RESULT_UNKCMD ) { -printk (KERN_ERR "SCU_RESULT_UNKCMD\n" ); +printk (KERN_ERR "drxk: SCU_RESULT_UNKCMD\n" );mutex_unlock (&state->mutex);return -1 ; }/* here it is assumed that negative means error, and positive no error */ else if (err <0 ) { -printk (KERN_ERR "%s ERROR\n" , __func__); +printk (KERN_ERR "drxk: %s ERROR\n" , __func__);mutex_unlock (&state->mutex);return -1 ; }
@@ -1458,7 +1459,7 @@ static int scu_command(struct drxk_state *state, }while (0 );mutex_unlock (&state->mutex);if (status <0 ) -printk (KERN_ERR "%s: status = %d\n" , __func__, status); +printk (KERN_ERR "drxk: %s: status = %d\n" , __func__, status);return status; }
@@ -2720,7 +2721,7 @@ static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,break ; }while ((blStatus ==0x1 ) &&time_is_after_jiffies (end));if (blStatus ==0x1 ) { -printk (KERN_ERR "SIO not ready\n" ); +printk (KERN_ERR "drxk: SIO not ready\n" );mutex_unlock (&state->mutex);return -1 ; }
@@ -3534,7 +3535,7 @@ static int SetDVBTStandard(struct drxk_state *state, }while (0 );if (status <0 ) -printk (KERN_ERR "%s status - %08x\n" , __func__, status); +printk (KERN_ERR "drxk: %s status - %08x\n" , __func__, status);return status; }
@@ -3589,7 +3590,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,u16 param1;int status; -/* printk(KERN_DEBUG "%s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */ +/* printk(KERN_DEBUG "drxk: %s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */ do { status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); if (status < 0)
@@ -4089,7 +4090,7 @@ static int SetQAMMeasurement(struct drxk_state *state, }while (0 );if (status <0 ) -printk (KERN_ERR "%s: status - %08x\n" , __func__, status); +printk (KERN_ERR "drxk: %s: status - %08x\n" , __func__, status);return status; }
@@ -5107,7 +5108,7 @@ static int QAMSetSymbolrate(struct drxk_state *state)/* Select & calculate correct IQM rate */ adcFrequency = (state->m_sysClockFreq *1000 ) /3 ; ratesel =0 ; -/* printk(KERN_DEBUG "SR %d\n", state->param.u.qam.symbol_rate); */ +/* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */ if (state->param.u.qam.symbol_rate <=1188750 ) ratesel =3 ;else if (state->param.u.qam.symbol_rate <=2377500 )
@@ -5174,7 +5175,7 @@ static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK ,0 ,NULL ,2 , Result);if (status <0 ) -printk (KERN_ERR "%s status = %08x\n" , __func__, status); +printk (KERN_ERR "drxk: %s status = %08x\n" , __func__, status);if (Result[1 ] <SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED ) {/* 0x0000 NOT LOCKED */
@@ -5444,7 +5445,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, }while (0 );if (status <0 ) -printk (KERN_ERR "%s %d\n" , __func__, status); +printk (KERN_ERR "drxk: %s %d\n" , __func__, status);return status; }
@@ -5734,9 +5735,9 @@ static int load_microcode(struct drxk_state *state, char *mc_name) err =request_firmware (&fw, mc_name, state->i2c->dev.parent);if (err <0 ) {printk (KERN_ERR -"Could not load firmware file %s.\n" , mc_name); +"drxk: Could not load firmware file %s.\n" , mc_name);printk (KERN_INFO -"Copy %s to your hotplug directory!\n" , mc_name); +"drxk: Copy %s to your hotplug directory!\n" , mc_name);return err; } err =DownloadMicrocode (state, fw->data, fw->size);
@@ -5970,7 +5971,7 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) {struct drxk_state *state = fe->demodulator_priv; -/* printk(KERN_DEBUG "drxk_gate %d\n", enable); */ +/* printk(KERN_DEBUG "drxk: drxk_gate %d\n", enable); */ return ConfigureI2CBridge (state, enable ? true : false); }
@@ -5990,7 +5991,7 @@ static int drxk_set_parameters(struct dvb_frontend *fe, fe->ops.tuner_ops.get_frequency (fe, &IF );Start (state,0 ,IF ); -/* printk(KERN_DEBUG "%s IF=%d done\n", __func__, IF); */ +/* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */ return 0 ; }
@@ -6068,7 +6069,7 @@ static void drxk_t_release(struct dvb_frontend *fe)#if 0 struct drxk_state *state = fe->demodulator_priv; -printk (KERN_DEBUG "%s\n" , __func__); +printk (KERN_DEBUG "drxk: %s\n" , __func__);kfree (state);#endif }
Signature · 1 line
1.7.1
PATCH 2/21 tda18271c2dd: add tda18271c2dd prefix to the errors
In reply to a message not in the archiveIt is hard to identify the origin for those errors without a prefix to indicate which driver produced them:
[ 1390.220984] i2c_write error [ 1390.224133] I2C Write error [ 1391.284202] i2c_read error [ 1392.288685] i2c_read error
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/tda18271c2dd.c +5 -5
@@ -130,7 +130,7 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) .buf = data, .len = len};if (i2c_transfer (adap, &msg,1 ) !=1 ) { -printk (KERN_ERR "i2c_write error\n" ); +printk (KERN_ERR "tda18271c2dd: i2c write error at addr %i\n" , adr);return -1 ; }return 0 ;
@@ -582,7 +582,7 @@ static int RFTrackingFiltersInit(struct tda_state *state, state->m_RF3[RFBand] =RF3 ;#if 0 -printk (KERN_ERR "%s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n" , __func__, +printk (KERN_ERR "tda18271c2dd: %s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n" , __func__, RFBand,RF1 , state->m_RF_A1[RFBand], state->m_RF_B1[RFBand],RF2 , state->m_RF_A2[RFBand], state->m_RF_B2[RFBand],RF3 );#endif
@@ -610,7 +610,7 @@ static int PowerScan(struct tda_state *state, SearchMap1(m_GainTaper_Map, RF_in, &Gain_Taper) && SearchMap3(m_CID_Target_Map, RF_in, &CID_Target, &CountLimit))) { -printk (KERN_ERR "%s Search map failed\n" , __func__); +printk (KERN_ERR "tda18271c2dd: %s Search map failed\n" , __func__);return -EINVAL ; }
@@ -991,7 +991,7 @@ static int ChannelConfiguration(struct tda_state *state,u8 IR_Meas =0 ; state->IF = IntermediateFrequency; -/* printk("%s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ +/* printk("tda18271c2dd: %s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ /* get values from tables */ if (!(SearchMap1(m_BP_Filter_Map, Frequency, &BP_Filter) &&
@@ -999,7 +999,7 @@ static int ChannelConfiguration(struct tda_state *state, SearchMap1(m_IR_Meas_Map, Frequency, &IR_Meas) && SearchMap4(m_RF_Band_Map, Frequency, &RF_Band))) { -printk (KERN_ERR "%s SearchMap failed\n" , __func__); +printk (KERN_ERR "tda18271c2dd: %s SearchMap failed\n" , __func__);return -EINVAL ; }
Signature · 1 line
1.7.1
PATCH 3/21 drxk: Add debug printk's
In reply to a message not in the archiveThis is a complex driver. Adding support for other devices with drxk requires to be able to debug it and see where it is failing. So, add optional printk messages to allow debugging it.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +181 -4
@@ -173,6 +173,16 @@ bool IsA1WithRomCode(struct drxk_state *state)#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520) +static unsigned int debug; +module_param (debug, int,0644 ); +MODULE_PARM_DESC (debug,"enable debug messages" ); + +#define dprintk(level, fmt, arg...) do { \ +if (debug >= level) \ + printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \ +} while (0) + +static inline u32 MulDiv32 (u32 a,u32 b,u32 c) {u64 tmp64;
@@ -316,6 +326,13 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)struct i2c_msg msg = { .addr = adr, .flags =0 , .buf = data, .len = len }; +dprintk (3 ,":" ); +if (debug >2 ) { +int i; +for (i =0 ; i < len; i++) +printk (KERN_CONT " %02x" , data[i]); +printk (KERN_CONT "\n" ); + }if (i2c_transfer (adap, &msg,1 ) !=1 ) {printk (KERN_ERR "drxk: i2c write error at addr 0x%02x\n" , adr);return -1 ;
@@ -331,10 +348,27 @@ static int i2c_read(struct i2c_adapter *adap, {.addr = adr, .flags = I2C_M_RD, .buf = answ, .len = alen} }; +dprintk (3 ,":" ); +if (debug >2 ) { +int i; +for (i =0 ; i < len; i++) +printk (KERN_CONT " %02x" , msg[i]); +printk (KERN_CONT "\n" ); + }if (i2c_transfer (adap, msgs,2 ) !=2 ) { +if (debug >2 ) +printk (KERN_CONT ": ERROR!\n" ); +printk (KERN_ERR "drxk: i2c read error at addr 0x%02x\n" , adr);return -1 ; } +if (debug >2 ) { +int i; +printk (KERN_CONT ": Read " ); +for (i =0 ; i < len; i++) +printk (KERN_CONT " %02x" , msg[i]); +printk (KERN_CONT "\n" ); + }return 0 ; }
@@ -355,10 +389,12 @@ static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags) mm1[1 ] = (((reg >>16 ) &0x0F ) | ((reg >>18 ) &0xF0 )); len =2 ; } +dprintk (2 ,"(0x%08x, 0x%02x)\n" , reg, flags);if (i2c_read (state->i2c, adr, mm1, len, mm2,2 ) <0 )return -1 ;if (data) *data = mm2[0 ] | (mm2[1 ] <<8 ); +return 0 ; }
@@ -384,11 +420,13 @@ static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags) mm1[1 ] = (((reg >>16 ) &0x0F ) | ((reg >>18 ) &0xF0 )); len =2 ; } +dprintk (2 ,"(0x%08x, 0x%02x)\n" , reg, flags);if (i2c_read (state->i2c, adr, mm1, len, mm2,4 ) <0 )return -1 ;if (data) *data = mm2[0 ] | (mm2[1 ] <<8 ) | (mm2[2 ] <<16 ) | (mm2[3 ] <<24 ); +return 0 ; }
@@ -411,6 +449,8 @@ static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags) } mm[len] = data &0xff ; mm[len +1 ] = (data >>8 ) &0xff ; + +dprintk (2 ,"(0x%08x, 0x%04x, 0x%02x)\n" , reg, data, flags);if (i2c_write (state->i2c, adr, mm, len +2 ) <0 )return -1 ;return 0 ;
@@ -442,6 +482,7 @@ static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags) mm[len +1 ] = (data >>8 ) &0xff ; mm[len +2 ] = (data >>16 ) &0xff ; mm[len +3 ] = (data >>24 ) &0xff ; +dprintk (2 ,"(0x%08x, 0x%08x, 0x%02x)\n" , reg, data, flags);if (i2c_write (state->i2c, adr, mm, len +4 ) <0 )return -1 ;return 0 ;
@@ -476,6 +517,14 @@ static int WriteBlock(struct drxk_state *state, u32 Address, AdrLength =2 ; }memcpy (&state->Chunk[AdrLength], pBlock, Chunk); +dprintk (2 ,"(0x%08x, 0x%02x)\n" , Address, Flags); +if (debug >1 ) { +int i; +if (pBlock) +for (i =0 ; i < Chunk; i++) +printk (KERN_CONT " %02x" , pBlock[i]); +printk (KERN_CONT "\n" ); + } status =i2c_write (state->i2c, state->demod_address, &state->Chunk[0 ], Chunk + AdrLength);if (status <0 ) {
@@ -500,6 +549,8 @@ int PowerUpDevice(struct drxk_state *state)u8 data =0 ;u16 retryCount =0 ; +dprintk (1 ,"\n" ); + status =i2c_read1 (state->i2c, state->demod_address, &data); if (status < 0) do {
@@ -592,6 +643,8 @@ static int init_state(struct drxk_state *state)u32 ulAntennaDVBC =0 ;u32 ulAntennaSwitchDVBTDVBC =0 ; +dprintk (1 ,"\n" ); + state->m_hasLNA = false; state->m_hasDVBT = false; state->m_hasDVBC = false;
@@ -794,6 +847,7 @@ static int DRXX_Open(struct drxk_state *state)u16 bid =0 ;u16 key =0 ; +dprintk (1 ,"\n" ); do { /* stop lock indicator process */ status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
@@ -825,6 +879,7 @@ static int GetDeviceCapabilities(struct drxk_state *state)u32 sioTopJtagidLo =0 ;int status; +dprintk (1 ,"\n" ); do { /* driver 0.9.0 */ /* stop lock indicator process */
@@ -1004,6 +1059,8 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)int status;bool powerdown_cmd; +dprintk (1 ,"\n" ); +/* Write command */ status =Write16_0 (state,SIO_HI_RA_RAM_CMD__A , cmd);if (status <0 )
@@ -1040,6 +1097,8 @@ static int HI_CfgCommand(struct drxk_state *state) {int status; +dprintk (1 ,"\n" ); +mutex_lock (&state->mutex); do { status = Write16_0(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
@@ -1072,6 +1131,8 @@ static int HI_CfgCommand(struct drxk_state *state)static int InitHI (struct drxk_state *state) { +dprintk (1 ,"\n" ); + state->m_HICfgWakeUpKey = (state->demod_address <<1 ); state->m_HICfgTimeout =0x96FF ;/* port/bridge/power down ctrl */
@@ -1085,6 +1146,7 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)u16 sioPdrMclkCfg =0 ;u16 sioPdrMdxCfg =0 ; +dprintk (1 ,"\n" ); do { /* stop lock indicator process */ status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
@@ -1223,6 +1285,8 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)static int MPEGTSDisable (struct drxk_state *state) { +dprintk (1 ,"\n" ); +return MPEGTSConfigurePins (state, false); }
@@ -1233,6 +1297,8 @@ static int BLChainCmd(struct drxk_state *state,int status;unsigned long end; +dprintk (1 ,"\n" ); +mutex_lock (&state->mutex); do { status = Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
@@ -1281,6 +1347,8 @@ static int DownloadMicrocode(struct drxk_state *state,u32 i;int status =0 ; +dprintk (1 ,"\n" ); +/* down the drain (we don care about MAGIC_WORD) */ Drain = (pSrc[0 ] <<8 ) | pSrc[1 ]; pSrc +=sizeof (u16);
@@ -1323,6 +1391,8 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)u16 desiredStatus =SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED ;unsigned long end; +dprintk (1 ,"\n" ); +if (enable == false) { desiredCtrl =SIO_OFDM_SH_OFDM_RING_ENABLE_OFF ; desiredStatus =SIO_OFDM_SH_OFDM_RING_STATUS_DOWN ;
@@ -1357,6 +1427,8 @@ static int MPEGTSStop(struct drxk_state *state)u16 fecOcSncMode =0 ;u16 fecOcIprMode =0 ; +dprintk (1 ,"\n" ); + do { /* Gracefull shutdown (byte boundaries) */ status = Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
@@ -1390,6 +1462,8 @@ static int scu_command(struct drxk_state *state,int status;unsigned long end; +dprintk (1 ,"\n" ); +if ((cmd ==0 ) || ((parameterLen >0 ) && (parameter ==NULL )) || ((resultLen >0 ) && (result ==NULL )))return -1 ;
@@ -1469,6 +1543,8 @@ static int SetIqmAf(struct drxk_state *state, bool active)u16 data =0 ;int status; +dprintk (1 ,"\n" ); + do { /* Configure IQM */ status = Read16_0(state, IQM_AF_STDBY__A, &data);
@@ -1501,6 +1577,8 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)int status =0 ;u16 sioCcPwdMode =0 ; +dprintk (1 ,"\n" ); +/* Check arguments */ if (mode ==NULL )return -1 ;
@@ -1607,6 +1685,8 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)u16 data =0 ;int status; +dprintk (1 ,"\n" ); + do { status = Read16_0(state, SCU_COMM_EXEC__A, &data); if (status < 0)
@@ -1653,6 +1733,7 @@ static int SetOperationMode(struct drxk_state *state, {int status =0 ; +dprintk (1 ,"\n" );/* Stop and power down previous standard TODO investigate total power down instead of partial
@@ -1734,6 +1815,7 @@ static int Start(struct drxk_state *state, s32 offsetFreq, {int status =0 ; +dprintk (1 ,"\n" ); do { u16 IFreqkHz; s32 OffsetkHz = offsetFreq / 1000;
@@ -1783,6 +1865,8 @@ static int Start(struct drxk_state *state, s32 offsetFreq,static int ShutDown (struct drxk_state *state) { +dprintk (1 ,"\n" ); +MPEGTSStop (state);return 0 ; }
@@ -1792,6 +1876,8 @@ static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, {int status =0 ; +dprintk (1 ,"\n" ); +if (pLockStatus ==NULL )return -1 ;
@@ -1839,6 +1925,8 @@ static int MPEGTSDtoInit(struct drxk_state *state) {int status =-1 ; +dprintk (1 ,"\n" ); + do { /* Rate integration settings */ status = Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
@@ -1897,6 +1985,8 @@ static int MPEGTSDtoSetup(struct drxk_state *state,u32 maxBitRate =0 ;bool staticCLK = false; +dprintk (1 ,"\n" ); + do { /* Check insertion of the Reed-Solomon parity bytes */ status = Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode);
@@ -2021,6 +2111,8 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)int status;u16 fecOcRegIprInvert =0 ; +dprintk (1 ,"\n" ); +/* Data mask for the output data byte */ u16 InvertDataMask = FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
@@ -2056,6 +2148,8 @@ static int SetAgcRf(struct drxk_state *state,int status =0 ;struct SCfgAgc *pIfAgcSettings; +dprintk (1 ,"\n" ); +if (pAgcCfg ==NULL )return -1 ;
@@ -2202,6 +2296,8 @@ static int SetAgcIf(struct drxk_state *state,int status =0 ;struct SCfgAgc *pRfAgcSettings; +dprintk (1 ,"\n" ); + do { switch (pAgcCfg->ctrlMode) { case DRXK_AGC_CTRL_AUTO:
@@ -2327,6 +2423,8 @@ static int ReadIFAgc(struct drxk_state *state, u32 *pValue)u16 agcDacLvl;int status =Read16_0 (state,IQM_AF_AGC_IF__A , &agcDacLvl); +dprintk (1 ,"\n" ); + *pValue =0 ;if (status ==0 ) {
@@ -2346,6 +2444,8 @@ static int GetQAMSignalToNoise(struct drxk_state *state, {int status =0 ; +dprintk (1 ,"\n" ); + do { /* MER calculation */ u16 qamSlErrPower = 0; /* accum. error between
@@ -2406,6 +2506,7 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,u32 iMER =0 ;u16 transmissionParams =0 ; +dprintk (1 ,"\n" ); do { status = Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); if (status < 0)
@@ -2491,6 +2592,8 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,static int GetSignalToNoise (struct drxk_state *state,s32 *pSignalToNoise) { +dprintk (1 ,"\n" ); + *pSignalToNoise =0 ;switch (state->m_OperationMode) {case OM_DVBT :
@@ -2510,6 +2613,8 @@ static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)/* SNR Values for quasi errorfree reception rom Nordig 2.2 */ int status =0 ; +dprintk (1 ,"\n" ); +static s32 QE_SN [] = {51 ,/* QPSK 1/2 */ 69 ,/* QPSK 2/3 */
@@ -2573,6 +2678,8 @@ static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)int status =0 ; *pQuality =0 ; +dprintk (1 ,"\n" ); + do { u32 SignalToNoise = 0; u32 BERQuality = 100;
@@ -2615,6 +2722,8 @@ static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)static int GetQuality (struct drxk_state *state,s32 *pQuality) { +dprintk (1 ,"\n" ); +switch (state->m_OperationMode) {case OM_DVBT :return GetDVBTQuality (state, pQuality);
@@ -2645,6 +2754,8 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) {int status; +dprintk (1 ,"\n" ); +if (state->m_DrxkState ==DRXK_UNINITIALIZED )return -1 ;if (state->m_DrxkState ==DRXK_POWERED_DOWN )
@@ -2676,6 +2787,8 @@ static int SetPreSaw(struct drxk_state *state, {int status; +dprintk (1 ,"\n" ); +if ((pPreSawCfg ==NULL ) || (pPreSawCfg->reference >IQM_AF_PDREF__M ))return -1 ;
@@ -2693,6 +2806,8 @@ static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,int status;unsigned long end; +dprintk (1 ,"\n" ); +mutex_lock (&state->mutex); do { status = Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
@@ -2736,6 +2851,8 @@ static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)u16 data =0 ;int status; +dprintk (1 ,"\n" ); + do { /* Start measurement */ status = Write16_0(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
@@ -2770,6 +2887,8 @@ static int ADCSynchronization(struct drxk_state *state)u16 count =0 ;int status; +dprintk (1 ,"\n" ); + do { status = ADCSyncMeasurement(state, &count); if (status < 0)
@@ -2822,6 +2941,8 @@ static int SetFrequencyShifter(struct drxk_state *state,u32 frequencyShift;bool imageToSelect; +dprintk (1 ,"\n" ); +/* Program frequency shifter No need to account for mirroring on RF
@@ -2889,6 +3010,8 @@ static int InitAGC(struct drxk_state *state, bool isDTV)u16 clpCtrlMode =0 ;int status =0 ; +dprintk (1 ,"\n" ); + do { /* Common settings */ snsSumMax = 1023;
@@ -3067,6 +3190,7 @@ static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr) {int status; +dprintk (1 ,"\n" ); do { if (packetErr == NULL) { status = Write16_0(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
@@ -3092,6 +3216,7 @@ static int DVBTScCommand(struct drxk_state *state,u16 scExec =0 ;int status; +dprintk (1 ,"\n" ); status =Read16_0 (state,OFDM_SC_COMM_EXEC__A , &scExec);if (scExec !=1 ) {/* SC is not running */
@@ -3197,6 +3322,7 @@ static int PowerUpDVBT(struct drxk_state *state)enum DRXPowerMode powerMode =DRX_POWER_UP ;int status; +dprintk (1 ,"\n" ); do { status = CtrlPowerMode(state, &powerMode); if (status < 0)
@@ -3209,6 +3335,7 @@ static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled) {int status; +dprintk (1 ,"\n" );if (*enabled == true) status =Write16_0 (state,IQM_CF_BYPASSDET__A ,0 );else
@@ -3223,6 +3350,7 @@ static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)int status; +dprintk (1 ,"\n" );if (*enabled == true) {/* write mask to 1 */ status = Write16_0(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
@@ -3241,6 +3369,7 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,u16 data =0 ;int status; +dprintk (1 ,"\n" ); do { status = Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); if (status < 0)
@@ -3279,6 +3408,8 @@ static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, {int status; +dprintk (1 ,"\n" ); +switch (*speed) {case DRXK_DVBT_SQI_SPEED_FAST :case DRXK_DVBT_SQI_SPEED_MEDIUM :
@@ -3309,6 +3440,7 @@ static int DVBTActivatePresets(struct drxk_state *state)struct DRXKCfgDvbtEchoThres_t echoThres2k = {0 ,DRX_FFTMODE_2K };struct DRXKCfgDvbtEchoThres_t echoThres8k = {0 ,DRX_FFTMODE_8K }; +dprintk (1 ,"\n" ); do { bool setincenable = false; bool setfrenable = true;
@@ -3349,8 +3481,9 @@ static int SetDVBTStandard(struct drxk_state *state,u16 data =0 ;int status; +dprintk (1 ,"\n" ); +PowerUpDVBT (state); - do { /* added antenna switch */ SwitchAntennaToDVBT(state);
@@ -3552,6 +3685,7 @@ static int DVBTStart(struct drxk_state *state)int status;/* DRXKOfdmScCmd_t scCmd; */ +dprintk (1 ,"\n" );/* Start correct processes to get in lock */ /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ do {
@@ -3590,6 +3724,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,u16 param1;int status; +dprintk (1 ,"\n" );/* printk(KERN_DEBUG "drxk: %s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */ do { status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
@@ -3926,6 +4061,8 @@ static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)u16 ScRaRamLock =0 ;u16 ScCommExec =0 ; +dprintk (1 ,"\n" ); +/* driver 0.9.0 */ /* Check if SC is running */ status =Read16_0 (state,OFDM_SC_COMM_EXEC__A , &ScCommExec);
@@ -3956,6 +4093,7 @@ static int PowerUpQAM(struct drxk_state *state)enum DRXPowerMode powerMode =DRXK_POWER_DOWN_OFDM ;int status =0 ; +dprintk (1 ,"\n" ); do { status = CtrlPowerMode(state, &powerMode); if (status < 0)
@@ -3974,6 +4112,7 @@ static int PowerDownQAM(struct drxk_state *state)u16 cmdResult;int status =0 ; +dprintk (1 ,"\n" ); do { status = Read16_0(state, SCU_COMM_EXEC__A, &data); if (status < 0)
@@ -4023,8 +4162,9 @@ static int SetQAMMeasurement(struct drxk_state *state,u16 fecRsPeriod =0 ;/* Value for corresponding I2C register */ int status =0 ; +dprintk (1 ,"\n" ); + fecRsPrescale =1 ; - do { /* fecBitsDesired = symbolRate [kHz] *
@@ -4099,6 +4239,7 @@ static int SetQAM16(struct drxk_state *state) {int status =0 ; +dprintk (1 ,"\n" ); do { /* QAM Equalizer Setup */ /* Equalizer */
@@ -4290,6 +4431,7 @@ static int SetQAM32(struct drxk_state *state) {int status =0 ; +dprintk (1 ,"\n" ); do { /* QAM Equalizer Setup */ /* Equalizer */
@@ -4485,6 +4627,7 @@ static int SetQAM64(struct drxk_state *state) {int status =0 ; +dprintk (1 ,"\n" ); do { /* QAM Equalizer Setup */ /* Equalizer */
@@ -4679,6 +4822,7 @@ static int SetQAM128(struct drxk_state *state) {int status =0 ; +dprintk (1 ,"\n" ); do { /* QAM Equalizer Setup */ /* Equalizer */
@@ -4875,6 +5019,7 @@ static int SetQAM256(struct drxk_state *state) {int status =0 ; +dprintk (1 ,"\n" ); do { /* QAM Equalizer Setup */ /* Equalizer */
@@ -5072,6 +5217,7 @@ static int QAMResetQAM(struct drxk_state *state)int status;u16 cmdResult; +dprintk (1 ,"\n" ); do { /* Stop QAM comstate->m_exec */ status = Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
@@ -5104,6 +5250,7 @@ static int QAMSetSymbolrate(struct drxk_state *state)u32 lcSymbRate =0 ;int status; +dprintk (1 ,"\n" ); do { /* Select & calculate correct IQM rate */ adcFrequency = (state->m_sysClockFreq * 1000) / 3;
@@ -5169,6 +5316,7 @@ static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)int status;u16 Result[2 ] = {0 ,0 }; +dprintk (1 ,"\n" ); status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM |
@@ -5212,6 +5360,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,u16 setParamParameters[4 ] = {0 ,0 ,0 ,0 };u16 cmdResult; +dprintk (1 ,"\n" ); do { /* STEP 1: reset demodulator
@@ -5461,6 +5610,7 @@ static int SetQAMStandard(struct drxk_state *state,int status;#endif +dprintk (1 ,"\n" ); do { /* added antenna switch */ SwitchAntennaToQAM(state);
@@ -5622,6 +5772,7 @@ static int WriteGPIO(struct drxk_state *state)int status;u16 value =0 ; +dprintk (1 ,"\n" ); do { /* stop lock indicator process */ status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
@@ -5665,6 +5816,7 @@ static int SwitchAntennaToQAM(struct drxk_state *state) {int status =-1 ; +dprintk (1 ,"\n" );if (state->m_AntennaSwitchDVBTDVBC !=0 ) {if (state->m_GPIO != state->m_AntennaDVBC) { state->m_GPIO = state->m_AntennaDVBC;
@@ -5678,6 +5830,7 @@ static int SwitchAntennaToDVBT(struct drxk_state *state) {int status =-1 ; +dprintk (1 ,"\n" );if (state->m_AntennaSwitchDVBTDVBC !=0 ) {if (state->m_GPIO != state->m_AntennaDVBT) { state->m_GPIO = state->m_AntennaDVBT;
@@ -5697,6 +5850,8 @@ static int PowerDownDevice(struct drxk_state *state)/* ADC power down */ /* Power down device */ int status; + +dprintk (1 ,"\n" ); do { if (state->m_bPDownOpenBridge) { /* Open I2C bridge before power down of DRXK */
@@ -5732,6 +5887,8 @@ static int load_microcode(struct drxk_state *state, char *mc_name)const struct firmware *fw =NULL ;int err =0 ; +dprintk (1 ,"\n" ); + err =request_firmware (&fw, mc_name, state->i2c->dev.parent);if (err <0 ) { printk(KERN_ERR
@@ -5751,6 +5908,7 @@ static int init_drxk(struct drxk_state *state)enum DRXPowerMode powerMode =DRXK_POWER_DOWN_OFDM ;u16 driverVersion; +dprintk (1 ,"\n" );if ((state->m_DrxkState ==DRXK_UNINITIALIZED )) { do { status = PowerUpDevice(state);
@@ -5945,6 +6103,7 @@ static void drxk_c_release(struct dvb_frontend *fe) {struct drxk_state *state = fe->demodulator_priv; +dprintk (1 ,"\n" );kfree (state); }
@@ -5952,6 +6111,7 @@ static int drxk_c_init(struct dvb_frontend *fe) {struct drxk_state *state = fe->demodulator_priv; +dprintk (1 ,"\n" );if (mutex_trylock (&state->ctlock) ==0 )return -EBUSY ;SetOperationMode (state,OM_QAM_ITU_A );
@@ -5962,6 +6122,7 @@ static int drxk_c_sleep(struct dvb_frontend *fe) {struct drxk_state *state = fe->demodulator_priv; +dprintk (1 ,"\n" );ShutDown (state);mutex_unlock (&state->ctlock);return 0 ;
@@ -5971,7 +6132,7 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) {struct drxk_state *state = fe->demodulator_priv; -/* printk(KERN_DEBUG "drxk: drxk_gate %d\n", enable); */ +dprintk (1 ,"%s\n" , enable ?"enable" :"disable" );return ConfigureI2CBridge (state, enable ? true : false); }
@@ -5981,6 +6142,7 @@ static int drxk_set_parameters(struct dvb_frontend *fe,struct drxk_state *state = fe->demodulator_priv;u32 IF ; +dprintk (1 ,"\n" );if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl (fe,1 );if (fe->ops.tuner_ops.set_params)
@@ -5999,6 +6161,7 @@ static int drxk_set_parameters(struct dvb_frontend *fe,static int drxk_c_get_frontend (struct dvb_frontend *fe,struct dvb_frontend_parameters *p) { +dprintk (1 ,"\n" );return 0 ; }
@@ -6007,6 +6170,7 @@ static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)struct drxk_state *state = fe->demodulator_priv;u32 stat; +dprintk (1 ,"\n" ); *status =0 ;GetLockStatus (state, &stat,0 );if (stat ==MPEG_LOCK )
@@ -6020,6 +6184,8 @@ static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)static int drxk_read_ber (struct dvb_frontend *fe,u32 *ber) { +dprintk (1 ,"\n" ); + *ber =0 ;return 0 ; }
@@ -6030,6 +6196,7 @@ static int drxk_read_signal_strength(struct dvb_frontend *fe,struct drxk_state *state = fe->demodulator_priv;u32 val; +dprintk (1 ,"\n" );ReadIFAgc (state, &val); *strength = val &0xffff ;return 0 ;
@@ -6040,6 +6207,7 @@ static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)struct drxk_state *state = fe->demodulator_priv;s32 snr2; +dprintk (1 ,"\n" );GetSignalToNoise (state, &snr2); *snr = snr2 &0xffff ;return 0 ;
@@ -6050,6 +6218,7 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)struct drxk_state *state = fe->demodulator_priv;u16 err; +dprintk (1 ,"\n" );DVBTQAMGetAccPktErr (state, &err); *ucblocks = (u32 ) err;return 0 ;
@@ -6058,6 +6227,7 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)static int drxk_c_get_tune_settings (struct dvb_frontend *fe,struct dvb_frontend_tune_settings *sets) { +dprintk (1 ,"\n" ); sets->min_delay_ms =3000 ; sets->max_drift =0 ; sets->step_size =0 ;
@@ -6069,7 +6239,7 @@ static void drxk_t_release(struct dvb_frontend *fe)#if 0 struct drxk_state *state = fe->demodulator_priv; -printk (KERN_DEBUG "drxk: %s\n" , __func__); +dprintk (1 ,"\n" );kfree (state);#endif }
@@ -6077,6 +6247,8 @@ static void drxk_t_release(struct dvb_frontend *fe)static int drxk_t_init (struct dvb_frontend *fe) {struct drxk_state *state = fe->demodulator_priv; + +dprintk (1 ,"\n" );if (mutex_trylock (&state->ctlock) ==0 )return -EBUSY ;SetOperationMode (state,OM_DVBT );
@@ -6086,6 +6258,8 @@ static int drxk_t_init(struct dvb_frontend *fe)static int drxk_t_sleep (struct dvb_frontend *fe) {struct drxk_state *state = fe->demodulator_priv; + +dprintk (1 ,"\n" );mutex_unlock (&state->ctlock);return 0 ; }
@@ -6093,6 +6267,8 @@ static int drxk_t_sleep(struct dvb_frontend *fe)static int drxk_t_get_frontend (struct dvb_frontend *fe,struct dvb_frontend_parameters *p) { +dprintk (1 ,"\n" ); +return 0 ; }
@@ -6159,6 +6335,7 @@ struct dvb_frontend *drxk_attach(struct i2c_adapter *i2c, u8 adr, {struct drxk_state *state =NULL ; +dprintk (1 ,"\n" ); state =kzalloc (sizeof (struct drxk_state ),GFP_KERNEL );if (!state)return NULL ;
Signature · 1 line
1.7.1
PATCH 4/21 drxk: remove _0 from read/write routines
In reply to a message not in the archiveThe normal 16-bits read routine is called as "Read16_0". This is due to a flags that could optionally be passed. Yet, on no places at the code, a flag is passed there.
The same happens with 16-bits write and 32-read/write routines, and with WriteBlock.
Also, using flags, is an exception: there's no place currently using flags, except for an #ifdef at WriteBlock.
Rename the function as just "read16", and the one that requires flags, as "read16_flags".
This helps to see where the flags are used, and also avoid using CamelCase on Kernel.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +662 -651
@@ -372,7 +372,7 @@ static int i2c_read(struct i2c_adapter *adap,return 0 ; } -static int Read16 (struct drxk_state *state,u32 reg,u16 *data,u8 flags) +static int read16_flags (struct drxk_state *state,u32 reg,u16 *data,u8 flags) {u8 adr = state->demod_address, mm1[4 ], mm2[2 ], len;#ifdef I2C_LONG_ADR
@@ -398,12 +398,12 @@ static int Read16(struct drxk_state *state, u32 reg, u16 *data, u8 flags)return 0 ; } -static int Read16_0 (struct drxk_state *state,u32 reg,u16 *data) +static int read16 (struct drxk_state *state,u32 reg,u16 *data) { -return Read16 (state, reg, data,0 ); +return read16_flags (state, reg, data,0 ); } -static int Read32 (struct drxk_state *state,u32 reg,u32 *data,u8 flags) +static int read32_flags (struct drxk_state *state,u32 reg,u32 *data,u8 flags) {u8 adr = state->demod_address, mm1[4 ], mm2[4 ], len;#ifdef I2C_LONG_ADR
@@ -430,7 +430,12 @@ static int Read32(struct drxk_state *state, u32 reg, u32 *data, u8 flags)return 0 ; } -static int Write16 (struct drxk_state *state,u32 reg,u16 data,u8 flags) +static int read32 (struct drxk_state *state,u32 reg,u32 *data) +{ +return read32_flags (state, reg, data,0 ); +} + +static int write16_flags (struct drxk_state *state,u32 reg,u16 data,u8 flags) {u8 adr = state->demod_address, mm[6 ], len;#ifdef I2C_LONG_ADR
@@ -456,12 +461,12 @@ static int Write16(struct drxk_state *state, u32 reg, u16 data, u8 flags)return 0 ; } -static int Write16_0 (struct drxk_state *state,u32 reg,u16 data) +static int write16 (struct drxk_state *state,u32 reg,u16 data) { -return Write16 (state, reg, data,0 ); +return write16_flags (state, reg, data,0 ); } -static int Write32 (struct drxk_state *state,u32 reg,u32 data,u8 flags) +static int write32_flags (struct drxk_state *state,u32 reg,u32 data,u8 flags) {u8 adr = state->demod_address, mm[8 ], len;#ifdef I2C_LONG_ADR
@@ -488,10 +493,16 @@ static int Write32(struct drxk_state *state, u32 reg, u32 data, u8 flags)return 0 ; } -static int WriteBlock (struct drxk_state *state,u32 Address, -const int BlockSize,const u8 pBlock[],u8 Flags) +static int write32 (struct drxk_state *state,u32 reg,u32 data) +{ +return write32_flags (state, reg, data,0 ); +} + +static int write_block (struct drxk_state *state,u32 Address, +const int BlockSize,const u8 pBlock[]) {int status =0 , BlkSize = BlockSize; +u8 Flags =0 ;#ifdef I2C_LONG_ADR Flags |=0xC0 ;#endif
@@ -567,14 +578,14 @@ int PowerUpDevice(struct drxk_state *state)return -1 ; do { /* Make sure all clk domains are active */ - status = Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); + status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); if (status < 0) break; - status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); + status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); if (status < 0) break; /* Enable pll lock tests */ - status = Write16_0(state, SIO_CC_PLL_LOCK__A, 1); + status = write16(state, SIO_CC_PLL_LOCK__A, 1); if (status < 0) break; state->m_currentPowerMode = DRX_POWER_UP;
@@ -850,23 +861,23 @@ static int DRXX_Open(struct drxk_state *state)dprintk (1 ,"\n" );do {/* stop lock indicator process */ - status =Write16_0 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); + status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE );if (status <0 )break ;/* Check device id */ - status =Read16 (state,SIO_TOP_COMM_KEY__A , &key,0 ); + status =read16 (state,SIO_TOP_COMM_KEY__A , &key);if (status <0 )break ; - status =Write16_0 (state,SIO_TOP_COMM_KEY__A ,SIO_TOP_COMM_KEY_KEY ); + status =write16 (state,SIO_TOP_COMM_KEY__A ,SIO_TOP_COMM_KEY_KEY );if (status <0 )break ; - status =Read32 (state,SIO_TOP_JTAGID_LO__A , &jtag,0 ); + status =read32 (state,SIO_TOP_JTAGID_LO__A , &jtag);if (status <0 )break ; - status =Read16 (state,SIO_PDR_UIO_IN_HI__A , &bid,0 ); + status =read16 (state,SIO_PDR_UIO_IN_HI__A , &bid);if (status <0 )break ; - status =Write16_0 (state,SIO_TOP_COMM_KEY__A , key); + status =write16 (state,SIO_TOP_COMM_KEY__A , key);if (status <0 )break ; }while (0 );
@@ -883,17 +894,17 @@ static int GetDeviceCapabilities(struct drxk_state *state) do { /* driver 0.9.0 */ /* stop lock indicator process */ - status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); + status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); if (status < 0) break; - status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA); + status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); if (status < 0) break; - status = Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0); + status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); if (status < 0) break; - status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000); + status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); if (status < 0) break;
@@ -920,7 +931,7 @@ static int GetDeviceCapabilities(struct drxk_state *state)Determine device capabilities Based on pinning v14 */ - status =Read32 (state,SIO_TOP_JTAGID_LO__A , &sioTopJtagidLo,0 ); + status =read32 (state,SIO_TOP_JTAGID_LO__A , &sioTopJtagidLo);if (status <0 )break ;/* driver 0.9.0 */
@@ -1062,7 +1073,7 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)dprintk (1 ,"\n" );/* Write command */ - status =Write16_0 (state,SIO_HI_RA_RAM_CMD__A , cmd); + status =write16 (state,SIO_HI_RA_RAM_CMD__A , cmd);if (status <0 )return status;if (cmd ==SIO_HI_RA_RAM_CMD_RESET )
@@ -1081,14 +1092,14 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)do {msleep (1 ); retryCount +=1 ; - status =Read16 (state,SIO_HI_RA_RAM_CMD__A , - &waitCmd,0 ); + status =read16 (state,SIO_HI_RA_RAM_CMD__A , + &waitCmd); }while ((status <0 ) && (retryCount <DRXK_MAX_RETRIES ) && (waitCmd !=0 ));if (status ==0 ) - status =Read16 (state,SIO_HI_RA_RAM_RES__A , - pResult,0 ); + status =read16 (state,SIO_HI_RA_RAM_RES__A , + pResult); }return status; }
@@ -1101,22 +1112,22 @@ static int HI_CfgCommand(struct drxk_state *state)mutex_lock (&state->mutex); do { - status = Write16_0(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); + status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); if (status < 0) break; - status = Write16_0(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); + status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); if (status < 0) break; - status = Write16_0(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); + status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); if (status < 0) break; - status = Write16_0(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); + status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); if (status < 0) break; - status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); + status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); if (status < 0) break; - status = Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); + status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); if (status < 0) break; status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
@@ -1149,51 +1160,51 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)dprintk (1 ,"\n" ); do { /* stop lock indicator process */ - status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); + status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); if (status < 0) break; /* MPEG TS pad configuration */ - status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA); + status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); if (status < 0) break; if (mpegEnable == false) { /* Set MPEG TS pads to inputmode */ - status = Write16_0(state, SIO_PDR_MSTRT_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MERR_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MCLK_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MVAL_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); if (status < 0) break; - status = Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000); + status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); if (status < 0) break; } else {
@@ -1205,36 +1216,36 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) SIO_PDR_MCLK_CFG_DRIVE__B) | 0x0003); - status =Write16_0 (state,SIO_PDR_MSTRT_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MSTRT_CFG__A , sioPdrMdxCfg);if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MERR_CFG__A ,0x0000 );/* Disable */ + status =write16 (state,SIO_PDR_MERR_CFG__A ,0x0000 );/* Disable */ if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MVAL_CFG__A ,0x0000 );/* Disable */ + status =write16 (state,SIO_PDR_MVAL_CFG__A ,0x0000 );/* Disable */ if (status <0 )break ;if (state->m_enableParallel == true) {/* paralel -> enable MD1 to MD7 */ - status =Write16_0 (state,SIO_PDR_MD1_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MD1_CFG__A , sioPdrMdxCfg);if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD2_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MD2_CFG__A , sioPdrMdxCfg);if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD3_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MD3_CFG__A , sioPdrMdxCfg);if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD4_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MD4_CFG__A , sioPdrMdxCfg);if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD5_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MD5_CFG__A , sioPdrMdxCfg);if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD6_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MD6_CFG__A , sioPdrMdxCfg);if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD7_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MD7_CFG__A , sioPdrMdxCfg);if (status <0 )break ; }else {
@@ -1242,41 +1253,41 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);/* serial -> disable MD1 to MD7 */ - status =Write16_0 (state,SIO_PDR_MD1_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MD1_CFG__A ,0x0000 );if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD2_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MD2_CFG__A ,0x0000 );if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD3_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MD3_CFG__A ,0x0000 );if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD4_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MD4_CFG__A ,0x0000 );if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD5_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MD5_CFG__A ,0x0000 );if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD6_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MD6_CFG__A ,0x0000 );if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD7_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MD7_CFG__A ,0x0000 );if (status <0 )break ; } - status =Write16_0 (state,SIO_PDR_MCLK_CFG__A , sioPdrMclkCfg); + status =write16 (state,SIO_PDR_MCLK_CFG__A , sioPdrMclkCfg);if (status <0 )break ; - status =Write16_0 (state,SIO_PDR_MD0_CFG__A , sioPdrMdxCfg); + status =write16 (state,SIO_PDR_MD0_CFG__A , sioPdrMdxCfg);if (status <0 )break ; }/* Enable MB output over MPEG pads and ctl input */ - status =Write16_0 (state,SIO_PDR_MON_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MON_CFG__A ,0x0000 );if (status <0 )break ;/* Write nomagic word to enable pdr reg write */ - status =Write16_0 (state,SIO_TOP_COMM_KEY__A ,0x0000 ); + status =write16 (state,SIO_TOP_COMM_KEY__A ,0x0000 );if (status <0 )break ; }while (0 );
@@ -1301,23 +1312,23 @@ static int BLChainCmd(struct drxk_state *state,mutex_lock (&state->mutex); do { - status = Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); + status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); if (status < 0) break; - status = Write16_0(state, SIO_BL_CHAIN_ADDR__A, romOffset); + status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset); if (status < 0) break; - status = Write16_0(state, SIO_BL_CHAIN_LEN__A, nrOfElements); + status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements); if (status < 0) break; - status = Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); + status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); if (status < 0) break; end = jiffies + msecs_to_jiffies(timeOut); do { msleep(1); - status = Read16(state, SIO_BL_STATUS__A, &blStatus, 0); + status = read16(state, SIO_BL_STATUS__A, &blStatus); if (status < 0) break; } while ((blStatus == 0x1) &&
@@ -1374,7 +1385,7 @@ static int DownloadMicrocode(struct drxk_state *state, BlockCRC = (pSrc[0 ] <<8 ) | pSrc[1 ]; pSrc +=sizeof (u16); offset +=sizeof (u16); - status =WriteBlock (state, Address, BlockSize, pSrc,0 ); + status =write_block (state, Address, BlockSize, pSrc);if (status <0 )break ; pSrc += BlockSize;
@@ -1398,7 +1409,7 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) desiredStatus =SIO_OFDM_SH_OFDM_RING_STATUS_DOWN ; } - status = (Read16_0 (state,SIO_OFDM_SH_OFDM_RING_STATUS__A , &data)); + status = (read16 (state,SIO_OFDM_SH_OFDM_RING_STATUS__A , &data));if (data == desiredStatus) {/* tokenring already has correct status */
@@ -1406,11 +1417,11 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) }/* Disable/enable dvbt tokenring bridge */ status = -Write16_0 (state,SIO_OFDM_SH_OFDM_RING_ENABLE__A , desiredCtrl); +write16 (state,SIO_OFDM_SH_OFDM_RING_ENABLE__A , desiredCtrl); end = jiffies +msecs_to_jiffies (DRXK_OFDM_TR_SHUTDOWN_TIMEOUT );do { - status =Read16_0 (state,SIO_OFDM_SH_OFDM_RING_STATUS__A , &data); + status =read16 (state,SIO_OFDM_SH_OFDM_RING_STATUS__A , &data);if (status <0 )break ; }while ((data != desiredStatus) && ((time_is_after_jiffies (end))));
@@ -1431,20 +1442,20 @@ static int MPEGTSStop(struct drxk_state *state)do {/* Gracefull shutdown (byte boundaries) */ - status =Read16_0 (state,FEC_OC_SNC_MODE__A , &fecOcSncMode); + status =read16 (state,FEC_OC_SNC_MODE__A , &fecOcSncMode);if (status <0 )break ; fecOcSncMode |=FEC_OC_SNC_MODE_SHUTDOWN__M ; - status =Write16_0 (state,FEC_OC_SNC_MODE__A , fecOcSncMode); + status =write16 (state,FEC_OC_SNC_MODE__A , fecOcSncMode);if (status <0 )break ;/* Suppress MCLK during absence of data */ - status =Read16_0 (state,FEC_OC_IPR_MODE__A , &fecOcIprMode); + status =read16 (state,FEC_OC_IPR_MODE__A , &fecOcIprMode);if (status <0 )break ; fecOcIprMode |=FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M ; - status =Write16_0 (state,FEC_OC_IPR_MODE__A , fecOcIprMode); + status =write16 (state,FEC_OC_IPR_MODE__A , fecOcIprMode);if (status <0 )break ; }while (0 );
@@ -1482,13 +1493,13 @@ static int scu_command(struct drxk_state *state, buffer[cnt++] = (cmd &0xFF ); buffer[cnt++] = ((cmd >>8 ) &0xFF ); -WriteBlock (state,SCU_RAM_PARAM_0__A - - (parameterLen -1 ), cnt, buffer,0x00 ); +write_block (state,SCU_RAM_PARAM_0__A - + (parameterLen -1 ), cnt, buffer);/* Wait until SCU has processed command */ end = jiffies +msecs_to_jiffies (DRXK_MAX_WAITTIME );do {msleep (1 ); - status =Read16_0 (state,SCU_RAM_COMMAND__A , &curCmd); + status =read16 (state,SCU_RAM_COMMAND__A , &curCmd);if (status <0 )break ; } while (!(curCmd == DRX_SCU_READY)
@@ -1504,7 +1515,7 @@ static int scu_command(struct drxk_state *state,int ii;for (ii = resultLen -1 ; ii >=0 ; ii -=1 ) { - status =Read16_0 (state,SCU_RAM_PARAM_0__A - ii, &result[ii]); + status =read16 (state,SCU_RAM_PARAM_0__A - ii, &result[ii]);if (status <0 )break ; }
@@ -1547,7 +1558,7 @@ static int SetIqmAf(struct drxk_state *state, bool active) do { /* Configure IQM */ - status = Read16_0(state, IQM_AF_STDBY__A, &data); + status = read16(state, IQM_AF_STDBY__A, &data); if (status < 0) break; if (!active) {
@@ -1565,7 +1576,7 @@ static int SetIqmAf(struct drxk_state *state, bool active) & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ) ); } - status =Write16_0 (state,IQM_AF_STDBY__A , data); + status =write16 (state,IQM_AF_STDBY__A , data);if (status <0 )break ; }while (0 );
@@ -1658,10 +1669,10 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode) status =DVBTEnableOFDMTokenRing (state, false);if (status <0 )break ; - status =Write16_0 (state,SIO_CC_PWD_MODE__A , sioCcPwdMode); + status =write16 (state,SIO_CC_PWD_MODE__A , sioCcPwdMode);if (status <0 )break ; - status =Write16_0 (state,SIO_CC_UPDATE__A ,SIO_CC_UPDATE_KEY ); + status =write16 (state,SIO_CC_UPDATE__A ,SIO_CC_UPDATE_KEY );if (status <0 )break ;
@@ -1688,7 +1699,7 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)dprintk (1 ,"\n" ); do { - status = Read16_0(state, SCU_COMM_EXEC__A, &data); + status = read16(state, SCU_COMM_EXEC__A, &data); if (status < 0) break; if (data == SCU_COMM_EXEC_ACTIVE) {
@@ -1703,13 +1714,13 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) }/* Reset datapath for OFDM, processors first */ - status =Write16_0 (state,OFDM_SC_COMM_EXEC__A ,OFDM_SC_COMM_EXEC_STOP ); + status =write16 (state,OFDM_SC_COMM_EXEC__A ,OFDM_SC_COMM_EXEC_STOP );if (status <0 )break ; - status =Write16_0 (state,OFDM_LC_COMM_EXEC__A ,OFDM_LC_COMM_EXEC_STOP ); + status =write16 (state,OFDM_LC_COMM_EXEC__A ,OFDM_LC_COMM_EXEC_STOP );if (status <0 )break ; - status =Write16_0 (state,IQM_COMM_EXEC__A ,IQM_COMM_EXEC_B_STOP ); + status =write16 (state,IQM_COMM_EXEC__A ,IQM_COMM_EXEC_B_STOP );if (status <0 )break ;
@@ -1741,7 +1752,7 @@ static int SetOperationMode(struct drxk_state *state,*/ do { /* disable HW lock indicator */ - status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); + status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); if (status < 0) break;
@@ -1907,14 +1918,14 @@ static int MPEGTSStart(struct drxk_state *state)do {/* Allow OC to sync again */ - status =Read16_0 (state,FEC_OC_SNC_MODE__A , &fecOcSncMode); + status =read16 (state,FEC_OC_SNC_MODE__A , &fecOcSncMode);if (status <0 )break ; fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M ; - status =Write16_0 (state,FEC_OC_SNC_MODE__A , fecOcSncMode); + status =write16 (state,FEC_OC_SNC_MODE__A , fecOcSncMode);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_SNC_UNLOCK__A ,1 ); + status =write16 (state,FEC_OC_SNC_UNLOCK__A ,1 );if (status <0 )break ; }while (0 );
@@ -1929,39 +1940,39 @@ static int MPEGTSDtoInit(struct drxk_state *state)do {/* Rate integration settings */ - status =Write16_0 (state,FEC_OC_RCN_CTL_STEP_LO__A ,0x0000 ); + status =write16 (state,FEC_OC_RCN_CTL_STEP_LO__A ,0x0000 );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_RCN_CTL_STEP_HI__A ,0x000C ); + status =write16 (state,FEC_OC_RCN_CTL_STEP_HI__A ,0x000C );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_RCN_GAIN__A ,0x000A ); + status =write16 (state,FEC_OC_RCN_GAIN__A ,0x000A );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_AVR_PARM_A__A ,0x0008 ); + status =write16 (state,FEC_OC_AVR_PARM_A__A ,0x0008 );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_AVR_PARM_B__A ,0x0006 ); + status =write16 (state,FEC_OC_AVR_PARM_B__A ,0x0006 );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_TMD_HI_MARGIN__A ,0x0680 ); + status =write16 (state,FEC_OC_TMD_HI_MARGIN__A ,0x0680 );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_TMD_LO_MARGIN__A ,0x0080 ); + status =write16 (state,FEC_OC_TMD_LO_MARGIN__A ,0x0080 );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_TMD_COUNT__A ,0x03F4 ); + status =write16 (state,FEC_OC_TMD_COUNT__A ,0x03F4 );if (status <0 )break ;/* Additional configuration */ - status =Write16_0 (state,FEC_OC_OCR_INVERT__A ,0 ); + status =write16 (state,FEC_OC_OCR_INVERT__A ,0 );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_SNC_LWM__A ,2 ); + status =write16 (state,FEC_OC_SNC_LWM__A ,2 );if (status <0 )break ; - status =Write16_0 (state,FEC_OC_SNC_HWM__A ,12 ); + status =write16 (state,FEC_OC_SNC_HWM__A ,12 );if (status <0 )break ; }while (0 );
@@ -1989,10 +2000,10 @@ static int MPEGTSDtoSetup(struct drxk_state *state, do { /* Check insertion of the Reed-Solomon parity bytes */ - status = Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode); + status = read16(state, FEC_OC_MODE__A, &fecOcRegMode); if (status < 0) break; - status = Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); + status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); if (status < 0) break; fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
@@ -2073,33 +2084,33 @@ static int MPEGTSDtoSetup(struct drxk_state *state, }/* Write appropriate registers with requested configuration */ - status =Write16_0 (state,FEC_OC_DTO_BURST_LEN__A , fecOcDtoBurstLen); + status =write16 (state,FEC_OC_DTO_BURST_LEN__A , fecOcDtoBurstLen);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_DTO_PERIOD__A , fecOcDtoPeriod); + status =write16 (state,FEC_OC_DTO_PERIOD__A , fecOcDtoPeriod);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_DTO_MODE__A , fecOcDtoMode); + status =write16 (state,FEC_OC_DTO_MODE__A , fecOcDtoMode);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_FCT_MODE__A , fecOcFctMode); + status =write16 (state,FEC_OC_FCT_MODE__A , fecOcFctMode);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_MODE__A , fecOcRegMode); + status =write16 (state,FEC_OC_MODE__A , fecOcRegMode);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_IPR_MODE__A , fecOcRegIprMode); + status =write16 (state,FEC_OC_IPR_MODE__A , fecOcRegIprMode);if (status <0 )break ;/* Rate integration settings */ - status =Write32 (state,FEC_OC_RCN_CTL_RATE_LO__A , fecOcRcnCtlRate,0 ); + status =write32 (state,FEC_OC_RCN_CTL_RATE_LO__A , fecOcRcnCtlRate);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_TMD_INT_UPD_RATE__A , fecOcTmdIntUpdRate); + status =write16 (state,FEC_OC_TMD_INT_UPD_RATE__A , fecOcTmdIntUpdRate);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_TMD_MODE__A , fecOcTmdMode); + status =write16 (state,FEC_OC_TMD_MODE__A , fecOcTmdMode);if (status <0 )break ; }while (0 );
@@ -2136,7 +2147,7 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state) fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M ));if (state->m_invertCLK == true) fecOcRegIprInvert |=FEC_OC_IPR_INVERT_MCLK__M ; - status =Write16_0 (state,FEC_OC_IPR_INVERT__A , fecOcRegIprInvert); + status =write16 (state,FEC_OC_IPR_INVERT__A , fecOcRegIprInvert);return status; }
@@ -2160,15 +2171,15 @@ static int SetAgcRf(struct drxk_state *state,case DRXK_AGC_CTRL_AUTO :/* Enable RF AGC DAC */ - status =Read16_0 (state,IQM_AF_STDBY__A , &data); + status =read16 (state,IQM_AF_STDBY__A , &data);if (status <0 )break ; data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; - status =Write16_0 (state,IQM_AF_STDBY__A , data); + status =write16 (state,IQM_AF_STDBY__A , data);if (status <0 )break ; - status =Read16 (state,SCU_RAM_AGC_CONFIG__A , &data,0 ); + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data);if (status <0 )break ;
@@ -2180,12 +2191,12 @@ static int SetAgcRf(struct drxk_state *state, data |=SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; else data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - status =Write16_0 (state,SCU_RAM_AGC_CONFIG__A , data); + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data);if (status <0 )break ;/* Set speed (using complementary reduction value) */ - status =Read16 (state,SCU_RAM_AGC_KI_RED__A , &data,0 ); + status =read16 (state,SCU_RAM_AGC_KI_RED__A , &data);if (status <0 )break ;
@@ -2194,7 +2205,7 @@ static int SetAgcRf(struct drxk_state *state, SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M); - status =Write16_0 (state,SCU_RAM_AGC_KI_RED__A , data); + status =write16 (state,SCU_RAM_AGC_KI_RED__A , data);if (status <0 )break ;
@@ -2209,17 +2220,17 @@ static int SetAgcRf(struct drxk_state *state,/* Set TOP, only if IF-AGC is in AUTO mode */ if (pIfAgcSettings->ctrlMode ==DRXK_AGC_CTRL_AUTO ) - status =Write16_0 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pAgcCfg->top); + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pAgcCfg->top);if (status <0 )break ;/* Cut-Off current */ - status =Write16_0 (state,SCU_RAM_AGC_RF_IACCU_HI_CO__A , pAgcCfg->cutOffCurrent); + status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI_CO__A , pAgcCfg->cutOffCurrent);if (status <0 )break ;/* Max. output level */ - status =Write16_0 (state,SCU_RAM_AGC_RF_MAX__A , pAgcCfg->maxOutputLevel); + status =write16 (state,SCU_RAM_AGC_RF_MAX__A , pAgcCfg->maxOutputLevel);if (status <0 )break ;
@@ -2227,16 +2238,16 @@ static int SetAgcRf(struct drxk_state *state,case DRXK_AGC_CTRL_USER :/* Enable RF AGC DAC */ - status =Read16_0 (state,IQM_AF_STDBY__A , &data); + status =read16 (state,IQM_AF_STDBY__A , &data);if (status <0 )break ; data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; - status =Write16_0 (state,IQM_AF_STDBY__A , data); + status =write16 (state,IQM_AF_STDBY__A , data);if (status <0 )break ;/* Disable SCU RF AGC loop */ - status =Read16_0 (state,SCU_RAM_AGC_CONFIG__A , &data); + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data);if (status <0 )break ; data |=SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M ;
@@ -2244,37 +2255,37 @@ static int SetAgcRf(struct drxk_state *state, data |=SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; else data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - status =Write16_0 (state,SCU_RAM_AGC_CONFIG__A , data); + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data);if (status <0 )break ;/* SCU c.o.c. to 0, enabling full control range */ - status =Write16_0 (state,SCU_RAM_AGC_RF_IACCU_HI_CO__A ,0 ); + status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI_CO__A ,0 );if (status <0 )break ;/* Write value to output pin */ - status =Write16_0 (state,SCU_RAM_AGC_RF_IACCU_HI__A , pAgcCfg->outputLevel); + status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI__A , pAgcCfg->outputLevel);if (status <0 )break ;break ;case DRXK_AGC_CTRL_OFF :/* Disable RF AGC DAC */ - status =Read16_0 (state,IQM_AF_STDBY__A , &data); + status =read16 (state,IQM_AF_STDBY__A , &data);if (status <0 )break ; data |=IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; - status =Write16_0 (state,IQM_AF_STDBY__A , data); + status =write16 (state,IQM_AF_STDBY__A , data);if (status <0 )break ;/* Disable SCU RF AGC loop */ - status =Read16_0 (state,SCU_RAM_AGC_CONFIG__A , &data); + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data);if (status <0 )break ; data |=SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M ; - status =Write16_0 (state,SCU_RAM_AGC_CONFIG__A , data); + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data);if (status <0 )break ;break ;
@@ -2303,15 +2314,15 @@ static int SetAgcIf(struct drxk_state *state,case DRXK_AGC_CTRL_AUTO :/* Enable IF AGC DAC */ - status =Read16_0 (state,IQM_AF_STDBY__A , &data); + status =read16 (state,IQM_AF_STDBY__A , &data);if (status <0 )break ; data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; - status =Write16_0 (state,IQM_AF_STDBY__A , data); + status =write16 (state,IQM_AF_STDBY__A , data);if (status <0 )break ; - status =Read16_0 (state,SCU_RAM_AGC_CONFIG__A , &data); + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data);if (status <0 )break ;
@@ -2323,12 +2334,12 @@ static int SetAgcIf(struct drxk_state *state, data |=SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; else data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - status =Write16_0 (state,SCU_RAM_AGC_CONFIG__A , data); + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data);if (status <0 )break ;/* Set speed (using complementary reduction value) */ - status =Read16_0 (state,SCU_RAM_AGC_KI_RED__A , &data); + status =read16 (state,SCU_RAM_AGC_KI_RED__A , &data);if (status <0 )break ; data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M ;
@@ -2336,7 +2347,7 @@ static int SetAgcIf(struct drxk_state *state, SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M); - status =Write16_0 (state,SCU_RAM_AGC_KI_RED__A , data); + status =write16 (state,SCU_RAM_AGC_KI_RED__A , data);if (status <0 )break ;
@@ -2347,7 +2358,7 @@ static int SetAgcIf(struct drxk_state *state,if (pRfAgcSettings ==NULL )return -1 ;/* Restore TOP */ - status =Write16_0 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pRfAgcSettings->top); + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pRfAgcSettings->top);if (status <0 )break ;break ;
@@ -2355,15 +2366,15 @@ static int SetAgcIf(struct drxk_state *state,case DRXK_AGC_CTRL_USER :/* Enable IF AGC DAC */ - status =Read16_0 (state,IQM_AF_STDBY__A , &data); + status =read16 (state,IQM_AF_STDBY__A , &data);if (status <0 )break ; data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; - status =Write16_0 (state,IQM_AF_STDBY__A , data); + status =write16 (state,IQM_AF_STDBY__A , data);if (status <0 )break ; - status =Read16_0 (state,SCU_RAM_AGC_CONFIG__A , &data); + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data);if (status <0 )break ;
@@ -2375,12 +2386,12 @@ static int SetAgcIf(struct drxk_state *state, data |=SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; else data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - status =Write16_0 (state,SCU_RAM_AGC_CONFIG__A , data); + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data);if (status <0 )break ;/* Write value to output pin */ - status =Write16_0 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pAgcCfg->outputLevel); + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pAgcCfg->outputLevel);if (status <0 )break ;break ;
@@ -2388,20 +2399,20 @@ static int SetAgcIf(struct drxk_state *state,case DRXK_AGC_CTRL_OFF :/* Disable If AGC DAC */ - status =Read16_0 (state,IQM_AF_STDBY__A , &data); + status =read16 (state,IQM_AF_STDBY__A , &data);if (status <0 )break ; data |=IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; - status =Write16_0 (state,IQM_AF_STDBY__A , data); + status =write16 (state,IQM_AF_STDBY__A , data);if (status <0 )break ;/* Disable SCU IF AGC loop */ - status =Read16_0 (state,SCU_RAM_AGC_CONFIG__A , &data); + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data);if (status <0 )break ; data |=SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M ; - status =Write16_0 (state,SCU_RAM_AGC_CONFIG__A , data); + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data);if (status <0 )break ;break ;
@@ -2409,7 +2420,7 @@ static int SetAgcIf(struct drxk_state *state,/* always set the top to support configurations without if-loop */ - status =Write16_0 (state,SCU_RAM_AGC_INGAIN_TGT_MIN__A , pAgcCfg->top); + status =write16 (state,SCU_RAM_AGC_INGAIN_TGT_MIN__A , pAgcCfg->top);if (status <0 )break ;
@@ -2421,7 +2432,7 @@ static int SetAgcIf(struct drxk_state *state,static int ReadIFAgc (struct drxk_state *state,u32 *pValue) {u16 agcDacLvl; -int status =Read16_0 (state,IQM_AF_AGC_IF__A , &agcDacLvl); +int status =read16 (state,IQM_AF_AGC_IF__A , &agcDacLvl);dprintk (1 ,"\n" );
@@ -2455,7 +2466,7 @@ static int GetQAMSignalToNoise(struct drxk_state *state,u32 qamSlMer =0 ;/* QAM MER */ /* get the register value needed for MER */ - status =Read16_0 (state,QAM_SL_ERR_POWER__A , &qamSlErrPower); + status =read16 (state,QAM_SL_ERR_POWER__A , &qamSlErrPower);if (status <0 )break ;
@@ -2508,16 +2519,16 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,dprintk (1 ,"\n" ); do { - status = Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); + status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); if (status < 0) break; - status = Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); + status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); if (status < 0) break; - status = Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); + status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); if (status < 0) break; - status = Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data); + status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data); if (status < 0) break; /* Extend SQR_ERR_I operational range */
@@ -2526,7 +2537,7 @@ static int GetDVBTSignalToNoise(struct drxk_state *state, (EqRegTdSqrErrI < 0x00000FFFUL)) { EqRegTdSqrErrI +=0x00010000UL ; } - status =Read16_0 (state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A , ®Data); + status =read16 (state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A , ®Data);if (status <0 )break ;/* Extend SQR_ERR_Q operational range */
@@ -2535,7 +2546,7 @@ static int GetDVBTSignalToNoise(struct drxk_state *state, (EqRegTdSqrErrQ < 0x00000FFFUL)) EqRegTdSqrErrQ +=0x00010000UL ; - status =Read16_0 (state,OFDM_SC_RA_RAM_OP_PARAM__A , &transmissionParams); + status =read16 (state,OFDM_SC_RA_RAM_OP_PARAM__A , &transmissionParams);if (status <0 )break ;
@@ -2645,12 +2656,12 @@ static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) status =GetDVBTSignalToNoise (state, &SignalToNoise);if (status <0 )break ; - status =Read16_0 (state,OFDM_EQ_TOP_TD_TPS_CONST__A , &Constellation); + status =read16 (state,OFDM_EQ_TOP_TD_TPS_CONST__A , &Constellation);if (status <0 )break ; Constellation &=OFDM_EQ_TOP_TD_TPS_CONST__M ; - status =Read16_0 (state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A , &CodeRate); + status =read16 (state,OFDM_EQ_TOP_TD_TPS_CODE_HP__A , &CodeRate);if (status <0 )break ; CodeRate &=OFDM_EQ_TOP_TD_TPS_CODE_HP__M ;
@@ -2762,15 +2773,15 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)return -1 ; do { - status = Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); + status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); if (status < 0) break; if (bEnableBridge) { - status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); + status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); if (status < 0) break; } else { - status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); + status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); if (status < 0) break; }
@@ -2793,7 +2804,7 @@ static int SetPreSaw(struct drxk_state *state, || (pPreSawCfg->reference > IQM_AF_PDREF__M))return -1 ; - status =Write16_0 (state,IQM_AF_PDREF__A , pPreSawCfg->reference); + status =write16 (state,IQM_AF_PDREF__A , pPreSawCfg->reference);return status; }
@@ -2810,28 +2821,28 @@ static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,mutex_lock (&state->mutex); do { - status = Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); + status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); if (status < 0) break; - status = Write16_0(state, SIO_BL_TGT_HDR__A, blockbank); + status = write16(state, SIO_BL_TGT_HDR__A, blockbank); if (status < 0) break; - status = Write16_0(state, SIO_BL_TGT_ADDR__A, offset); + status = write16(state, SIO_BL_TGT_ADDR__A, offset); if (status < 0) break; - status = Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset); + status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); if (status < 0) break; - status = Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements); + status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); if (status < 0) break; - status = Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); + status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); if (status < 0) break; end = jiffies + msecs_to_jiffies(timeOut); do { - status = Read16_0(state, SIO_BL_STATUS__A, &blStatus); + status = read16(state, SIO_BL_STATUS__A, &blStatus); if (status < 0) break; } while ((blStatus == 0x1) && time_is_after_jiffies(end));
@@ -2855,25 +2866,25 @@ static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) do { /* Start measurement */ - status = Write16_0(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); + status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); if (status < 0) break; - status = Write16_0(state, IQM_AF_START_LOCK__A, 1); + status = write16(state, IQM_AF_START_LOCK__A, 1); if (status < 0) break; *count = 0; - status = Read16_0(state, IQM_AF_PHASE0__A, &data); + status = read16(state, IQM_AF_PHASE0__A, &data); if (status < 0) break; if (data == 127) *count = *count + 1; - status = Read16_0(state, IQM_AF_PHASE1__A, &data); + status = read16(state, IQM_AF_PHASE1__A, &data); if (status < 0) break; if (data == 127) *count = *count + 1; - status = Read16_0(state, IQM_AF_PHASE2__A, &data); + status = read16(state, IQM_AF_PHASE2__A, &data); if (status < 0) break; if (data == 127)
@@ -2898,7 +2909,7 @@ static int ADCSynchronization(struct drxk_state *state)/* Try sampling on a diffrent edge */ u16 clkNeg =0 ; - status =Read16_0 (state,IQM_AF_CLKNEG__A , &clkNeg); + status =read16 (state,IQM_AF_CLKNEG__A , &clkNeg);if (status <0 )break ; if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
@@ -2911,7 +2922,7 @@ static int ADCSynchronization(struct drxk_state *state) clkNeg |=IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS ; } - status =Write16_0 (state,IQM_AF_CLKNEG__A , clkNeg); + status =write16 (state,IQM_AF_CLKNEG__A , clkNeg);if (status <0 )break ; status =ADCSyncMeasurement (state, &count);
@@ -2984,8 +2995,8 @@ static int SetFrequencyShifter(struct drxk_state *state,/* Program frequency shifter with tuner offset compensation */ /* frequencyShift += tunerFreqOffset; TODO */ - status =Write32 (state,IQM_FS_RATE_OFS_LO__A , - state->m_IqmFsRateOfs,0 ); + status =write32 (state,IQM_FS_RATE_OFS_LO__A , + state->m_IqmFsRateOfs);return status; }
@@ -3049,127 +3060,127 @@ static int InitAGC(struct drxk_state *state, bool isDTV) fastClpCtrlDelay = state->m_dvbtIfAgcCfg.FastClipCtrlDelay; } - status =Write16_0 (state,SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A , fastClpCtrlDelay); + status =write16 (state,SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A , fastClpCtrlDelay);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_CTRL_MODE__A , clpCtrlMode); + status =write16 (state,SCU_RAM_AGC_CLP_CTRL_MODE__A , clpCtrlMode);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_INGAIN_TGT__A , ingainTgt); + status =write16 (state,SCU_RAM_AGC_INGAIN_TGT__A , ingainTgt);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_INGAIN_TGT_MIN__A , ingainTgtMin); + status =write16 (state,SCU_RAM_AGC_INGAIN_TGT_MIN__A , ingainTgtMin);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_INGAIN_TGT_MAX__A , ingainTgtMax); + status =write16 (state,SCU_RAM_AGC_INGAIN_TGT_MAX__A , ingainTgtMax);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A , ifIaccuHiTgtMin); + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A , ifIaccuHiTgtMin);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , ifIaccuHiTgtMax); + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , ifIaccuHiTgtMax);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_IF_IACCU_HI__A ,0 ); + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_IF_IACCU_LO__A ,0 ); + status =write16 (state,SCU_RAM_AGC_IF_IACCU_LO__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_RF_IACCU_HI__A ,0 ); + status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_RF_IACCU_LO__A ,0 ); + status =write16 (state,SCU_RAM_AGC_RF_IACCU_LO__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_SUM_MAX__A , clpSumMax); + status =write16 (state,SCU_RAM_AGC_CLP_SUM_MAX__A , clpSumMax);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_SNS_SUM_MAX__A , snsSumMax); + status =write16 (state,SCU_RAM_AGC_SNS_SUM_MAX__A , snsSumMax);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_KI_INNERGAIN_MIN__A , kiInnergainMin); + status =write16 (state,SCU_RAM_AGC_KI_INNERGAIN_MIN__A , kiInnergainMin);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT__A , ifIaccuHiTgt); + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT__A , ifIaccuHiTgt);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_CYCLEN__A , clpCyclen); + status =write16 (state,SCU_RAM_AGC_CLP_CYCLEN__A , clpCyclen);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_RF_SNS_DEV_MAX__A ,1023 ); + status =write16 (state,SCU_RAM_AGC_RF_SNS_DEV_MAX__A ,1023 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_RF_SNS_DEV_MIN__A , (u16) -1023 ); + status =write16 (state,SCU_RAM_AGC_RF_SNS_DEV_MIN__A , (u16) -1023 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A ,50 ); + status =write16 (state,SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_KI_MAXMINGAIN_TH__A ,20 ); + status =write16 (state,SCU_RAM_AGC_KI_MAXMINGAIN_TH__A ,20 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_SUM_MIN__A , clpSumMin); + status =write16 (state,SCU_RAM_AGC_CLP_SUM_MIN__A , clpSumMin);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_SNS_SUM_MIN__A , snsSumMin); + status =write16 (state,SCU_RAM_AGC_SNS_SUM_MIN__A , snsSumMin);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_DIR_TO__A , clpDirTo); + status =write16 (state,SCU_RAM_AGC_CLP_DIR_TO__A , clpDirTo);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_SNS_DIR_TO__A , snsDirTo); + status =write16 (state,SCU_RAM_AGC_SNS_DIR_TO__A , snsDirTo);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_KI_MINGAIN__A ,0x7fff ); + status =write16 (state,SCU_RAM_AGC_KI_MINGAIN__A ,0x7fff );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_KI_MAXGAIN__A ,0x0 ); + status =write16 (state,SCU_RAM_AGC_KI_MAXGAIN__A ,0x0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_KI_MIN__A ,0x0117 ); + status =write16 (state,SCU_RAM_AGC_KI_MIN__A ,0x0117 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_KI_MAX__A ,0x0657 ); + status =write16 (state,SCU_RAM_AGC_KI_MAX__A ,0x0657 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_SUM__A ,0 ); + status =write16 (state,SCU_RAM_AGC_CLP_SUM__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_CYCCNT__A ,0 ); + status =write16 (state,SCU_RAM_AGC_CLP_CYCCNT__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_DIR_WD__A ,0 ); + status =write16 (state,SCU_RAM_AGC_CLP_DIR_WD__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_CLP_DIR_STP__A ,1 ); + status =write16 (state,SCU_RAM_AGC_CLP_DIR_STP__A ,1 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_SNS_SUM__A ,0 ); + status =write16 (state,SCU_RAM_AGC_SNS_SUM__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_SNS_CYCCNT__A ,0 ); + status =write16 (state,SCU_RAM_AGC_SNS_CYCCNT__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_SNS_DIR_WD__A ,0 ); + status =write16 (state,SCU_RAM_AGC_SNS_DIR_WD__A ,0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_SNS_DIR_STP__A ,1 ); + status =write16 (state,SCU_RAM_AGC_SNS_DIR_STP__A ,1 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_SNS_CYCLEN__A ,500 ); + status =write16 (state,SCU_RAM_AGC_SNS_CYCLEN__A ,500 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_KI_CYCLEN__A ,500 ); + status =write16 (state,SCU_RAM_AGC_KI_CYCLEN__A ,500 );if (status <0 )break ;/* Initialize inner-loop KI gain factors */ - status =Read16_0 (state,SCU_RAM_AGC_KI__A , &data); + status =read16 (state,SCU_RAM_AGC_KI__A , &data);if (status <0 )break ;if (IsQAM (state)) {
@@ -3179,7 +3190,7 @@ static int InitAGC(struct drxk_state *state, bool isDTV) data &= ~SCU_RAM_AGC_KI_IF__M ; data |= (DRXK_KI_IAGC_QAM <<SCU_RAM_AGC_KI_IF__B ); } - status =Write16_0 (state,SCU_RAM_AGC_KI__A , data); + status =write16 (state,SCU_RAM_AGC_KI__A , data);if (status <0 )break ; }while (0 );
@@ -3193,11 +3204,11 @@ static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)dprintk (1 ,"\n" ); do { if (packetErr == NULL) { - status = Write16_0(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); + status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); if (status < 0) break; } else { - status = Read16_0(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); + status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); if (status < 0) break; }
@@ -3217,7 +3228,7 @@ static int DVBTScCommand(struct drxk_state *state,int status;dprintk (1 ,"\n" ); - status =Read16_0 (state,OFDM_SC_COMM_EXEC__A , &scExec); + status =read16 (state,OFDM_SC_COMM_EXEC__A , &scExec);if (scExec !=1 ) {/* SC is not running */ return -1 ;
@@ -3227,7 +3238,7 @@ static int DVBTScCommand(struct drxk_state *state, retryCnt =0 ;do {msleep (1 ); - status =Read16_0 (state,OFDM_SC_RA_RAM_CMD__A , &curCmd); + status =read16 (state,OFDM_SC_RA_RAM_CMD__A , &curCmd); retryCnt++; }while ((curCmd !=0 ) && (retryCnt <DRXK_MAX_RETRIES ));if (retryCnt >=DRXK_MAX_RETRIES )
@@ -3239,7 +3250,7 @@ static int DVBTScCommand(struct drxk_state *state,case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM :case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM : status = -Write16_0 (state,OFDM_SC_RA_RAM_CMD_ADDR__A , subcmd); +write16 (state,OFDM_SC_RA_RAM_CMD_ADDR__A , subcmd);break ;default :/* Do nothing */
@@ -3256,17 +3267,17 @@ static int DVBTScCommand(struct drxk_state *state,case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM :case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM : status = -Write16_0 (state,OFDM_SC_RA_RAM_PARAM1__A , param1); +write16 (state,OFDM_SC_RA_RAM_PARAM1__A , param1);/* All commands using 1 parameters */ case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING :case OFDM_SC_RA_RAM_CMD_USER_IO : status = -Write16_0 (state,OFDM_SC_RA_RAM_PARAM0__A , param0); +write16 (state,OFDM_SC_RA_RAM_PARAM0__A , param0);/* All commands using 0 parameters */ case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM :case OFDM_SC_RA_RAM_CMD_NULL :/* Write command */ - status =Write16_0 (state,OFDM_SC_RA_RAM_CMD__A , cmd); + status =write16 (state,OFDM_SC_RA_RAM_CMD__A , cmd);break ;default :/* Unknown command */
@@ -3277,14 +3288,14 @@ static int DVBTScCommand(struct drxk_state *state, retryCnt =0 ;do {msleep (1 ); - status =Read16_0 (state,OFDM_SC_RA_RAM_CMD__A , &curCmd); + status =read16 (state,OFDM_SC_RA_RAM_CMD__A , &curCmd); retryCnt++; }while ((curCmd !=0 ) && (retryCnt <DRXK_MAX_RETRIES ));if (retryCnt >=DRXK_MAX_RETRIES )return -1 ;/* Check for illegal cmd */ - status =Read16_0 (state,OFDM_SC_RA_RAM_CMD_ADDR__A , &errCode); + status =read16 (state,OFDM_SC_RA_RAM_CMD_ADDR__A , &errCode);if (errCode ==0xFFFF ) {/* illegal command */ return -EINVAL ;
@@ -3300,7 +3311,7 @@ static int DVBTScCommand(struct drxk_state *state,case OFDM_SC_RA_RAM_CMD_USER_IO :case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM : status = -Read16_0 (state,OFDM_SC_RA_RAM_PARAM0__A , &(param0)); +read16 (state,OFDM_SC_RA_RAM_PARAM0__A , &(param0));/* All commands yielding 0 results */ case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING :case OFDM_SC_RA_RAM_CMD_SET_TIMER :
@@ -3337,9 +3348,9 @@ static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)dprintk (1 ,"\n" );if (*enabled == true) - status =Write16_0 (state,IQM_CF_BYPASSDET__A ,0 ); + status =write16 (state,IQM_CF_BYPASSDET__A ,0 );else - status =Write16_0 (state,IQM_CF_BYPASSDET__A ,1 ); + status =write16 (state,IQM_CF_BYPASSDET__A ,1 );return status; }
@@ -3353,11 +3364,11 @@ static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)dprintk (1 ,"\n" );if (*enabled == true) {/* write mask to 1 */ - status =Write16_0 (state,OFDM_SC_RA_RAM_FR_THRES_8K__A , + status =write16 (state,OFDM_SC_RA_RAM_FR_THRES_8K__A ,DEFAULT_FR_THRES_8K ); }else {/* write mask to 0 */ - status =Write16_0 (state,OFDM_SC_RA_RAM_FR_THRES_8K__A ,0 ); + status =write16 (state,OFDM_SC_RA_RAM_FR_THRES_8K__A ,0 ); }return status;
@@ -3371,7 +3382,7 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,dprintk (1 ,"\n" ); do { - status = Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); + status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); if (status < 0) break;
@@ -3395,7 +3406,7 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,break ; } - status =Write16_0 (state,OFDM_SC_RA_RAM_ECHO_THRES__A , data); + status =write16 (state,OFDM_SC_RA_RAM_ECHO_THRES__A , data);if (status <0 )break ; }while (0 );
@@ -3418,7 +3429,7 @@ static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,default :return -EINVAL ; } - status =Write16_0 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A , + status =write16 (state,SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A , (u16) *speed);return status; }
@@ -3456,7 +3467,7 @@ static int DVBTActivatePresets(struct drxk_state *state) status =DVBTCtrlSetEchoThreshold (state, &echoThres8k);if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_AGC_INGAIN_TGT_MAX__A , state->m_dvbtIfAgcCfg.IngainTgtMax); + status =write16 (state,SCU_RAM_AGC_INGAIN_TGT_MAX__A , state->m_dvbtIfAgcCfg.IngainTgtMax);if (status <0 )break ; }while (0 );
@@ -3498,73 +3509,73 @@ static int SetDVBTStandard(struct drxk_state *state,break ;/* reset datapath for OFDM, processors first */ - status =Write16_0 (state,OFDM_SC_COMM_EXEC__A ,OFDM_SC_COMM_EXEC_STOP ); + status =write16 (state,OFDM_SC_COMM_EXEC__A ,OFDM_SC_COMM_EXEC_STOP );if (status <0 )break ; - status =Write16_0 (state,OFDM_LC_COMM_EXEC__A ,OFDM_LC_COMM_EXEC_STOP ); + status =write16 (state,OFDM_LC_COMM_EXEC__A ,OFDM_LC_COMM_EXEC_STOP );if (status <0 )break ; - status =Write16_0 (state,IQM_COMM_EXEC__A ,IQM_COMM_EXEC_B_STOP ); + status =write16 (state,IQM_COMM_EXEC__A ,IQM_COMM_EXEC_B_STOP );if (status <0 )break ;/* IQM setup */ /* synchronize on ofdstate->m_festart */ - status =Write16_0 (state,IQM_AF_UPD_SEL__A ,1 ); + status =write16 (state,IQM_AF_UPD_SEL__A ,1 );if (status <0 )break ;/* window size for clipping ADC detection */ - status =Write16_0 (state,IQM_AF_CLP_LEN__A ,0 ); + status =write16 (state,IQM_AF_CLP_LEN__A ,0 );if (status <0 )break ;/* window size for for sense pre-SAW detection */ - status =Write16_0 (state,IQM_AF_SNS_LEN__A ,0 ); + status =write16 (state,IQM_AF_SNS_LEN__A ,0 );if (status <0 )break ;/* sense threshold for sense pre-SAW detection */ - status =Write16_0 (state,IQM_AF_AMUX__A ,IQM_AF_AMUX_SIGNAL2ADC ); + status =write16 (state,IQM_AF_AMUX__A ,IQM_AF_AMUX_SIGNAL2ADC );if (status <0 )break ; status =SetIqmAf (state, true);if (status <0 )break ; - status =Write16_0 (state,IQM_AF_AGC_RF__A ,0 ); + status =write16 (state,IQM_AF_AGC_RF__A ,0 );if (status <0 )break ;/* Impulse noise cruncher setup */ - status =Write16_0 (state,IQM_AF_INC_LCT__A ,0 );/* crunch in IQM_CF */ + status =write16 (state,IQM_AF_INC_LCT__A ,0 );/* crunch in IQM_CF */ if (status <0 )break ; - status =Write16_0 (state,IQM_CF_DET_LCT__A ,0 );/* detect in IQM_CF */ + status =write16 (state,IQM_CF_DET_LCT__A ,0 );/* detect in IQM_CF */ if (status <0 )break ; - status =Write16_0 (state,IQM_CF_WND_LEN__A ,3 );/* peak detector window length */ + status =write16 (state,IQM_CF_WND_LEN__A ,3 );/* peak detector window length */ if (status <0 )break ; - status =Write16_0 (state,IQM_RC_STRETCH__A ,16 ); + status =write16 (state,IQM_RC_STRETCH__A ,16 );if (status <0 )break ; - status =Write16_0 (state,IQM_CF_OUT_ENA__A ,0x4 );/* enable output 2 */ + status =write16 (state,IQM_CF_OUT_ENA__A ,0x4 );/* enable output 2 */ if (status <0 )break ; - status =Write16_0 (state,IQM_CF_DS_ENA__A ,0x4 );/* decimate output 2 */ + status =write16 (state,IQM_CF_DS_ENA__A ,0x4 );/* decimate output 2 */ if (status <0 )break ; - status =Write16_0 (state,IQM_CF_SCALE__A ,1600 ); + status =write16 (state,IQM_CF_SCALE__A ,1600 );if (status <0 )break ; - status =Write16_0 (state,IQM_CF_SCALE_SH__A ,0 ); + status =write16 (state,IQM_CF_SCALE_SH__A ,0 );if (status <0 )break ;/* virtual clipping threshold for clipping ADC detection */ - status =Write16_0 (state,IQM_AF_CLP_TH__A ,448 ); + status =write16 (state,IQM_AF_CLP_TH__A ,448 );if (status <0 )break ; - status =Write16_0 (state,IQM_CF_DATATH__A ,495 );/* crunching threshold */ + status =write16 (state,IQM_CF_DATATH__A ,495 );/* crunching threshold */ if (status <0 )break ;
@@ -3572,17 +3583,17 @@ static int SetDVBTStandard(struct drxk_state *state,if (status <0 )break ; - status =Write16_0 (state,IQM_CF_PKDTH__A ,2 );/* peak detector threshold */ + status =write16 (state,IQM_CF_PKDTH__A ,2 );/* peak detector threshold */ if (status <0 )break ; - status =Write16_0 (state,IQM_CF_POW_MEAS_LEN__A ,2 ); + status =write16 (state,IQM_CF_POW_MEAS_LEN__A ,2 );if (status <0 )break ;/* enable power measurement interrupt */ - status =Write16_0 (state,IQM_CF_COMM_INT_MSK__A ,1 ); + status =write16 (state,IQM_CF_COMM_INT_MSK__A ,1 );if (status <0 )break ; - status =Write16_0 (state,IQM_COMM_EXEC__A ,IQM_COMM_EXEC_B_ACTIVE ); + status =write16 (state,IQM_COMM_EXEC__A ,IQM_COMM_EXEC_B_ACTIVE );if (status <0 )break ;
@@ -3595,7 +3606,7 @@ static int SetDVBTStandard(struct drxk_state *state,break ;/* Halt SCU to enable safe non-atomic accesses */ - status =Write16_0 (state,SCU_COMM_EXEC__A ,SCU_COMM_EXEC_HOLD ); + status =write16 (state,SCU_COMM_EXEC__A ,SCU_COMM_EXEC_HOLD );if (status <0 )break ;
@@ -3607,52 +3618,52 @@ static int SetDVBTStandard(struct drxk_state *state,break ;/* Set Noise Estimation notch width and enable DC fix */ - status =Read16_0 (state,OFDM_SC_RA_RAM_CONFIG__A , &data); + status =read16 (state,OFDM_SC_RA_RAM_CONFIG__A , &data);if (status <0 )break ; data |=OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M ; - status =Write16_0 (state,OFDM_SC_RA_RAM_CONFIG__A , data); + status =write16 (state,OFDM_SC_RA_RAM_CONFIG__A , data);if (status <0 )break ;/* Activate SCU to enable SCU commands */ - status =Write16_0 (state,SCU_COMM_EXEC__A ,SCU_COMM_EXEC_ACTIVE ); + status =write16 (state,SCU_COMM_EXEC__A ,SCU_COMM_EXEC_ACTIVE );if (status <0 )break ;if (!state->m_DRXK_A3_ROM_CODE) {/* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ - status =Write16_0 (state,SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A , state->m_dvbtIfAgcCfg.FastClipCtrlDelay); + status =write16 (state,SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A , state->m_dvbtIfAgcCfg.FastClipCtrlDelay);if (status <0 )break ; }/* OFDM_SC setup */ #ifdef COMPILE_FOR_NONRT - status =Write16_0 (state,OFDM_SC_RA_RAM_BE_OPT_DELAY__A ,1 ); + status =write16 (state,OFDM_SC_RA_RAM_BE_OPT_DELAY__A ,1 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A ,2 ); + status =write16 (state,OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A ,2 );if (status <0 )break ;#endif /* FEC setup */ - status =Write16_0 (state,FEC_DI_INPUT_CTL__A ,1 );/* OFDM input */ + status =write16 (state,FEC_DI_INPUT_CTL__A ,1 );/* OFDM input */ if (status <0 )break ;#ifdef COMPILE_FOR_NONRT - status =Write16_0 (state,FEC_RS_MEASUREMENT_PERIOD__A ,0x400 ); + status =write16 (state,FEC_RS_MEASUREMENT_PERIOD__A ,0x400 );if (status <0 )break ;#else - status =Write16_0 (state,FEC_RS_MEASUREMENT_PERIOD__A ,0x1000 ); + status =write16 (state,FEC_RS_MEASUREMENT_PERIOD__A ,0x1000 );if (status <0 )break ;#endif - status =Write16_0 (state,FEC_RS_MEASUREMENT_PRESCALE__A ,0x0001 ); + status =write16 (state,FEC_RS_MEASUREMENT_PRESCALE__A ,0x0001 );if (status <0 )break ;
@@ -3697,7 +3708,7 @@ static int DVBTStart(struct drxk_state *state) status =MPEGTSStart (state);if (status <0 )break ; - status =Write16_0 (state,FEC_COMM_EXEC__A ,FEC_COMM_EXEC_ACTIVE ); + status =write16 (state,FEC_COMM_EXEC__A ,FEC_COMM_EXEC_ACTIVE );if (status <0 )break ; }while (0 );
@@ -3732,21 +3743,21 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,break ;/* Halt SCU to enable safe non-atomic accesses */ - status =Write16_0 (state,SCU_COMM_EXEC__A ,SCU_COMM_EXEC_HOLD ); + status =write16 (state,SCU_COMM_EXEC__A ,SCU_COMM_EXEC_HOLD );if (status <0 )break ;/* Stop processors */ - status =Write16_0 (state,OFDM_SC_COMM_EXEC__A ,OFDM_SC_COMM_EXEC_STOP ); + status =write16 (state,OFDM_SC_COMM_EXEC__A ,OFDM_SC_COMM_EXEC_STOP );if (status <0 )break ; - status =Write16_0 (state,OFDM_LC_COMM_EXEC__A ,OFDM_LC_COMM_EXEC_STOP ); + status =write16 (state,OFDM_LC_COMM_EXEC__A ,OFDM_LC_COMM_EXEC_STOP );if (status <0 )break ;/* Mandatory fix, always stop CP, required to set spl offset back to hardware default (is set to 0 by ucode during pilot detection */ - status =Write16_0 (state,OFDM_CP_COMM_EXEC__A ,OFDM_CP_COMM_EXEC_STOP ); + status =write16 (state,OFDM_CP_COMM_EXEC__A ,OFDM_CP_COMM_EXEC_STOP );if (status <0 )break ;
@@ -3859,7 +3870,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,#else /* Set Priorty high */ transmissionParams |=OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI ; - status =Write16_0 (state,OFDM_EC_SB_PRIOR__A ,OFDM_EC_SB_PRIOR_HI ); + status =write16 (state,OFDM_EC_SB_PRIOR__A ,OFDM_EC_SB_PRIOR_HI );if (status <0 )break ;#endif
@@ -3903,58 +3914,58 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,case BANDWIDTH_AUTO :case BANDWIDTH_8_MHZ : bandwidth =DRXK_BANDWIDTH_8MHZ_IN_HZ ; - status =Write16_0 (state,OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A ,3052 ); + status =write16 (state,OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A ,3052 );if (status <0 )break ;/* cochannel protection for PAL 8 MHz */ - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A ,7 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A ,7 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A ,7 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A ,7 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A ,7 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A ,7 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A ,1 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A ,1 );if (status <0 )break ;break ;case BANDWIDTH_7_MHZ : bandwidth =DRXK_BANDWIDTH_7MHZ_IN_HZ ; - status =Write16_0 (state,OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A ,3491 ); + status =write16 (state,OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A ,3491 );if (status <0 )break ;/* cochannel protection for PAL 7 MHz */ - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A ,8 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A ,8 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A ,8 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A ,8 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A ,4 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A ,4 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A ,1 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A ,1 );if (status <0 )break ;break ;case BANDWIDTH_6_MHZ : bandwidth =DRXK_BANDWIDTH_6MHZ_IN_HZ ; - status =Write16_0 (state,OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A ,4073 ); + status =write16 (state,OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A ,4073 );if (status <0 )break ;/* cochannel protection for NTSC 6 MHz */ - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A ,19 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A ,19 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A ,19 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A ,19 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A ,14 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A ,14 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A ,1 ); + status =write16 (state,OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A ,1 );if (status <0 )break ;break ;
@@ -3986,7 +3997,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, iqmRcRateOfs &= ((((u32 )IQM_RC_RATE_OFS_HI__M ) <<IQM_RC_RATE_OFS_LO__W ) |IQM_RC_RATE_OFS_LO__M ); - status =Write32 (state,IQM_RC_RATE_OFS_LO__A , iqmRcRateOfs,0 ); + status =write32 (state,IQM_RC_RATE_OFS_LO__A , iqmRcRateOfs);if (status <0 )break ;
@@ -4004,15 +4015,15 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,/*== Start SC, write channel settings to SC ===============================*/ /* Activate SCU to enable SCU commands */ - status =Write16_0 (state,SCU_COMM_EXEC__A ,SCU_COMM_EXEC_ACTIVE ); + status =write16 (state,SCU_COMM_EXEC__A ,SCU_COMM_EXEC_ACTIVE );if (status <0 )break ;/* Enable SC after setting all other parameters */ - status =Write16_0 (state,OFDM_SC_COMM_STATE__A ,0 ); + status =write16 (state,OFDM_SC_COMM_STATE__A ,0 );if (status <0 )break ; - status =Write16_0 (state,OFDM_SC_COMM_EXEC__A ,1 ); + status =write16 (state,OFDM_SC_COMM_EXEC__A ,1 );if (status <0 )break ;
@@ -4065,14 +4076,14 @@ static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)/* driver 0.9.0 */ /* Check if SC is running */ - status =Read16_0 (state,OFDM_SC_COMM_EXEC__A , &ScCommExec); + status =read16 (state,OFDM_SC_COMM_EXEC__A , &ScCommExec);if (ScCommExec ==OFDM_SC_COMM_EXEC_STOP ) {/* SC not active; return DRX_NOT_LOCKED */ *pLockStatus =NOT_LOCKED ;return status; } - status =Read16_0 (state,OFDM_SC_RA_RAM_LOCK__A , &ScRaRamLock); + status =read16 (state,OFDM_SC_RA_RAM_LOCK__A , &ScRaRamLock);if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) *pLockStatus =MPEG_LOCK ;
@@ -4114,7 +4125,7 @@ static int PowerDownQAM(struct drxk_state *state)dprintk (1 ,"\n" ); do { - status = Read16_0(state, SCU_COMM_EXEC__A, &data); + status = read16(state, SCU_COMM_EXEC__A, &data); if (status < 0) break; if (data == SCU_COMM_EXEC_ACTIVE) {
@@ -4123,7 +4134,7 @@ static int PowerDownQAM(struct drxk_state *state)QAM and HW blocks */ /* stop all comstate->m_exec */ - status =Write16_0 (state,QAM_COMM_EXEC__A ,QAM_COMM_EXEC_STOP ); + status =write16 (state,QAM_COMM_EXEC__A ,QAM_COMM_EXEC_STOP );if (status <0 )break ; status =scu_command (state,SCU_RAM_COMMAND_STANDARD_QAM |SCU_RAM_COMMAND_CMD_DEMOD_STOP ,0 ,NULL ,1 , &cmdResult);
@@ -4217,13 +4228,13 @@ static int SetQAMMeasurement(struct drxk_state *state, (fecRsPrescale >> 1)) / fecRsPrescale;/* write corresponding registers */ - status =Write16_0 (state,FEC_RS_MEASUREMENT_PERIOD__A , fecRsPeriod); + status =write16 (state,FEC_RS_MEASUREMENT_PERIOD__A , fecRsPeriod);if (status <0 )break ; - status =Write16_0 (state,FEC_RS_MEASUREMENT_PRESCALE__A , fecRsPrescale); + status =write16 (state,FEC_RS_MEASUREMENT_PRESCALE__A , fecRsPrescale);if (status <0 )break ; - status =Write16_0 (state,FEC_OC_SNC_FAIL_PERIOD__A , fecRsPeriod); + status =write16 (state,FEC_OC_SNC_FAIL_PERIOD__A , fecRsPeriod);if (status <0 )break ;
@@ -4243,176 +4254,176 @@ static int SetQAM16(struct drxk_state *state)do {/* QAM Equalizer Setup */ /* Equalizer */ - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,13517 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,13517 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,13517 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,13517 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,13517 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,13517 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,13517 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,13517 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,13517 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,13517 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,13517 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,13517 );if (status <0 )break ;/* Decision Feedback Equalizer */ - status =Write16_0 (state,QAM_DQ_QUAL_FUN0__A ,2 ); + status =write16 (state,QAM_DQ_QUAL_FUN0__A ,2 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN1__A ,2 ); + status =write16 (state,QAM_DQ_QUAL_FUN1__A ,2 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN2__A ,2 ); + status =write16 (state,QAM_DQ_QUAL_FUN2__A ,2 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN3__A ,2 ); + status =write16 (state,QAM_DQ_QUAL_FUN3__A ,2 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN4__A ,2 ); + status =write16 (state,QAM_DQ_QUAL_FUN4__A ,2 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN5__A ,0 ); + status =write16 (state,QAM_DQ_QUAL_FUN5__A ,0 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_HWM__A ,5 ); + status =write16 (state,QAM_SY_SYNC_HWM__A ,5 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_AWM__A ,4 ); + status =write16 (state,QAM_SY_SYNC_AWM__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_LWM__A ,3 ); + status =write16 (state,QAM_SY_SYNC_LWM__A ,3 );if (status <0 )break ;/* QAM Slicer Settings */ - status =Write16_0 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM16 ); + status =write16 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM16 );if (status <0 )break ;/* QAM Loop Controller Coeficients */ - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,20 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,20 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,80 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,80 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,20 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,20 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,50 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,32 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,32 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,10 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,10 );if (status <0 )break ;/* QAM State Machine (FSM) Thresholds */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_RTH__A ,140 ); + status =write16 (state,SCU_RAM_QAM_FSM_RTH__A ,140 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FTH__A ,50 ); + status =write16 (state,SCU_RAM_QAM_FSM_FTH__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_CTH__A ,95 ); + status =write16 (state,SCU_RAM_QAM_FSM_CTH__A ,95 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_PTH__A ,120 ); + status =write16 (state,SCU_RAM_QAM_FSM_PTH__A ,120 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_QTH__A ,230 ); + status =write16 (state,SCU_RAM_QAM_FSM_QTH__A ,230 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_MTH__A ,105 ); + status =write16 (state,SCU_RAM_QAM_FSM_MTH__A ,105 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 ); + status =write16 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,4 ); + status =write16 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,4 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,24 ); + status =write16 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,24 );if (status <0 )break ;/* QAM FSM Tracking Parameters */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )16 ); + status =write16 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )220 ); + status =write16 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )220 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16 )25 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16 )25 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16 )6 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16 )6 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16) -24 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16) -24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16) -65 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16) -65 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -127 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -127 );if (status <0 )break ; }while (0 );
@@ -4435,180 +4446,180 @@ static int SetQAM32(struct drxk_state *state)do {/* QAM Equalizer Setup */ /* Equalizer */ - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,6707 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,6707 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,6707 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,6707 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,6707 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,6707 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,6707 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,6707 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,6707 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,6707 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,6707 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,6707 );if (status <0 )break ;/* Decision Feedback Equalizer */ - status =Write16_0 (state,QAM_DQ_QUAL_FUN0__A ,3 ); + status =write16 (state,QAM_DQ_QUAL_FUN0__A ,3 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN1__A ,3 ); + status =write16 (state,QAM_DQ_QUAL_FUN1__A ,3 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN2__A ,3 ); + status =write16 (state,QAM_DQ_QUAL_FUN2__A ,3 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN3__A ,3 ); + status =write16 (state,QAM_DQ_QUAL_FUN3__A ,3 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN4__A ,3 ); + status =write16 (state,QAM_DQ_QUAL_FUN4__A ,3 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN5__A ,0 ); + status =write16 (state,QAM_DQ_QUAL_FUN5__A ,0 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_HWM__A ,6 ); + status =write16 (state,QAM_SY_SYNC_HWM__A ,6 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_AWM__A ,5 ); + status =write16 (state,QAM_SY_SYNC_AWM__A ,5 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_LWM__A ,3 ); + status =write16 (state,QAM_SY_SYNC_LWM__A ,3 );if (status <0 )break ;/* QAM Slicer Settings */ - status =Write16_0 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM32 ); + status =write16 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM32 );if (status <0 )break ;/* QAM Loop Controller Coeficients */ - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,20 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,20 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,80 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,80 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,20 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,20 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,50 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,0 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,0 );if (status <0 )break ;/* QAM State Machine (FSM) Thresholds */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_RTH__A ,90 ); + status =write16 (state,SCU_RAM_QAM_FSM_RTH__A ,90 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FTH__A ,50 ); + status =write16 (state,SCU_RAM_QAM_FSM_FTH__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_CTH__A ,80 ); + status =write16 (state,SCU_RAM_QAM_FSM_CTH__A ,80 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_PTH__A ,100 ); + status =write16 (state,SCU_RAM_QAM_FSM_PTH__A ,100 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_QTH__A ,170 ); + status =write16 (state,SCU_RAM_QAM_FSM_QTH__A ,170 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_MTH__A ,100 ); + status =write16 (state,SCU_RAM_QAM_FSM_MTH__A ,100 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 ); + status =write16 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,4 ); + status =write16 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,4 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,10 ); + status =write16 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,10 );if (status <0 )break ;/* QAM FSM Tracking Parameters */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )12 ); + status =write16 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )140 ); + status =write16 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )140 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16) -8 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16) -8 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16) -16 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16) -16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16) -26 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16) -26 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16) -56 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16) -56 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -86 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -86 );if (status <0 )break ; }while (0 );
@@ -4631,179 +4642,179 @@ static int SetQAM64(struct drxk_state *state)do {/* QAM Equalizer Setup */ /* Equalizer */ - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,13336 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,13336 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,12618 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,12618 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,11988 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,11988 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,13809 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,13809 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,13809 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,13809 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,15609 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,15609 );if (status <0 )break ;/* Decision Feedback Equalizer */ - status =Write16_0 (state,QAM_DQ_QUAL_FUN0__A ,4 ); + status =write16 (state,QAM_DQ_QUAL_FUN0__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN1__A ,4 ); + status =write16 (state,QAM_DQ_QUAL_FUN1__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN2__A ,4 ); + status =write16 (state,QAM_DQ_QUAL_FUN2__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN3__A ,4 ); + status =write16 (state,QAM_DQ_QUAL_FUN3__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN4__A ,3 ); + status =write16 (state,QAM_DQ_QUAL_FUN4__A ,3 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN5__A ,0 ); + status =write16 (state,QAM_DQ_QUAL_FUN5__A ,0 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_HWM__A ,5 ); + status =write16 (state,QAM_SY_SYNC_HWM__A ,5 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_AWM__A ,4 ); + status =write16 (state,QAM_SY_SYNC_AWM__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_LWM__A ,3 ); + status =write16 (state,QAM_SY_SYNC_LWM__A ,3 );if (status <0 )break ;/* QAM Slicer Settings */ - status =Write16_0 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM64 ); + status =write16 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM64 );if (status <0 )break ;/* QAM Loop Controller Coeficients */ - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,30 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,30 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,100 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,100 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,30 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,30 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,50 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,25 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,25 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,48 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,48 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,10 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,10 );if (status <0 )break ;/* QAM State Machine (FSM) Thresholds */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_RTH__A ,100 ); + status =write16 (state,SCU_RAM_QAM_FSM_RTH__A ,100 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FTH__A ,60 ); + status =write16 (state,SCU_RAM_QAM_FSM_FTH__A ,60 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_CTH__A ,80 ); + status =write16 (state,SCU_RAM_QAM_FSM_CTH__A ,80 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_PTH__A ,110 ); + status =write16 (state,SCU_RAM_QAM_FSM_PTH__A ,110 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_QTH__A ,200 ); + status =write16 (state,SCU_RAM_QAM_FSM_QTH__A ,200 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_MTH__A ,95 ); + status =write16 (state,SCU_RAM_QAM_FSM_MTH__A ,95 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 ); + status =write16 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,4 ); + status =write16 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,4 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,15 ); + status =write16 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,15 );if (status <0 )break ;/* QAM FSM Tracking Parameters */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )12 ); + status =write16 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )141 ); + status =write16 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )141 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16 )7 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16 )7 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16 )0 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16 )0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16) -15 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16) -15 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16) -45 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16) -45 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -80 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -80 );if (status <0 )break ; }while (0 );
@@ -4826,181 +4837,181 @@ static int SetQAM128(struct drxk_state *state)do {/* QAM Equalizer Setup */ /* Equalizer */ - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,6564 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,6564 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,6598 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,6598 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,6394 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,6394 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,6409 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,6409 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,6656 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,6656 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,7238 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,7238 );if (status <0 )break ;/* Decision Feedback Equalizer */ - status =Write16_0 (state,QAM_DQ_QUAL_FUN0__A ,6 ); + status =write16 (state,QAM_DQ_QUAL_FUN0__A ,6 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN1__A ,6 ); + status =write16 (state,QAM_DQ_QUAL_FUN1__A ,6 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN2__A ,6 ); + status =write16 (state,QAM_DQ_QUAL_FUN2__A ,6 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN3__A ,6 ); + status =write16 (state,QAM_DQ_QUAL_FUN3__A ,6 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN4__A ,5 ); + status =write16 (state,QAM_DQ_QUAL_FUN4__A ,5 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN5__A ,0 ); + status =write16 (state,QAM_DQ_QUAL_FUN5__A ,0 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_HWM__A ,6 ); + status =write16 (state,QAM_SY_SYNC_HWM__A ,6 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_AWM__A ,5 ); + status =write16 (state,QAM_SY_SYNC_AWM__A ,5 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_LWM__A ,3 ); + status =write16 (state,QAM_SY_SYNC_LWM__A ,3 );if (status <0 )break ;/* QAM Slicer Settings */ - status =Write16_0 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM128 ); + status =write16 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM128 );if (status <0 )break ;/* QAM Loop Controller Coeficients */ - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,40 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,120 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,120 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,40 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,60 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,60 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,25 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,25 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,64 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,64 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,0 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,0 );if (status <0 )break ;/* QAM State Machine (FSM) Thresholds */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_RTH__A ,50 ); + status =write16 (state,SCU_RAM_QAM_FSM_RTH__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FTH__A ,60 ); + status =write16 (state,SCU_RAM_QAM_FSM_FTH__A ,60 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_CTH__A ,80 ); + status =write16 (state,SCU_RAM_QAM_FSM_CTH__A ,80 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_PTH__A ,100 ); + status =write16 (state,SCU_RAM_QAM_FSM_PTH__A ,100 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_QTH__A ,140 ); + status =write16 (state,SCU_RAM_QAM_FSM_QTH__A ,140 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_MTH__A ,100 ); + status =write16 (state,SCU_RAM_QAM_FSM_MTH__A ,100 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 ); + status =write16 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,5 ); + status =write16 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,12 ); + status =write16 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,12 );if (status <0 )break ;/* QAM FSM Tracking Parameters */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )8 ); + status =write16 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )8 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )65 ); + status =write16 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )65 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16 )5 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16 )5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16 )3 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16 )3 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16) -1 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16) -1 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16) -12 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16) -12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -23 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -23 );if (status <0 )break ; }while (0 );
@@ -5023,180 +5034,180 @@ static int SetQAM256(struct drxk_state *state)do {/* QAM Equalizer Setup */ /* Equalizer */ - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,11502 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD0__A ,11502 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,12084 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD1__A ,12084 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,12543 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD2__A ,12543 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,12931 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD3__A ,12931 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,13629 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD4__A ,13629 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,15385 ); + status =write16 (state,SCU_RAM_QAM_EQ_CMA_RAD5__A ,15385 );if (status <0 )break ;/* Decision Feedback Equalizer */ - status =Write16_0 (state,QAM_DQ_QUAL_FUN0__A ,8 ); + status =write16 (state,QAM_DQ_QUAL_FUN0__A ,8 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN1__A ,8 ); + status =write16 (state,QAM_DQ_QUAL_FUN1__A ,8 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN2__A ,8 ); + status =write16 (state,QAM_DQ_QUAL_FUN2__A ,8 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN3__A ,8 ); + status =write16 (state,QAM_DQ_QUAL_FUN3__A ,8 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN4__A ,6 ); + status =write16 (state,QAM_DQ_QUAL_FUN4__A ,6 );if (status <0 )break ; - status =Write16_0 (state,QAM_DQ_QUAL_FUN5__A ,0 ); + status =write16 (state,QAM_DQ_QUAL_FUN5__A ,0 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_HWM__A ,5 ); + status =write16 (state,QAM_SY_SYNC_HWM__A ,5 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_AWM__A ,4 ); + status =write16 (state,QAM_SY_SYNC_AWM__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_SYNC_LWM__A ,3 ); + status =write16 (state,QAM_SY_SYNC_LWM__A ,3 );if (status <0 )break ;/* QAM Slicer Settings */ - status =Write16_0 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM256 ); + status =write16 (state,SCU_RAM_QAM_SL_SIG_POWER__A ,DRXK_QAM_SL_SIG_POWER_QAM256 );if (status <0 )break ;/* QAM Loop Controller Coeficients */ - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_FINE__A ,15 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 ); + status =write16 (state,SCU_RAM_QAM_LC_CA_COARSE__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_MEDIUM__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 ); + status =write16 (state,SCU_RAM_QAM_LC_EP_COARSE__A ,24 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_FINE__A ,12 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_MEDIUM__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_EI_COARSE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,50 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_MEDIUM__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,250 ); + status =write16 (state,SCU_RAM_QAM_LC_CP_COARSE__A ,250 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,50 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_MEDIUM__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,125 ); + status =write16 (state,SCU_RAM_QAM_LC_CI_COARSE__A ,125 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_FINE__A ,16 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,25 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_MEDIUM__A ,25 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,48 ); + status =write16 (state,SCU_RAM_QAM_LC_CF_COARSE__A ,48 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_FINE__A ,5 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_MEDIUM__A ,10 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,10 ); + status =write16 (state,SCU_RAM_QAM_LC_CF1_COARSE__A ,10 );if (status <0 )break ;/* QAM State Machine (FSM) Thresholds */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_RTH__A ,50 ); + status =write16 (state,SCU_RAM_QAM_FSM_RTH__A ,50 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FTH__A ,60 ); + status =write16 (state,SCU_RAM_QAM_FSM_FTH__A ,60 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_CTH__A ,80 ); + status =write16 (state,SCU_RAM_QAM_FSM_CTH__A ,80 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_PTH__A ,100 ); + status =write16 (state,SCU_RAM_QAM_FSM_PTH__A ,100 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_QTH__A ,150 ); + status =write16 (state,SCU_RAM_QAM_FSM_QTH__A ,150 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_MTH__A ,110 ); + status =write16 (state,SCU_RAM_QAM_FSM_MTH__A ,110 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 ); + status =write16 (state,SCU_RAM_QAM_FSM_RATE_LIM__A ,40 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,4 ); + status =write16 (state,SCU_RAM_QAM_FSM_COUNT_LIM__A ,4 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,12 ); + status =write16 (state,SCU_RAM_QAM_FSM_FREQ_LIM__A ,12 );if (status <0 )break ;/* QAM FSM Tracking Parameters */ - status =Write16_0 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )8 ); + status =write16 (state,SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A , (u16 )8 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )74 ); + status =write16 (state,SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A , (u16 )74 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16 )18 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A , (u16 )18 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16 )13 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A , (u16 )13 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16 )7 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A , (u16 )7 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16 )0 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A , (u16 )0 );if (status <0 )break ; - status =Write16_0 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -8 ); + status =write16 (state,SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A , (u16) -8 );if (status <0 )break ; }while (0 );
@@ -5220,7 +5231,7 @@ static int QAMResetQAM(struct drxk_state *state)dprintk (1 ,"\n" ); do { /* Stop QAM comstate->m_exec */ - status = Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); + status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); if (status < 0) break;
@@ -5262,7 +5273,7 @@ static int QAMSetSymbolrate(struct drxk_state *state) ratesel =2 ; else if (state->param.u.qam.symbol_rate <= 4755000) ratesel =1 ; - status =Write16_0 (state,IQM_FD_RATESEL__A , ratesel); + status =write16 (state,IQM_FD_RATESEL__A , ratesel);if (status <0 )break ;
@@ -5277,7 +5288,7 @@ static int QAMSetSymbolrate(struct drxk_state *state) iqmRcRate = (adcFrequency / symbFreq) * (1 <<21 ) + (Frac28a ((adcFrequency % symbFreq), symbFreq) >>7 ) - (1 <<23 ); - status =Write32 (state,IQM_RC_RATE_OFS_LO__A , iqmRcRate,0 ); + status =write32 (state,IQM_RC_RATE_OFS_LO__A , iqmRcRate);if (status <0 )break ; state->m_iqmRcRate = iqmRcRate;
@@ -5294,7 +5305,7 @@ static int QAMSetSymbolrate(struct drxk_state *state) 16);if (lcSymbRate >511 ) lcSymbRate =511 ; - status =Write16_0 (state,QAM_LC_SYMBOL_FREQ__A , (u16 ) lcSymbRate); + status =write16 (state,QAM_LC_SYMBOL_FREQ__A , (u16 ) lcSymbRate);if (status <0 )break ; }while (0 );
@@ -5368,10 +5379,10 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,resets QAM block resets SCU variables */ - status =Write16_0 (state,FEC_DI_COMM_EXEC__A ,FEC_DI_COMM_EXEC_STOP ); + status =write16 (state,FEC_DI_COMM_EXEC__A ,FEC_DI_COMM_EXEC_STOP );if (status <0 )break ; - status =Write16_0 (state,FEC_RS_COMM_EXEC__A ,FEC_RS_COMM_EXEC_STOP ); + status =write16 (state,FEC_RS_COMM_EXEC__A ,FEC_RS_COMM_EXEC_STOP );if (status <0 )break ; status =QAMResetQAM (state);
@@ -5446,80 +5457,80 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,break ;/* Reset default values */ - status =Write16_0 (state,IQM_CF_SCALE_SH__A ,IQM_CF_SCALE_SH__PRE ); + status =write16 (state,IQM_CF_SCALE_SH__A ,IQM_CF_SCALE_SH__PRE );if (status <0 )break ; - status =Write16_0 (state,QAM_SY_TIMEOUT__A ,QAM_SY_TIMEOUT__PRE ); + status =write16 (state,QAM_SY_TIMEOUT__A ,QAM_SY_TIMEOUT__PRE );if (status <0 )break ;/* Reset default LC values */ - status =Write16_0 (state,QAM_LC_RATE_LIMIT__A ,3 ); + status =write16 (state,QAM_LC_RATE_LIMIT__A ,3 );if (status <0 )break ; - status =Write16_0 (state,QAM_LC_LPF_FACTORP__A ,4 ); + status =write16 (state,QAM_LC_LPF_FACTORP__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_LC_LPF_FACTORI__A ,4 ); + status =write16 (state,QAM_LC_LPF_FACTORI__A ,4 );if (status <0 )break ; - status =Write16_0 (state,QAM_LC_MODE__A ,7 ); + status =write16 (state,QAM_LC_MODE__A ,7 );if (status <0 )break ; - status =Write16_0 (state,QAM_LC_QUAL_TAB0__A ,1 ); + status =write16 (state,QAM_LC_QUAL_TAB0__A ,1 );if (status <0 )break ; - status =Write16_0 (state,QAM_LC_QUAL_TAB1__A ,1 ); + status =write16 (state,QAM_LC_QUAL_TAB1__A ,1 );if (status <0 )break ; - status =Write16_0 (state,QAM_LC_QUAL_TAB2__A ,1 ); + status =write16 (state,QAM_LC_QUAL_TAB2__A ,1 );if (status <0 )break ; - status =Write16_0 (state,QAM_LC_QUAL_TAB3__A ,1 ); + status =write16 (state,QAM_LC_QUAL_TAB3__A ,1 );if (status <0 )break ;
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Signature · 1 line
1.7.1
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PATCH 5/21 drxk: Move I2C address into a config structure
In reply to a message not in the archiveCurrently, the only parameter to be configured is the I2C address. However, Terratec H5 logs shows that it needs a different setting for some things, and it has its own firmware.
So, move the addr into a config structure, in order to allow adding the required configuration bits.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/ddbridge/ddbridge-core.c +5 -3
@@ -574,10 +574,12 @@ static int demod_attach_drxk(struct ddb_input *input) {struct i2c_adapter *i2c = &input->port->i2c->adap;struct dvb_frontend *fe; +struct drxk_config config; - fe = input->fe =dvb_attach (drxk_attach, - i2c,0x29 + (input->nr&1 ), - &input->fe2); +memset (&config,0 ,sizeof (config)); + config.adr =0x29 + (input->nr &1 ); + + fe = input->fe =dvb_attach (drxk_attach, &config, i2c, &input->fe2);if (!input->fe) {printk (KERN_ERR "No DRXK found!\n" );return -ENODEV ;
drivers/media/dvb/frontends/drxk.h +6 -2
@@ -4,7 +4,11 @@#include <linux/types.h> #include <linux/i2c.h> -extern struct dvb_frontend *drxk_attach (struct i2c_adapter *i2c, -u8 adr, +struct drxk_config { +u8 adr; +}; + +extern struct dvb_frontend *drxk_attach (const struct drxk_config *config, +struct i2c_adapter *i2c,struct dvb_frontend **fe_t);#endif
drivers/media/dvb/frontends/drxk_hard.c +3 -1
@@ -6341,10 +6341,12 @@ static struct dvb_frontend_ops drxk_t_ops = { .read_ucblocks = drxk_read_ucblocks, }; -struct dvb_frontend *drxk_attach (struct i2c_adapter *i2c,u8 adr, +struct dvb_frontend *drxk_attach (const struct drxk_config *config, +struct i2c_adapter *i2c,struct dvb_frontend **fe_t) {struct drxk_state *state =NULL ; +u8 adr = config->adr;dprintk (1 ,"\n" ); state =kzalloc (sizeof (struct drxk_state ),GFP_KERNEL );
drivers/media/dvb/ngene/ngene-cards.c +6 -3
@@ -213,9 +213,12 @@ static int port_has_drxk(struct i2c_adapter *i2c, int port)static int demod_attach_drxk (struct ngene_channel *chan,struct i2c_adapter *i2c) { - chan->fe =dvb_attach (drxk_attach, - i2c,0x29 + (chan->number^2 ), - &chan->fe2); +struct drxk_config config; + +memset (&config,0 ,sizeof (config)); + config.adr =0x29 + (chan->number ^2 ); + + chan->fe =dvb_attach (drxk_attach, &config, i2c, &chan->fe2);if (!chan->fe) {printk (KERN_ERR "No DRXK found!\n" );return -ENODEV ;
Signature · 1 line
1.7.1
PATCH 6/21 drxk: Convert an #ifdef logic as a new config parameter
In reply to a message not in the archiveInstead of using #ifdef I2C_LONG_ADR for some devices, convert it into a parameter. Terratec H5 logs from the original driver seems to need this mode.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk.h +1 -0
@@ -6,6 +6,7 @@struct drxk_config {u8 adr; +u32 single_master :1 ; }; extern struct dvb_frontend *drxk_attach(const struct drxk_config *config,
drivers/media/dvb/frontends/drxk_hard.c +19 -15
@@ -375,9 +375,10 @@ static int i2c_read(struct i2c_adapter *adap,static int read16_flags (struct drxk_state *state,u32 reg,u16 *data,u8 flags) {u8 adr = state->demod_address, mm1[4 ], mm2[2 ], len; -#ifdef I2C_LONG_ADR - flags |=0xC0 ; -#endif + +if (state->single_master) + flags |=0xC0 ; +if (DRXDAP_FASI_LONG_FORMAT (reg) || (flags !=0 )) { mm1[0 ] = (((reg <<1 ) &0xFF ) |0x01 ); mm1[1 ] = ((reg >>16 ) &0xFF );
@@ -406,9 +407,10 @@ static int read16(struct drxk_state *state, u32 reg, u16 *data)static int read32_flags (struct drxk_state *state,u32 reg,u32 *data,u8 flags) {u8 adr = state->demod_address, mm1[4 ], mm2[4 ], len; -#ifdef I2C_LONG_ADR - flags |=0xC0 ; -#endif + +if (state->single_master) + flags |=0xC0 ; +if (DRXDAP_FASI_LONG_FORMAT (reg) || (flags !=0 )) { mm1[0 ] = (((reg <<1 ) &0xFF ) |0x01 ); mm1[1 ] = ((reg >>16 ) &0xFF );
@@ -438,9 +440,9 @@ static int read32(struct drxk_state *state, u32 reg, u32 *data)static int write16_flags (struct drxk_state *state,u32 reg,u16 data,u8 flags) {u8 adr = state->demod_address, mm[6 ], len; -#ifdef I2C_LONG_ADR - flags |=0xC0 ; -#endif + +if (state->single_master) + flags |=0xC0 ;if (DRXDAP_FASI_LONG_FORMAT (reg) || (flags !=0 )) { mm[0 ] = (((reg <<1 ) &0xFF ) |0x01 ); mm[1 ] = ((reg >>16 ) &0xFF );
@@ -469,9 +471,9 @@ static int write16(struct drxk_state *state, u32 reg, u16 data)static int write32_flags (struct drxk_state *state,u32 reg,u32 data,u8 flags) {u8 adr = state->demod_address, mm[8 ], len; -#ifdef I2C_LONG_ADR - flags |=0xC0 ; -#endif + +if (state->single_master) + flags |=0xC0 ;if (DRXDAP_FASI_LONG_FORMAT (reg) || (flags !=0 )) { mm[0 ] = (((reg <<1 ) &0xFF ) |0x01 ); mm[1 ] = ((reg >>16 ) &0xFF );
@@ -503,9 +505,10 @@ static int write_block(struct drxk_state *state, u32 Address, {int status =0 , BlkSize = BlockSize;u8 Flags =0 ; -#ifdef I2C_LONG_ADR - Flags |=0xC0 ; -#endif + +if (state->single_master) + Flags |=0xC0 ; +while (BlkSize >0 ) {int Chunk = BlkSize > state->m_ChunkSize ? state->m_ChunkSize : BlkSize;
@@ -6355,6 +6358,7 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, state->i2c = i2c; state->demod_address = adr; + state->single_master = config->single_master;mutex_init (&state->mutex);mutex_init (&state->ctlock);
drivers/media/dvb/frontends/drxk_hard.h +5 -0
@@ -326,6 +326,11 @@ struct drxk_state {u16 m_AntennaSwitchDVBTDVBC;enum DRXPowerMode m_currentPowerMode; + +/* Configurable parameters at the driver */ + + u32 single_master : 1; /* Use single master i2c mode */ + };#define NEVER_LOCK 0
Signature · 1 line
1.7.1
PATCH 7/21 drxk: Avoid OOPSes if firmware is corrupted
In reply to a message not in the archiveDon't read paste the buffer, if the firmware is corrupted. Instead, print an error message.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +6 -0
@@ -1388,6 +1388,12 @@ static int DownloadMicrocode(struct drxk_state *state, BlockCRC = (pSrc[0 ] <<8 ) | pSrc[1 ]; pSrc +=sizeof (u16); offset +=sizeof (u16); + +if (offset + BlockSize > Length) { +printk (KERN_ERR "drxk: Firmware is corrupted.\n" ); +return -EINVAL ; + } + status =write_block (state, Address, BlockSize, pSrc);if (status <0 )break ;
Signature · 1 line
1.7.1
PATCH 8/21 drxk: Print an error if firmware is not loaded
In reply to a message not in the archiveIf something bad happens during firmware load, an error should be printed at dmesg.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +3 -1
@@ -1395,8 +1395,10 @@ static int DownloadMicrocode(struct drxk_state *state, } status =write_block (state, Address, BlockSize, pSrc); -if (status <0 ) +if (status <0 ) { +printk (KERN_ERR "drxk: Error %d while loading firmware\n" , status);break ; + } pSrc += BlockSize; offset += BlockSize; }
Signature · 1 line
1.7.1
PATCH 9/21 Add initial support for Terratec H5
In reply to a message not in the archiveNot working yet. There are some fixes at the DRX-K that are needed for it to work.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/video/em28xx/Kconfig +2 -0
@@ -39,6 +39,8 @@ config VIDEO_EM28XX_DVB select DVB_S921 if !DVB_FE_CUSTOMISE select DVB_DRXD if !DVB_FE_CUSTOMISE select DVB_CXD2820R if !DVB_FE_CUSTOMISE + select DVB_DRXK if !DVB_FE_CUSTOMISE + select DVB_TDA18271C2DD if !DVB_FE_CUSTOMISE select VIDEOBUF_DVB ---help--- This adds support for DVB cards based on the
drivers/media/video/em28xx/em28xx-cards.c +37 -0
@@ -300,6 +300,23 @@ static struct em28xx_reg_seq pctv_290e[] = { {-1, -1, -1, -1}, }; +#if 0 +static struct em28xx_reg_seq terratec_h5_gpio[] = { + {EM28XX_R08_GPIO ,0xff ,0xff ,10 }, + {EM2874_R80_GPIO ,0xf6 ,0xff ,100 }, + {EM2874_R80_GPIO ,0xf2 ,0xff ,50 }, + {EM2874_R80_GPIO ,0xf6 ,0xff ,50 }, + {-1 ,-1 ,-1 ,-1 }, +}; + +static struct em28xx_reg_seq terratec_h5_digital[] = { + {EM2874_R80_GPIO ,0xf6 ,0xff ,10 }, + {EM2874_R80_GPIO ,0xe6 ,0xff ,100 }, + {EM2874_R80_GPIO ,0xa6 ,0xff ,10 }, + {-1 ,-1 ,-1 ,-1 }, +}; +#endif +/* * Board definitions */
@@ -843,6 +860,19 @@ struct em28xx_board em28xx_boards[] = { .gpio = terratec_cinergy_USB_XS_FR_analog, } }, }, + [EM2884_BOARD_TERRATEC_H5] = { + .name = "Terratec Cinergy H5", + .has_dvb = 1, +#if 0 + .tuner_type = TUNER_PHILIPS_TDA8290, + .tuner_addr = 0x41, + .dvb_gpio = terratec_h5_digital, /* FIXME: probably wrong */ + .tuner_gpio = terratec_h5_gpio, +#endif + .i2c_speed = EM2874_I2C_SECONDARY_BUS_SELECT | + EM28XX_I2C_CLK_WAIT_ENABLE | + EM28XX_I2C_FREQ_400_KHZ, + }, [EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900] = { .name = "Hauppauge WinTV HVR 900", .tda9887_conf = TDA9887_PRESENT,
@@ -1855,6 +1885,8 @@ struct usb_device_id em28xx_id_table[] = { .driver_info = EM2882_BOARD_TERRATEC_HYBRID_XS }, { USB_DEVICE(0x0ccd, 0x0043), .driver_info = EM2870_BOARD_TERRATEC_XS }, + { USB_DEVICE(0x0ccd, 0x10a2), + .driver_info = EM2884_BOARD_TERRATEC_H5 }, { USB_DEVICE(0x0ccd, 0x0047), .driver_info = EM2880_BOARD_TERRATEC_PRODIGY_XS }, { USB_DEVICE(0x0ccd, 0x0084),
@@ -2840,6 +2872,11 @@ static int em28xx_init_dev(struct em28xx **devhandle, struct usb_device *udev,em28xx_info ("chip ID is em2882/em2883\n" ); dev->wait_after_write =0 ;break ; +case CHIP_ID_EM2884 : +em28xx_info ("chip ID is em2884\n" ); + dev->reg_gpio_num =EM2874_R80_GPIO ; + dev->wait_after_write =0 ; +break ;default :em28xx_info ("em28xx chip ID = %d\n" , dev->chip_id); }
drivers/media/video/em28xx/em28xx-core.c +6 -2
@@ -211,6 +211,7 @@ int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val) {return em28xx_write_regs (dev, reg, &val,1 ); } +EXPORT_SYMBOL_GPL (em28xx_write_reg);/* * em28xx_write_reg_bits()
@@ -618,7 +619,9 @@ int em28xx_capture_start(struct em28xx *dev, int start) {int rc; -if (dev->chip_id ==CHIP_ID_EM2874 || dev->chip_id ==CHIP_ID_EM28174 ) { +if (dev->chip_id ==CHIP_ID_EM2874 || + dev->chip_id ==CHIP_ID_EM2884 || + dev->chip_id ==CHIP_ID_EM28174 ) {/* The Transport Stream Enable Register moved in em2874 */ if (!start) { rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
@@ -887,6 +890,7 @@ int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio) }return rc; } +EXPORT_SYMBOL_GPL (em28xx_gpio_set);int em28xx_set_mode (struct em28xx *dev,enum em28xx_mode set_mode) {
@@ -1111,7 +1115,7 @@ int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)unsigned int chip_cfg2;unsigned int packet_size =564 ; -if (dev->chip_id ==CHIP_ID_EM2874 ) { +if (dev->chip_id ==CHIP_ID_EM2874 || dev->chip_id ==CHIP_ID_EM2884 ) {/* FIXME - for now assume 564 like it was before, but the em2874 code should be added to return the proper value... */ packet_size =564 ;
drivers/media/video/em28xx/em28xx-dvb.c +109 -1
140 lines not on this page · raw message
drivers/media/video/em28xx/em28xx-i2c.c +3 -1
@@ -330,7 +330,9 @@ static int em28xx_i2c_eeprom(struct em28xx *dev, unsigned char *eedata, int len)struct em28xx_eeprom *em_eeprom = (void *)eedata;int i, err, size = len, block; -if (dev->chip_id ==CHIP_ID_EM2874 || dev->chip_id ==CHIP_ID_EM28174 ) { +if (dev->chip_id ==CHIP_ID_EM2874 || + dev->chip_id ==CHIP_ID_EM28174 || + dev->chip_id ==CHIP_ID_EM2884 ) {/* Empia switched to a 16-bit addressable eeprom in newer devices. While we could certainly write a routine to read the eeprom, there is nothing of use in there that cannot be
drivers/media/video/em28xx/em28xx-reg.h +1 -0
@@ -201,6 +201,7 @@ enum em28xx_chip_id {CHIP_ID_EM2870 =35 ,CHIP_ID_EM2883 =36 ,CHIP_ID_EM2874 =65 , +CHIP_ID_EM2884 =68 , CHIP_ID_EM28174 = 113, };
drivers/media/video/em28xx/em28xx.h +2 -2
@@ -117,9 +117,9 @@#define EM2800_BOARD_VC211A 74#define EM2882_BOARD_DIKOM_DK300 75#define EM2870_BOARD_KWORLD_A340 76 -#define EM2874_BOARD_LEADERSHIP_ISDBT 77 +#define EM2874_BOARD_LEADERSHIP_ISDBT 77#define EM28174_BOARD_PCTV_290E 78 - +#define EM2884_BOARD_TERRATEC_H5 79/* Limits minimum and default number of buffers */ #define EM28XX_MIN_BUF 4
Signature · 1 line
1.7.1
PATCH 10/21 drxk: Add a parameter for the microcode name
In reply to a message not in the archiveThe microcode firmware provided on Terratec H5 seems to be different. Add a parameter to allow specifying a different firmware per-device.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk.h +1 -0
@@ -7,6 +7,7 @@struct drxk_config {u8 adr;u32 single_master :1 ; +const char *microcode_name; }; extern struct dvb_frontend *drxk_attach(const struct drxk_config *config,
drivers/media/dvb/frontends/drxk_hard.c +11 -18
@@ -343,10 +343,11 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)static int i2c_read (struct i2c_adapter *adap,u8 adr,u8 *msg,int len,u8 *answ,int alen) { -struct i2c_msg msgs[2 ] = { {.addr = adr, .flags =0 , +struct i2c_msg msgs[2 ] = { + {.addr = adr, .flags =0 , .buf = msg, .len = len}, - {.addr = adr, .flags =I2C_M_RD , - .buf = answ, .len = alen} + {.addr = adr, .flags =I2C_M_RD , + .buf = answ, .len = alen} };dprintk (3 ,":" );if (debug >2 ) {
@@ -5904,7 +5905,7 @@ static int PowerDownDevice(struct drxk_state *state)return 0 ; } -static int load_microcode (struct drxk_state *state,char *mc_name) +static int load_microcode (struct drxk_state *state,const char *mc_name) {const struct firmware *fw =NULL ;int err =0 ;
@@ -6010,20 +6011,11 @@ static int init_drxk(struct drxk_state *state)if (status <0 )break ; -#if 0 -if (state->m_DRXK_A3_PATCH_CODE) - status =DownloadMicrocode (state, DRXK_A3_microcode, DRXK_A3_microcode_length); -if (status <0 ) -break ; -#else -load_microcode (state,"drxk_a3.mc" ); -#endif -#if NOA1ROM -if (state->m_DRXK_A2_PATCH_CODE) - status =DownloadMicrocode (state, DRXK_A2_microcode, DRXK_A2_microcode_length); -if (status <0 ) -break ; -#endif +if (!state->microcode_name) +load_microcode (state,"drxk_a3.mc" ); +else +load_microcode (state, state->microcode_name); +/* disable token-ring bus through OFDM block for possible ucode upload */ status =write16 (state,SIO_OFDM_SH_OFDM_RING_ENABLE__A ,SIO_OFDM_SH_OFDM_RING_ENABLE_OFF );if (status <0 )
@@ -6367,6 +6359,7 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, state->i2c = i2c; state->demod_address = adr; state->single_master = config->single_master; + state->microcode_name = config->microcode_name;mutex_init (&state->mutex);mutex_init (&state->ctlock);
drivers/media/dvb/frontends/drxk_hard.h +1 -0
@@ -330,6 +330,7 @@ struct drxk_state {/* Configurable parameters at the driver */ u32 single_master : 1; /* Use single master i2c mode */ +const char *microcode_name; };
drivers/media/video/em28xx/em28xx-dvb.c +2 -2
@@ -301,10 +301,10 @@ static struct drxd_config em28xx_drxd = { .disable_i2c_gate_ctrl = 1, }; -#define TERRATEC_H5_DRXK_I2C_ADDR 0x29 -struct drxk_config terratec_h5_drxk = { .adr =0x29 , + .single_master =1 , + .microcode_name ="terratec_h5.fw" , };static int drxk_gate_ctrl (struct dvb_frontend *fe,int enable)
Signature · 1 line
1.7.1
PATCH 11/21 em28xx-i2c: Add a read after I2C write
In reply to a message not in the archiveAll I2C logs we got for em28xx does that. With Terratec H5, at 400MHz speed, it seems that this is required, to avoid having troubles at the I2C bus.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/video/em28xx/em28xx-i2c.c +10 -1
@@ -181,16 +181,25 @@ static int em2800_i2c_recv_bytes(struct em28xx *dev, unsigned char addr,/* * em28xx_i2c_send_bytes() -* untested for more than 4 bytes */ static int em28xx_i2c_send_bytes (void *data,unsigned char addr,char *buf,short len,int stop) {int wrcount =0 ;struct em28xx *dev = (struct em28xx *)data; +int write_timeout, ret; wrcount = dev->em28xx_write_regs_req (dev, stop ?2 :3 , addr, buf, len); +/* Seems to be required after a write */ +for (write_timeout =EM2800_I2C_WRITE_TIMEOUT ; write_timeout >0 ; + write_timeout -=5 ) { + ret = dev->em28xx_read_reg (dev,0x05 ); +if (!ret) +break ; +msleep (5 ); + } +return wrcount; }
Signature · 1 line
1.7.1
PATCH 12/21 drxk: Allow to disable I2C Bridge control switch
In reply to a message not in the archiveOn em28xx, tda18271C2 is accessible when the i2c port is not touched. Touching on it breaks the driver.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk.h +1 -0
@@ -7,6 +7,7 @@struct drxk_config {u8 adr;u32 single_master :1 ; +u32 no_i2c_bridge :1 ;const char *microcode_name; };
drivers/media/dvb/frontends/drxk_hard.c +3 -0
@@ -2784,6 +2784,8 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)if (state->m_DrxkState ==DRXK_POWERED_DOWN )return -1 ; +if (state->no_i2c_bridge) +return 0 ; do { status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); if (status < 0)
@@ -6360,6 +6362,7 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, state->demod_address = adr; state->single_master = config->single_master; state->microcode_name = config->microcode_name; + state->no_i2c_bridge = config->no_i2c_bridge;mutex_init (&state->mutex);mutex_init (&state->ctlock);
drivers/media/dvb/frontends/drxk_hard.h +1 -0
@@ -330,6 +330,7 @@ struct drxk_state {/* Configurable parameters at the driver */ u32 single_master : 1; /* Use single master i2c mode */ + u32 no_i2c_bridge : 1; /* Tuner is not on port 1, don't use I2C bridge */const char *microcode_name; };
drivers/media/video/em28xx/em28xx-dvb.c +1 -0
@@ -304,6 +304,7 @@ static struct drxd_config em28xx_drxd = {struct drxk_config terratec_h5_drxk = { .adr =0x29 , .single_master =1 , + .no_i2c_bridge =1 , .microcode_name ="terratec_h5.fw" , };
Signature · 1 line
1.7.1
PATCH 13/21 drxk: Proper handle/propagate the error codes
In reply to a message not in the archiveThis driver is very big and complex. An error happening in the middle of any initialization may cause the frontend to not work. So, it needs to properly propagate error codes internally and to userspace.
Also, printing the error codes at the places it happened helps to discover were's a bug at the code.
Before this change, a do { } while (0) loop and lots of breaks inside were used to propagate errors. While this works, if there are loops inside other loops, it could be easy to forget to add another break, causing the error to not abort the function.
Also, as not all functions were reporting errors, it is hard to discover why something failed.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +3650 -3669
@@ -318,11 +318,13 @@ static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)struct i2c_msg msgs[1 ] = { {.addr = adr, .flags =I2C_M_RD , .buf = val, .len =1 } }; -return (i2c_transfer (adapter, msgs,1 ) ==1 ) ?0 :-1 ; + +return i2c_transfer (adapter, msgs,1 ); }static int i2c_write (struct i2c_adapter *adap,u8 adr,u8 *data,int len) { +int status;struct i2c_msg msg = { .addr = adr, .flags =0 , .buf = data, .len = len };
@@ -333,16 +335,20 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)printk (KERN_CONT " %02x" , data[i]);printk (KERN_CONT "\n" ); } -if (i2c_transfer (adap, &msg,1 ) !=1 ) { + status =i2c_transfer (adap, &msg,1 ); +if (status >=0 && status !=1 ) + status = -EIO ; + +if (status <0 )printk (KERN_ERR "drxk: i2c write error at addr 0x%02x\n" , adr); -return -1 ; - } -return 0 ; + +return status; }static int i2c_read (struct i2c_adapter *adap,u8 adr,u8 *msg,int len,u8 *answ,int alen) { +int status;struct i2c_msg msgs[2 ] = { {.addr = adr, .flags =0 , .buf = msg, .len = len},
@@ -356,12 +362,15 @@ static int i2c_read(struct i2c_adapter *adap,printk (KERN_CONT " %02x" , msg[i]);printk (KERN_CONT "\n" ); } -if (i2c_transfer (adap, msgs,2 ) !=2 ) { + status =i2c_transfer (adap, msgs,2 ); +if (status !=2 ) {if (debug >2 )printk (KERN_CONT ": ERROR!\n" ); +if (status >=0 ) + status = -EIO ;printk (KERN_ERR "drxk: i2c read error at addr 0x%02x\n" , adr); -return -1 ; +return status; }if (debug >2 ) {int i;
@@ -375,6 +384,7 @@ static int i2c_read(struct i2c_adapter *adap,static int read16_flags (struct drxk_state *state,u32 reg,u16 *data,u8 flags) { +int status;u8 adr = state->demod_address, mm1[4 ], mm2[2 ], len;if (state->single_master)
@@ -392,8 +402,9 @@ static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) len =2 ; }dprintk (2 ,"(0x%08x, 0x%02x)\n" , reg, flags); -if (i2c_read (state->i2c, adr, mm1, len, mm2,2 ) <0 ) -return -1 ; + status =i2c_read (state->i2c, adr, mm1, len, mm2,2 ); +if (status <0 ) +return status;if (data) *data = mm2[0 ] | (mm2[1 ] <<8 );
@@ -407,6 +418,7 @@ static int read16(struct drxk_state *state, u32 reg, u16 *data)static int read32_flags (struct drxk_state *state,u32 reg,u32 *data,u8 flags) { +int status;u8 adr = state->demod_address, mm1[4 ], mm2[4 ], len;if (state->single_master)
@@ -424,8 +436,9 @@ static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) len =2 ; }dprintk (2 ,"(0x%08x, 0x%02x)\n" , reg, flags); -if (i2c_read (state->i2c, adr, mm1, len, mm2,4 ) <0 ) -return -1 ; + status =i2c_read (state->i2c, adr, mm1, len, mm2,4 ); +if (status <0 ) +return status;if (data) *data = mm2[0 ] | (mm2[1 ] <<8 ) | (mm2[2 ] <<16 ) | (mm2[3 ] <<24 );
@@ -459,9 +472,7 @@ static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) mm[len +1 ] = (data >>8 ) &0xff ;dprintk (2 ,"(0x%08x, 0x%04x, 0x%02x)\n" , reg, data, flags); -if (i2c_write (state->i2c, adr, mm, len +2 ) <0 ) -return -1 ; -return 0 ; +return i2c_write (state->i2c, adr, mm, len +2 ); }static int write16 (struct drxk_state *state,u32 reg,u16 data)
@@ -491,9 +502,8 @@ static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) mm[len +2 ] = (data >>16 ) &0xff ; mm[len +3 ] = (data >>24 ) &0xff ;dprintk (2 ,"(0x%08x, 0x%08x, 0x%02x)\n" , reg, data, flags); -if (i2c_write (state->i2c, adr, mm, len +4 ) <0 ) -return -1 ; -return 0 ; + +return i2c_write (state->i2c, adr, mm, len +4 ); }static int write32 (struct drxk_state *state,u32 reg,u32 data)
@@ -567,33 +577,41 @@ int PowerUpDevice(struct drxk_state *state)dprintk (1 ,"\n" ); status =i2c_read1 (state->i2c, state->demod_address, &data); -if (status <0 ) +if (status <0 ) {do { data =0 ; -if (i2c_write (state->i2c, - state->demod_address, &data,1 ) <0 ) -printk (KERN_ERR "drxk: powerup failed\n" ); + status =i2c_write (state->i2c, state->demod_address, + &data,1 );msleep (10 ); retryCount++; - }while (i2c_read1 (state->i2c, - state->demod_address, &data) <0 && +if (status <0 ) +continue ; + status =i2c_read1 (state->i2c, state->demod_address, + &data); + }while (status <0 && (retryCount <DRXK_MAX_RETRIES_POWERUP )); -if (retryCount >=DRXK_MAX_RETRIES_POWERUP ) -return -1 ; -do { -/* Make sure all clk domains are active */ - status =write16 (state,SIO_CC_PWD_MODE__A ,SIO_CC_PWD_MODE_LEVEL_NONE ); -if (status <0 ) -break ; - status =write16 (state,SIO_CC_UPDATE__A ,SIO_CC_UPDATE_KEY ); -if (status <0 ) -break ; -/* Enable pll lock tests */ - status =write16 (state,SIO_CC_PLL_LOCK__A ,1 ); -if (status <0 ) -break ; - state->m_currentPowerMode =DRX_POWER_UP ; - }while (0 ); +if (status <0 && retryCount >=DRXK_MAX_RETRIES_POWERUP ) + goto error; + } + +/* Make sure all clk domains are active */ + status =write16 (state,SIO_CC_PWD_MODE__A ,SIO_CC_PWD_MODE_LEVEL_NONE ); +if (status <0 ) + goto error; + status =write16 (state,SIO_CC_UPDATE__A ,SIO_CC_UPDATE_KEY ); +if (status <0 ) + goto error; +/* Enable pll lock tests */ + status =write16 (state,SIO_CC_PLL_LOCK__A ,1 ); +if (status <0 ) + goto error; + + state->m_currentPowerMode =DRX_POWER_UP ; + +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); +return status; }
@@ -863,28 +881,27 @@ static int DRXX_Open(struct drxk_state *state)u16 key =0 ;dprintk (1 ,"\n" ); -do { -/* stop lock indicator process */ - status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); -if (status <0 ) -break ; -/* Check device id */ - status =read16 (state,SIO_TOP_COMM_KEY__A , &key); -if (status <0 ) -break ; - status =write16 (state,SIO_TOP_COMM_KEY__A ,SIO_TOP_COMM_KEY_KEY ); -if (status <0 ) -break ; - status =read32 (state,SIO_TOP_JTAGID_LO__A , &jtag); -if (status <0 ) -break ; - status =read16 (state,SIO_PDR_UIO_IN_HI__A , &bid); -if (status <0 ) -break ; - status =write16 (state,SIO_TOP_COMM_KEY__A , key); -if (status <0 ) -break ; - }while (0 ); +/* stop lock indicator process */ + status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); +if (status <0 ) + goto error; +/* Check device id */ + status =read16 (state,SIO_TOP_COMM_KEY__A , &key); +if (status <0 ) + goto error; + status =write16 (state,SIO_TOP_COMM_KEY__A ,SIO_TOP_COMM_KEY_KEY ); +if (status <0 ) + goto error; + status =read32 (state,SIO_TOP_JTAGID_LO__A , &jtag); +if (status <0 ) + goto error; + status =read16 (state,SIO_PDR_UIO_IN_HI__A , &bid); +if (status <0 ) + goto error; + status =write16 (state,SIO_TOP_COMM_KEY__A , key); +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -895,177 +912,183 @@ static int GetDeviceCapabilities(struct drxk_state *state)int status;dprintk (1 ,"\n" ); -do { -/* driver 0.9.0 */ -/* stop lock indicator process */ - status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); -if (status <0 ) -break ; - status =write16 (state,SIO_TOP_COMM_KEY__A ,0xFABA ); -if (status <0 ) -break ; - status =read16 (state,SIO_PDR_OHW_CFG__A , &sioPdrOhwCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_TOP_COMM_KEY__A ,0x0000 ); -if (status <0 ) -break ; +/* driver 0.9.0 */ +/* stop lock indicator process */ + status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); +if (status <0 ) + goto error; + status =write16 (state,SIO_TOP_COMM_KEY__A ,0xFABA ); +if (status <0 ) + goto error; + status =read16 (state,SIO_PDR_OHW_CFG__A , &sioPdrOhwCfg); +if (status <0 ) + goto error; + status =write16 (state,SIO_TOP_COMM_KEY__A ,0x0000 ); +if (status <0 ) + goto error; -switch ((sioPdrOhwCfg &SIO_PDR_OHW_CFG_FREF_SEL__M )) { -case 0 : -/* ignore (bypass ?) */ -break ; -case 1 : -/* 27 MHz */ - state->m_oscClockFreq =27000 ; -break ; -case 2 : -/* 20.25 MHz */ - state->m_oscClockFreq =20250 ; -break ; -case 3 : -/* 4 MHz */ - state->m_oscClockFreq =20250 ; -break ; -default : -return -1 ; - } -/* -Determine device capabilities -Based on pinning v14 -*/ - status =read32 (state,SIO_TOP_JTAGID_LO__A , &sioTopJtagidLo); -if (status <0 ) -break ; -/* driver 0.9.0 */ -switch ((sioTopJtagidLo >>29 ) &0xF ) { -case 0 : - state->m_deviceSpin =DRXK_SPIN_A1 ; -break ; -case 2 : - state->m_deviceSpin =DRXK_SPIN_A2 ; -break ; -case 3 : - state->m_deviceSpin =DRXK_SPIN_A3 ; -break ; -default : - state->m_deviceSpin =DRXK_SPIN_UNKNOWN ; - status =-1 ; -break ; - } -switch ((sioTopJtagidLo >>12 ) &0xFF ) { -case 0x13 : -/* typeId = DRX3913K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = false; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = false; - state->m_hasGPIO1 = false; - state->m_hasIRQN = false; -break ; -case 0x15 : -/* typeId = DRX3915K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; -break ; -case 0x16 : -/* typeId = DRX3916K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; -break ; -case 0x18 : -/* typeId = DRX3918K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = false; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; -break ; -case 0x21 : -/* typeId = DRX3921K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; -break ; -case 0x23 : -/* typeId = DRX3923K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; -break ; -case 0x25 : -/* typeId = DRX3925K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = true; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; -break ; -case 0x26 : -/* typeId = DRX3926K_TYPE_ID */ - state->m_hasLNA = false; - state->m_hasOOB = false; - state->m_hasATV = true; - state->m_hasAudio = false; - state->m_hasDVBT = true; - state->m_hasDVBC = true; - state->m_hasSAWSW = true; - state->m_hasGPIO2 = true; - state->m_hasGPIO1 = true; - state->m_hasIRQN = false; -break ; -default : -printk (KERN_ERR "drxk: DeviceID not supported = %02x\n" , - ((sioTopJtagidLo >>12 ) &0xFF )); - status =-1 ; -break ; - } - }while (0 ); +switch ((sioPdrOhwCfg &SIO_PDR_OHW_CFG_FREF_SEL__M )) { +case 0 : +/* ignore (bypass ?) */ +break ; +case 1 : +/* 27 MHz */ + state->m_oscClockFreq =27000 ; +break ; +case 2 : +/* 20.25 MHz */ + state->m_oscClockFreq =20250 ; +break ; +case 3 : +/* 4 MHz */ + state->m_oscClockFreq =20250 ; +break ; +default : +printk (KERN_ERR "drxk: Clock Frequency is unkonwn\n" ); +return -EINVAL ; + } +/* +Determine device capabilities +Based on pinning v14 +*/ + status =read32 (state,SIO_TOP_JTAGID_LO__A , &sioTopJtagidLo); +if (status <0 ) + goto error; +/* driver 0.9.0 */ +switch ((sioTopJtagidLo >>29 ) &0xF ) { +case 0 : + state->m_deviceSpin =DRXK_SPIN_A1 ; +break ; +case 2 : + state->m_deviceSpin =DRXK_SPIN_A2 ; +break ; +case 3 : + state->m_deviceSpin =DRXK_SPIN_A3 ; +break ; +default : + state->m_deviceSpin =DRXK_SPIN_UNKNOWN ; + status = -EINVAL ; +printk (KERN_ERR "drxk: Spin unknown\n" ); + goto error2; + } +switch ((sioTopJtagidLo >>12 ) &0xFF ) { +case 0x13 : +/* typeId = DRX3913K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = false; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = false; + state->m_hasGPIO1 = false; + state->m_hasIRQN = false; +break ; +case 0x15 : +/* typeId = DRX3915K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; +break ; +case 0x16 : +/* typeId = DRX3916K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; +break ; +case 0x18 : +/* typeId = DRX3918K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = false; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; +break ; +case 0x21 : +/* typeId = DRX3921K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; +break ; +case 0x23 : +/* typeId = DRX3923K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; +break ; +case 0x25 : +/* typeId = DRX3925K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = true; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; +break ; +case 0x26 : +/* typeId = DRX3926K_TYPE_ID */ + state->m_hasLNA = false; + state->m_hasOOB = false; + state->m_hasATV = true; + state->m_hasAudio = false; + state->m_hasDVBT = true; + state->m_hasDVBC = true; + state->m_hasSAWSW = true; + state->m_hasGPIO2 = true; + state->m_hasGPIO1 = true; + state->m_hasIRQN = false; +break ; +default : +printk (KERN_ERR "drxk: DeviceID not supported = %02x\n" , + ((sioTopJtagidLo >>12 ) &0xFF )); + status = -EINVAL ; + goto error2; + } + +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); + +error2:return status; }
@@ -1079,7 +1102,7 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)/* Write command */ status =write16 (state,SIO_HI_RA_RAM_CMD__A , cmd);if (status <0 ) -return status; + goto error;if (cmd ==SIO_HI_RA_RAM_CMD_RESET )msleep (1 );
@@ -1100,11 +1123,14 @@ static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) &waitCmd); }while ((status <0 ) && (retryCount <DRXK_MAX_RETRIES ) && (waitCmd !=0 )); - -if (status ==0 ) - status =read16 (state,SIO_HI_RA_RAM_RES__A , - pResult); +if (status <0 ) + goto error; + status =read16 (state,SIO_HI_RA_RAM_RES__A , pResult); } +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); +return status; }
@@ -1115,32 +1141,34 @@ static int HI_CfgCommand(struct drxk_state *state)dprintk (1 ,"\n" );mutex_lock (&state->mutex); -do { - status =write16 (state,SIO_HI_RA_RAM_PAR_6__A , state->m_HICfgTimeout); -if (status <0 ) -break ; - status =write16 (state,SIO_HI_RA_RAM_PAR_5__A , state->m_HICfgCtrl); -if (status <0 ) -break ; - status =write16 (state,SIO_HI_RA_RAM_PAR_4__A , state->m_HICfgWakeUpKey); -if (status <0 ) -break ; - status =write16 (state,SIO_HI_RA_RAM_PAR_3__A , state->m_HICfgBridgeDelay); -if (status <0 ) -break ; - status =write16 (state,SIO_HI_RA_RAM_PAR_2__A , state->m_HICfgTimingDiv); -if (status <0 ) -break ; - status =write16 (state,SIO_HI_RA_RAM_PAR_1__A ,SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY ); -if (status <0 ) -break ; - status =HI_Command (state,SIO_HI_RA_RAM_CMD_CONFIG ,0 ); -if (status <0 ) -break ; - state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ ; - }while (0 ); + status =write16 (state,SIO_HI_RA_RAM_PAR_6__A , state->m_HICfgTimeout); +if (status <0 ) + goto error; + status =write16 (state,SIO_HI_RA_RAM_PAR_5__A , state->m_HICfgCtrl); +if (status <0 ) + goto error; + status =write16 (state,SIO_HI_RA_RAM_PAR_4__A , state->m_HICfgWakeUpKey); +if (status <0 ) + goto error; + status =write16 (state,SIO_HI_RA_RAM_PAR_3__A , state->m_HICfgBridgeDelay); +if (status <0 ) + goto error; + status =write16 (state,SIO_HI_RA_RAM_PAR_2__A , state->m_HICfgTimingDiv); +if (status <0 ) + goto error; + status =write16 (state,SIO_HI_RA_RAM_PAR_1__A ,SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY ); +if (status <0 ) + goto error; + status =HI_Command (state,SIO_HI_RA_RAM_CMD_CONFIG ,0 ); +if (status <0 ) + goto error; + + state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ ; +error:mutex_unlock (&state->mutex); +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -1152,6 +1180,7 @@ static int InitHI(struct drxk_state *state) state->m_HICfgTimeout =0x96FF ;/* port/bridge/power down ctrl */ state->m_HICfgCtrl =SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE ; +return HI_CfgCommand (state); }
@@ -1162,139 +1191,139 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)u16 sioPdrMdxCfg =0 ;dprintk (1 ,"\n" ); -do { -/* stop lock indicator process */ - status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); -if (status <0 ) -break ; -/* MPEG TS pad configuration */ - status =write16 (state,SIO_TOP_COMM_KEY__A ,0xFABA ); +/* stop lock indicator process */ + status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); +if (status <0 ) + goto error; + +/* MPEG TS pad configuration */ + status =write16 (state,SIO_TOP_COMM_KEY__A ,0xFABA ); +if (status <0 ) + goto error; + +if (mpegEnable == false) { +/* Set MPEG TS pads to inputmode */ + status =write16 (state,SIO_PDR_MSTRT_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MERR_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MCLK_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MVAL_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD0_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD1_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD2_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD3_CFG__A ,0x0000 );if (status <0 ) -break ; + goto error; + status =write16 (state,SIO_PDR_MD4_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD5_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD6_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD7_CFG__A ,0x0000 ); +if (status <0 ) + goto error; + }else { +/* Enable MPEG output */ + sioPdrMdxCfg = + ((state->m_TSDataStrength << +SIO_PDR_MD0_CFG_DRIVE__B ) |0x0003 ); + sioPdrMclkCfg = ((state->m_TSClockkStrength << +SIO_PDR_MCLK_CFG_DRIVE__B ) | +0x0003 ); -if (mpegEnable == false) { -/* Set MPEG TS pads to inputmode */ - status =write16 (state,SIO_PDR_MSTRT_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MSTRT_CFG__A , sioPdrMdxCfg); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MERR_CFG__A ,0x0000 );/* Disable */ +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MVAL_CFG__A ,0x0000 );/* Disable */ +if (status <0 ) + goto error; +if (state->m_enableParallel == true) { +/* paralel -> enable MD1 to MD7 */ + status =write16 (state,SIO_PDR_MD1_CFG__A , sioPdrMdxCfg); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD2_CFG__A , sioPdrMdxCfg); +if (status <0 ) + goto error; + status =write16 (state,SIO_PDR_MD3_CFG__A , sioPdrMdxCfg);if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MERR_CFG__A ,0x0000 ); + goto error; + status =write16 (state,SIO_PDR_MD4_CFG__A , sioPdrMdxCfg);if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MCLK_CFG__A ,0x0000 ); + goto error; + status =write16 (state,SIO_PDR_MD5_CFG__A , sioPdrMdxCfg);if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MVAL_CFG__A ,0x0000 ); + goto error; + status =write16 (state,SIO_PDR_MD6_CFG__A , sioPdrMdxCfg);if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD0_CFG__A ,0x0000 ); + goto error; + status =write16 (state,SIO_PDR_MD7_CFG__A , sioPdrMdxCfg);if (status <0 ) -break ; + goto error; + }else { + sioPdrMdxCfg = ((state->m_TSDataStrength << +SIO_PDR_MD0_CFG_DRIVE__B ) + |0x0003 ); +/* serial -> disable MD1 to MD7 */ status =write16 (state,SIO_PDR_MD1_CFG__A ,0x0000 );if (status <0 ) -break ; + goto error; status =write16 (state,SIO_PDR_MD2_CFG__A ,0x0000 );if (status <0 ) -break ; + goto error; status =write16 (state,SIO_PDR_MD3_CFG__A ,0x0000 );if (status <0 ) -break ; + goto error; status =write16 (state,SIO_PDR_MD4_CFG__A ,0x0000 );if (status <0 ) -break ; + goto error; status =write16 (state,SIO_PDR_MD5_CFG__A ,0x0000 );if (status <0 ) -break ; + goto error; status =write16 (state,SIO_PDR_MD6_CFG__A ,0x0000 );if (status <0 ) -break ; + goto error; status =write16 (state,SIO_PDR_MD7_CFG__A ,0x0000 );if (status <0 ) -break ; - }else { -/* Enable MPEG output */ - sioPdrMdxCfg = - ((state->m_TSDataStrength << -SIO_PDR_MD0_CFG_DRIVE__B ) |0x0003 ); - sioPdrMclkCfg = ((state->m_TSClockkStrength << -SIO_PDR_MCLK_CFG_DRIVE__B ) | -0x0003 ); - - status =write16 (state,SIO_PDR_MSTRT_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MERR_CFG__A ,0x0000 );/* Disable */ -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MVAL_CFG__A ,0x0000 );/* Disable */ -if (status <0 ) -break ; -if (state->m_enableParallel == true) { -/* paralel -> enable MD1 to MD7 */ - status =write16 (state,SIO_PDR_MD1_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD2_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD3_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD4_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD5_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD6_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD7_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; - }else { - sioPdrMdxCfg = ((state->m_TSDataStrength << -SIO_PDR_MD0_CFG_DRIVE__B ) - |0x0003 ); -/* serial -> disable MD1 to MD7 */ - status =write16 (state,SIO_PDR_MD1_CFG__A ,0x0000 ); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD2_CFG__A ,0x0000 ); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD3_CFG__A ,0x0000 ); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD4_CFG__A ,0x0000 ); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD5_CFG__A ,0x0000 ); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD6_CFG__A ,0x0000 ); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD7_CFG__A ,0x0000 ); -if (status <0 ) -break ; - } - status =write16 (state,SIO_PDR_MCLK_CFG__A , sioPdrMclkCfg); -if (status <0 ) -break ; - status =write16 (state,SIO_PDR_MD0_CFG__A , sioPdrMdxCfg); -if (status <0 ) -break ; + goto error; } -/* Enable MB output over MPEG pads and ctl input */ - status =write16 (state,SIO_PDR_MON_CFG__A ,0x0000 ); + status =write16 (state,SIO_PDR_MCLK_CFG__A , sioPdrMclkCfg);if (status <0 ) -break ; -/* Write nomagic word to enable pdr reg write */ - status =write16 (state,SIO_TOP_COMM_KEY__A ,0x0000 ); + goto error; + status =write16 (state,SIO_PDR_MD0_CFG__A , sioPdrMdxCfg);if (status <0 ) -break ; - }while (0 ); + goto error; + } +/* Enable MB output over MPEG pads and ctl input */ + status =write16 (state,SIO_PDR_MON_CFG__A ,0x0000 ); +if (status <0 ) + goto error; +/* Write nomagic word to enable pdr reg write */ + status =write16 (state,SIO_TOP_COMM_KEY__A ,0x0000 ); +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -1313,36 +1342,38 @@ static int BLChainCmd(struct drxk_state *state,unsigned long end;dprintk (1 ,"\n" ); -mutex_lock (&state->mutex); + status =write16 (state,SIO_BL_MODE__A ,SIO_BL_MODE_CHAIN ); +if (status <0 ) + goto error; + status =write16 (state,SIO_BL_CHAIN_ADDR__A , romOffset); +if (status <0 ) + goto error; + status =write16 (state,SIO_BL_CHAIN_LEN__A , nrOfElements); +if (status <0 ) + goto error; + status =write16 (state,SIO_BL_ENABLE__A ,SIO_BL_ENABLE_ON ); +if (status <0 ) + goto error; + + end = jiffies +msecs_to_jiffies (timeOut);do { - status =write16 (state,SIO_BL_MODE__A ,SIO_BL_MODE_CHAIN ); +msleep (1 ); + status =read16 (state,SIO_BL_STATUS__A , &blStatus);if (status <0 ) -break ; - status =write16 (state,SIO_BL_CHAIN_ADDR__A , romOffset); -if (status <0 ) -break ; - status =write16 (state,SIO_BL_CHAIN_LEN__A , nrOfElements); -if (status <0 ) -break ; - status =write16 (state,SIO_BL_ENABLE__A ,SIO_BL_ENABLE_ON ); -if (status <0 ) -break ; - end = jiffies +msecs_to_jiffies (timeOut); + goto error; + }while ((blStatus ==0x1 ) && + ((time_is_after_jiffies (end)))); -do { -msleep (1 ); - status =read16 (state,SIO_BL_STATUS__A , &blStatus); -if (status <0 ) -break ; - }while ((blStatus ==0x1 ) && - ((time_is_after_jiffies (end)))); -if (blStatus ==0x1 ) { -printk (KERN_ERR "drxk: SIO not ready\n" ); -mutex_unlock (&state->mutex); -return -1 ; - } - }while (0 ); +if (blStatus ==0x1 ) { +printk (KERN_ERR "drxk: SIO not ready\n" ); + status = -EINVAL ; + goto error2; + } +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); +error2:mutex_unlock (&state->mutex);return status; }
@@ -1421,25 +1452,24 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) desiredStatus =SIO_OFDM_SH_OFDM_RING_STATUS_DOWN ; } - status = (read16 (state,SIO_OFDM_SH_OFDM_RING_STATUS__A , &data)); - -if (data == desiredStatus) { + status =read16 (state,SIO_OFDM_SH_OFDM_RING_STATUS__A , &data); +if (status >=0 && data == desiredStatus) {/* tokenring already has correct status */ return status; }/* Disable/enable dvbt tokenring bridge */ - status = -write16 (state,SIO_OFDM_SH_OFDM_RING_ENABLE__A , desiredCtrl); + status =write16 (state,SIO_OFDM_SH_OFDM_RING_ENABLE__A , desiredCtrl); end = jiffies +msecs_to_jiffies (DRXK_OFDM_TR_SHUTDOWN_TIMEOUT );do { status =read16 (state,SIO_OFDM_SH_OFDM_RING_STATUS__A , &data); -if (status <0 ) +if ((status >=0 && data == desiredStatus) ||time_is_after_jiffies (end))break ; - }while ((data != desiredStatus) && ((time_is_after_jiffies (end)))); +msleep (1 ); + }while (1 );if (data != desiredStatus) {printk (KERN_ERR "drxk: SIO not ready\n" ); -return -1 ; +return -EINVAL ; }return status; }
@@ -1452,25 +1482,26 @@ static int MPEGTSStop(struct drxk_state *state)dprintk (1 ,"\n" ); -do { -/* Gracefull shutdown (byte boundaries) */ - status =read16 (state,FEC_OC_SNC_MODE__A , &fecOcSncMode); -if (status <0 ) -break ; - fecOcSncMode |=FEC_OC_SNC_MODE_SHUTDOWN__M ; - status =write16 (state,FEC_OC_SNC_MODE__A , fecOcSncMode); -if (status <0 ) -break ; +/* Gracefull shutdown (byte boundaries) */ + status =read16 (state,FEC_OC_SNC_MODE__A , &fecOcSncMode); +if (status <0 ) + goto error; + fecOcSncMode |=FEC_OC_SNC_MODE_SHUTDOWN__M ; + status =write16 (state,FEC_OC_SNC_MODE__A , fecOcSncMode); +if (status <0 ) + goto error; + +/* Suppress MCLK during absence of data */ + status =read16 (state,FEC_OC_IPR_MODE__A , &fecOcIprMode); +if (status <0 ) + goto error; + fecOcIprMode |=FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M ; + status =write16 (state,FEC_OC_IPR_MODE__A , fecOcIprMode); + +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); -/* Suppress MCLK during absence of data */ - status =read16 (state,FEC_OC_IPR_MODE__A , &fecOcIprMode); -if (status <0 ) -break ; - fecOcIprMode |=FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M ; - status =write16 (state,FEC_OC_IPR_MODE__A , fecOcIprMode); -if (status <0 ) -break ; - }while (0 );return status; }
@@ -1482,82 +1513,83 @@ static int scu_command(struct drxk_state *state,#error DRXK register mapping no longer compatible with this routine!#endif u16 curCmd =0 ; -int status; +int status = -EINVAL ;unsigned long end; +u8 buffer[34 ]; +int cnt =0 , ii;dprintk (1 ,"\n" );if ((cmd ==0 ) || ((parameterLen >0 ) && (parameter ==NULL )) || ((resultLen >0 ) && (result ==NULL ))) -return -1 ; + goto error;mutex_lock (&state->mutex); + +/* assume that the command register is ready +since it is checked afterwards */ +for (ii = parameterLen -1 ; ii >=0 ; ii -=1 ) { + buffer[cnt++] = (parameter[ii] &0xFF ); + buffer[cnt++] = ((parameter[ii] >>8 ) &0xFF ); + } + buffer[cnt++] = (cmd &0xFF ); + buffer[cnt++] = ((cmd >>8 ) &0xFF ); + +write_block (state,SCU_RAM_PARAM_0__A - + (parameterLen -1 ), cnt, buffer); +/* Wait until SCU has processed command */ + end = jiffies +msecs_to_jiffies (DRXK_MAX_WAITTIME );do { -/* assume that the command register is ready -since it is checked afterwards */ -u8 buffer[34 ]; -int cnt =0 , ii; +msleep (1 ); + status =read16 (state,SCU_RAM_COMMAND__A , &curCmd); +if (status <0 ) + goto error; + }while (!(curCmd ==DRX_SCU_READY ) && (time_is_after_jiffies (end))); +if (curCmd !=DRX_SCU_READY ) { +printk (KERN_ERR "drxk: SCU not ready\n" ); + status = -EIO ; + goto error2; + } +/* read results */ +if ((resultLen >0 ) && (result !=NULL )) { +s16 err; +int ii; -for (ii = parameterLen -1 ; ii >=0 ; ii -=1 ) { - buffer[cnt++] = (parameter[ii] &0xFF ); - buffer[cnt++] = ((parameter[ii] >>8 ) &0xFF ); - } - buffer[cnt++] = (cmd &0xFF ); - buffer[cnt++] = ((cmd >>8 ) &0xFF ); - -write_block (state,SCU_RAM_PARAM_0__A - - (parameterLen -1 ), cnt, buffer); -/* Wait until SCU has processed command */ - end = jiffies +msecs_to_jiffies (DRXK_MAX_WAITTIME ); -do { -msleep (1 ); - status =read16 (state,SCU_RAM_COMMAND__A , &curCmd); +for (ii = resultLen -1 ; ii >=0 ; ii -=1 ) { + status =read16 (state,SCU_RAM_PARAM_0__A - ii, &result[ii]);if (status <0 ) -break ; - }while (!(curCmd ==DRX_SCU_READY ) - && (time_is_after_jiffies (end))); -if (curCmd !=DRX_SCU_READY ) { -printk (KERN_ERR "drxk: SCU not ready\n" ); -mutex_unlock (&state->mutex); -return -1 ; + goto error; } -/* read results */ -if ((resultLen >0 ) && (result !=NULL )) { -s16 err; -int ii; -for (ii = resultLen -1 ; ii >=0 ; ii -=1 ) { - status =read16 (state,SCU_RAM_PARAM_0__A - ii, &result[ii]); -if (status <0 ) -break ; - } +/* Check if an error was reported by SCU */ + err = (s16 )result[0 ]; -/* Check if an error was reported by SCU */ - err = (s16 ) result[0 ]; - -/* check a few fixed error codes */ -if (err ==SCU_RESULT_UNKSTD ) { -printk (KERN_ERR "drxk: SCU_RESULT_UNKSTD\n" ); -mutex_unlock (&state->mutex); -return -1 ; - }else if (err ==SCU_RESULT_UNKCMD ) { -printk (KERN_ERR "drxk: SCU_RESULT_UNKCMD\n" ); -mutex_unlock (&state->mutex); -return -1 ; - } -/* here it is assumed that negative means error, -and positive no error */ -else if (err <0 ) { -printk (KERN_ERR "drxk: %s ERROR\n" , __func__); -mutex_unlock (&state->mutex); -return -1 ; - } +/* check a few fixed error codes */ +if (err ==SCU_RESULT_UNKSTD ) { +printk (KERN_ERR "drxk: SCU_RESULT_UNKSTD\n" ); + status = -EINVAL ; + goto error2; + }else if (err ==SCU_RESULT_UNKCMD ) { +printk (KERN_ERR "drxk: SCU_RESULT_UNKCMD\n" ); + status = -EINVAL ; + goto error2; + }else if (err <0 ) { +/* +* here it is assumed that a nagative result means +* error, and positive no error +*/ +printk (KERN_ERR "drxk: %s ERROR: %d\n" , __func__, err); + status = -EINVAL ; + goto error2; } - }while (0 ); -mutex_unlock (&state->mutex); + } + +error:if (status <0 ) -printk (KERN_ERR "drxk: %s: status = %d\n" , __func__, status); +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); +error2: +mutex_unlock (&state->mutex);return status; }
@@ -1568,30 +1600,30 @@ static int SetIqmAf(struct drxk_state *state, bool active)dprintk (1 ,"\n" ); -do { -/* Configure IQM */ - status =read16 (state,IQM_AF_STDBY__A , &data); -if (status <0 ) -break ; -if (!active) { - data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY - |IQM_AF_STDBY_STDBY_AMP_STANDBY - |IQM_AF_STDBY_STDBY_PD_STANDBY - |IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY - |IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ); - }else {/* active */ +/* Configure IQM */ + status =read16 (state,IQM_AF_STDBY__A , &data); +if (status <0 ) + goto error; - data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY ) - & (~IQM_AF_STDBY_STDBY_AMP_STANDBY ) - & (~IQM_AF_STDBY_STDBY_PD_STANDBY ) - & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ) - & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ) - ); - } - status =write16 (state,IQM_AF_STDBY__A , data); -if (status <0 ) -break ; - }while (0 ); +if (!active) { + data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY + |IQM_AF_STDBY_STDBY_AMP_STANDBY + |IQM_AF_STDBY_STDBY_PD_STANDBY + |IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY + |IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ); + }else { + data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY ) + & (~IQM_AF_STDBY_STDBY_AMP_STANDBY ) + & (~IQM_AF_STDBY_STDBY_PD_STANDBY ) + & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ) + & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ) + ); + } + status =write16 (state,IQM_AF_STDBY__A , data); + +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -1604,7 +1636,7 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)/* Check arguments */ if (mode ==NULL ) -return -1 ; +return -EINVAL ;switch (*mode) {case DRX_POWER_UP :
@@ -1624,7 +1656,7 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)break ;default :/* Unknow sleep mode */ -return -1 ; +return -EINVAL ;break ; }
@@ -1634,14 +1666,12 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)/* For next steps make sure to start from DRX_POWER_UP mode */ if (state->m_currentPowerMode !=DRX_POWER_UP ) { -do { - status =PowerUpDevice (state); -if (status <0 ) -break ; - status =DVBTEnableOFDMTokenRing (state, true); -if (status <0 ) -break ; - }while (0 ); + status =PowerUpDevice (state); +if (status <0 ) + goto error; + status =DVBTEnableOFDMTokenRing (state, true); +if (status <0 ) + goto error; }if (*mode ==DRX_POWER_UP ) {
@@ -1656,48 +1686,51 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)/* Power down device */ /* stop all comm_exec */ /* Stop and power down previous standard */ -do { -switch (state->m_OperationMode) { -case OM_DVBT : - status =MPEGTSStop (state); -if (status <0 ) -break ; - status =PowerDownDVBT (state, false); -if (status <0 ) -break ; -break ; -case OM_QAM_ITU_A : -case OM_QAM_ITU_C : - status =MPEGTSStop (state); -if (status <0 ) -break ; - status =PowerDownQAM (state); -if (status <0 ) -break ; -break ; -default : -break ; - } - status =DVBTEnableOFDMTokenRing (state, false); +switch (state->m_OperationMode) { +case OM_DVBT : + status =MPEGTSStop (state);if (status <0 ) -break ; - status =write16 (state,SIO_CC_PWD_MODE__A , sioCcPwdMode); + goto error; + status =PowerDownDVBT (state, false);if (status <0 ) -break ; - status =write16 (state,SIO_CC_UPDATE__A ,SIO_CC_UPDATE_KEY ); + goto error; +break ; +case OM_QAM_ITU_A : +case OM_QAM_ITU_C : + status =MPEGTSStop (state);if (status <0 ) -break ; + goto error; + status =PowerDownQAM (state); +if (status <0 ) + goto error; +break ; +default : +break ; + } + status =DVBTEnableOFDMTokenRing (state, false); +if (status <0 ) + goto error; + status =write16 (state,SIO_CC_PWD_MODE__A , sioCcPwdMode); +if (status <0 ) + goto error; + status =write16 (state,SIO_CC_UPDATE__A ,SIO_CC_UPDATE_KEY ); +if (status <0 ) + goto error; -if (*mode !=DRXK_POWER_DOWN_OFDM ) { - state->m_HICfgCtrl |= -SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ ; - status =HI_CfgCommand (state); -if (status <0 ) -break ; - } - }while (0 ); +if (*mode !=DRXK_POWER_DOWN_OFDM ) { + state->m_HICfgCtrl |= +SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ ; + status =HI_CfgCommand (state); +if (status <0 ) + goto error; + } } state->m_currentPowerMode = *mode; + +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); +return status; }
@@ -1710,44 +1743,45 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)dprintk (1 ,"\n" ); -do { - status =read16 (state,SCU_COMM_EXEC__A , &data); + status =read16 (state,SCU_COMM_EXEC__A , &data); +if (status <0 ) + goto error; +if (data ==SCU_COMM_EXEC_ACTIVE ) { +/* Send OFDM stop command */ + status =scu_command (state,SCU_RAM_COMMAND_STANDARD_OFDM |SCU_RAM_COMMAND_CMD_DEMOD_STOP ,0 ,NULL ,1 , &cmdResult);if (status <0 ) -break ; -if (data ==SCU_COMM_EXEC_ACTIVE ) { -/* Send OFDM stop command */ - status =scu_command (state,SCU_RAM_COMMAND_STANDARD_OFDM |SCU_RAM_COMMAND_CMD_DEMOD_STOP ,0 ,NULL ,1 , &cmdResult); -if (status <0 ) -break ; -/* Send OFDM reset command */ - status =scu_command (state,SCU_RAM_COMMAND_STANDARD_OFDM |SCU_RAM_COMMAND_CMD_DEMOD_RESET ,0 ,NULL ,1 , &cmdResult); -if (status <0 ) -break ; - } - -/* Reset datapath for OFDM, processors first */ - status =write16 (state,OFDM_SC_COMM_EXEC__A ,OFDM_SC_COMM_EXEC_STOP ); -if (status <0 ) -break ; - status =write16 (state,OFDM_LC_COMM_EXEC__A ,OFDM_LC_COMM_EXEC_STOP ); -if (status <0 ) -break ; - status =write16 (state,IQM_COMM_EXEC__A ,IQM_COMM_EXEC_B_STOP ); + goto error; +/* Send OFDM reset command */ + status =scu_command (state,SCU_RAM_COMMAND_STANDARD_OFDM |SCU_RAM_COMMAND_CMD_DEMOD_RESET ,0 ,NULL ,1 , &cmdResult);if (status <0 ) -break ; + goto error; + } -/* powerdown AFE */ - status =SetIqmAf (state, false); -if (status <0 ) -break ; +/* Reset datapath for OFDM, processors first */ + status =write16 (state,OFDM_SC_COMM_EXEC__A ,OFDM_SC_COMM_EXEC_STOP ); +if (status <0 ) + goto error; + status =write16 (state,OFDM_LC_COMM_EXEC__A ,OFDM_LC_COMM_EXEC_STOP ); +if (status <0 ) + goto error; + status =write16 (state,IQM_COMM_EXEC__A ,IQM_COMM_EXEC_B_STOP ); +if (status <0 ) + goto error; + +/* powerdown AFE */ + status =SetIqmAf (state, false); +if (status <0 ) + goto error; -/* powerdown to OFDM mode */ -if (setPowerMode) { - status =CtrlPowerMode (state, &powerMode); -if (status <0 ) -break ; - } - }while (0 ); +/* powerdown to OFDM mode */ +if (setPowerMode) { + status =CtrlPowerMode (state, &powerMode); +if (status <0 ) + goto error; + } +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -1762,127 +1796,118 @@ static int SetOperationMode(struct drxk_state *state,TODO investigate total power down instead of partial power down depending on "previous" standard. */ -do { -/* disable HW lock indicator */ - status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); -if (status <0 ) -break ; -if (state->m_OperationMode != oMode) { -switch (state->m_OperationMode) { -/* OM_NONE was added for start up */ -case OM_NONE : -break ; -case OM_DVBT : - status =MPEGTSStop (state); -if (status <0 ) -break ; - status =PowerDownDVBT (state, true); -if (status <0 ) -break ; - state->m_OperationMode =OM_NONE ; -break ; -case OM_QAM_ITU_B : - status =-1 ; -break ; -case OM_QAM_ITU_A :/* fallthrough */ -case OM_QAM_ITU_C : - status =MPEGTSStop (state); -if (status <0 ) -break ; - status =PowerDownQAM (state); -if (status <0 ) -break ; - state->m_OperationMode =OM_NONE ; -break ; -default : - status =-1 ; - } - status = status; -if (status <0 ) -break ; +/* disable HW lock indicator */ + status =write16 (state,SCU_RAM_GPIO__A ,SCU_RAM_GPIO_HW_LOCK_IND_DISABLE ); +if (status <0 ) + goto error; -/* -Power up new standard -*/ -switch (oMode) { -case OM_DVBT : - state->m_OperationMode = oMode; - status =SetDVBTStandard (state, oMode); -if (status <0 ) -break ; -break ; -case OM_QAM_ITU_B : - status =-1 ; -break ; -case OM_QAM_ITU_A :/* fallthrough */ -case OM_QAM_ITU_C : - state->m_OperationMode = oMode; - status =SetQAMStandard (state, oMode); -if (status <0 ) -break ; -break ; -default : - status =-1 ; - } +if (state->m_OperationMode != oMode) { +switch (state->m_OperationMode) { +/* OM_NONE was added for start up */ +case OM_NONE : +break ; +case OM_DVBT : + status =MPEGTSStop (state); +if (status <0 ) + goto error; + status =PowerDownDVBT (state, true); +if (status <0 ) + goto error; + state->m_OperationMode =OM_NONE ; +break ; +case OM_QAM_ITU_A :/* fallthrough */ +case OM_QAM_ITU_C : + status =MPEGTSStop (state); +if (status <0 ) + goto error; + status =PowerDownQAM (state); +if (status <0 ) + goto error; + state->m_OperationMode =OM_NONE ; +break ; +case OM_QAM_ITU_B : +default : + status = -EINVAL ; + goto error; } - status = status; -if (status <0 ) + +/* +Power up new standard +*/ +switch (oMode) { +case OM_DVBT : + status =SetDVBTStandard (state, oMode); +if (status <0 ) + goto error; + state->m_OperationMode = oMode;break ; - }while (0 ); -return 0 ; +case OM_QAM_ITU_A :/* fallthrough */ +case OM_QAM_ITU_C : + status =SetQAMStandard (state, oMode); +if (status <0 ) + goto error; + state->m_OperationMode = oMode; +break ; +case OM_QAM_ITU_B : +default : + status = -EINVAL ; + } + } +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); +return status; }static int Start (struct drxk_state *state,s32 offsetFreq,s32 IntermediateFrequency) { -int status =0 ; +int status = -EINVAL ; + +u16 IFreqkHz; +s32 OffsetkHz = offsetFreq /1000 ;dprintk (1 ,"\n" ); -do { -u16 IFreqkHz; -s32 OffsetkHz = offsetFreq /1000 ; +if (state->m_DrxkState !=DRXK_STOPPED && + state->m_DrxkState !=DRXK_DTV_STARTED ) + goto error; -if (state->m_DrxkState !=DRXK_STOPPED && - state->m_DrxkState !=DRXK_DTV_STARTED ) { - status =-1 ; -break ; - } - state->m_bMirrorFreqSpect = - (state->param.inversion ==INVERSION_ON ); + state->m_bMirrorFreqSpect = (state->param.inversion ==INVERSION_ON ); -if (IntermediateFrequency <0 ) { - state->m_bMirrorFreqSpect = - !state->m_bMirrorFreqSpect; - IntermediateFrequency = -IntermediateFrequency; - } +if (IntermediateFrequency <0 ) { + state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; + IntermediateFrequency = -IntermediateFrequency; + } -switch (state->m_OperationMode) { -case OM_QAM_ITU_A : -case OM_QAM_ITU_C : - IFreqkHz = (IntermediateFrequency /1000 ); - status =SetQAM (state, IFreqkHz, OffsetkHz); -if (status <0 ) -break ; - state->m_DrxkState =DRXK_DTV_STARTED ; -break ; -case OM_DVBT : - IFreqkHz = (IntermediateFrequency /1000 ); - status =MPEGTSStop (state); -if (status <0 ) -break ; - status =SetDVBT (state, IFreqkHz, OffsetkHz); -if (status <0 ) -break ; - status =DVBTStart (state); -if (status <0 ) -break ; - state->m_DrxkState =DRXK_DTV_STARTED ; -break ; -default : -break ; - } - }while (0 ); +switch (state->m_OperationMode) { +case OM_QAM_ITU_A : +case OM_QAM_ITU_C : + IFreqkHz = (IntermediateFrequency /1000 ); + status =SetQAM (state, IFreqkHz, OffsetkHz); +if (status <0 ) + goto error; + state->m_DrxkState =DRXK_DTV_STARTED ; +break ; +case OM_DVBT : + IFreqkHz = (IntermediateFrequency /1000 ); + status =MPEGTSStop (state); +if (status <0 ) + goto error; + status =SetDVBT (state, IFreqkHz, OffsetkHz); +if (status <0 ) + goto error; + status =DVBTStart (state); +if (status <0 ) + goto error; + state->m_DrxkState =DRXK_DTV_STARTED ; +break ; +default : +break ; + } +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -1897,12 +1922,12 @@ static int ShutDown(struct drxk_state *state)static int GetLockStatus (struct drxk_state *state,u32 *pLockStatus,u32 Time) { -int status =0 ; +int status = -EINVAL ;dprintk (1 ,"\n" );if (pLockStatus ==NULL ) -return -1 ; + goto error; *pLockStatus =NOT_LOCKED ;
@@ -1919,82 +1944,84 @@ static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,default :break ; } +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }static int MPEGTSStart (struct drxk_state *state) { -int status =0 ; +int status;u16 fecOcSncMode =0 ; -do { -/* Allow OC to sync again */ - status =read16 (state,FEC_OC_SNC_MODE__A , &fecOcSncMode); -if (status <0 ) -break ; - fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M ; - status =write16 (state,FEC_OC_SNC_MODE__A , fecOcSncMode); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_SNC_UNLOCK__A ,1 ); -if (status <0 ) -break ; - }while (0 ); +/* Allow OC to sync again */ + status =read16 (state,FEC_OC_SNC_MODE__A , &fecOcSncMode); +if (status <0 ) + goto error; + fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M ; + status =write16 (state,FEC_OC_SNC_MODE__A , fecOcSncMode); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_SNC_UNLOCK__A ,1 ); +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }static int MPEGTSDtoInit (struct drxk_state *state) { -int status =-1 ; +int status;dprintk (1 ,"\n" ); -do { -/* Rate integration settings */ - status =write16 (state,FEC_OC_RCN_CTL_STEP_LO__A ,0x0000 ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_RCN_CTL_STEP_HI__A ,0x000C ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_RCN_GAIN__A ,0x000A ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_AVR_PARM_A__A ,0x0008 ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_AVR_PARM_B__A ,0x0006 ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_TMD_HI_MARGIN__A ,0x0680 ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_TMD_LO_MARGIN__A ,0x0080 ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_TMD_COUNT__A ,0x03F4 ); -if (status <0 ) -break ; +/* Rate integration settings */ + status =write16 (state,FEC_OC_RCN_CTL_STEP_LO__A ,0x0000 ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_RCN_CTL_STEP_HI__A ,0x000C ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_RCN_GAIN__A ,0x000A ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_AVR_PARM_A__A ,0x0008 ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_AVR_PARM_B__A ,0x0006 ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_TMD_HI_MARGIN__A ,0x0680 ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_TMD_LO_MARGIN__A ,0x0080 ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_TMD_COUNT__A ,0x03F4 ); +if (status <0 ) + goto error; + +/* Additional configuration */ + status =write16 (state,FEC_OC_OCR_INVERT__A ,0 ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_SNC_LWM__A ,2 ); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_SNC_HWM__A ,12 ); +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); -/* Additional configuration */ - status =write16 (state,FEC_OC_OCR_INVERT__A ,0 ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_SNC_LWM__A ,2 ); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_SNC_HWM__A ,12 ); -if (status <0 ) -break ; - }while (0 );return status; }static int MPEGTSDtoSetup (struct drxk_state *state,enum OperationMode oMode) { -int status =-1 ; +int status;u16 fecOcRegMode =0 ;/* FEC_OC_MODE register value */ u16 fecOcRegIprMode =0 ;/* FEC_OC_IPR_MODE register value */
@@ -2010,132 +2037,127 @@ static int MPEGTSDtoSetup(struct drxk_state *state,dprintk (1 ,"\n" ); -do { -/* Check insertion of the Reed-Solomon parity bytes */ - status =read16 (state,FEC_OC_MODE__A , &fecOcRegMode); -if (status <0 ) -break ; - status =read16 (state,FEC_OC_IPR_MODE__A , &fecOcRegIprMode); -if (status <0 ) -break ; - fecOcRegMode &= (~FEC_OC_MODE_PARITY__M ); - fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M ); -if (state->m_insertRSByte == true) { -/* enable parity symbol forward */ - fecOcRegMode |=FEC_OC_MODE_PARITY__M ; -/* MVAL disable during parity bytes */ - fecOcRegIprMode |=FEC_OC_IPR_MODE_MVAL_DIS_PAR__M ; -/* TS burst length to 204 */ - fecOcDtoBurstLen =204 ; - } - -/* Check serial or parrallel output */ - fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M )); -if (state->m_enableParallel == false) { -/* MPEG data output is serial -> set ipr_mode[0] */ - fecOcRegIprMode |=FEC_OC_IPR_MODE_SERIAL__M ; - } +/* Check insertion of the Reed-Solomon parity bytes */ + status =read16 (state,FEC_OC_MODE__A , &fecOcRegMode); +if (status <0 ) + goto error; + status =read16 (state,FEC_OC_IPR_MODE__A , &fecOcRegIprMode); +if (status <0 ) + goto error; + fecOcRegMode &= (~FEC_OC_MODE_PARITY__M ); + fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M ); +if (state->m_insertRSByte == true) { +/* enable parity symbol forward */ + fecOcRegMode |=FEC_OC_MODE_PARITY__M ; +/* MVAL disable during parity bytes */ + fecOcRegIprMode |=FEC_OC_IPR_MODE_MVAL_DIS_PAR__M ; +/* TS burst length to 204 */ + fecOcDtoBurstLen =204 ; + } -switch (oMode) { -case OM_DVBT : - maxBitRate = state->m_DVBTBitrate; - fecOcTmdMode =3 ; - fecOcRcnCtlRate =0xC00000 ; - staticCLK = state->m_DVBTStaticCLK; -break ; -case OM_QAM_ITU_A :/* fallthrough */ -case OM_QAM_ITU_C : - fecOcTmdMode =0x0004 ; - fecOcRcnCtlRate =0xD2B4EE ;/* good for >63 Mb/s */ - maxBitRate = state->m_DVBCBitrate; - staticCLK = state->m_DVBCStaticCLK; -break ; -default : - status =-1 ; - }/* switch (standard) */ - status = status; -if (status <0 ) -break ; +/* Check serial or parrallel output */ + fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M )); +if (state->m_enableParallel == false) { +/* MPEG data output is serial -> set ipr_mode[0] */ + fecOcRegIprMode |=FEC_OC_IPR_MODE_SERIAL__M ; + } -/* Configure DTO's */ -if (staticCLK) { -u32 bitRate =0 ; +switch (oMode) { +case OM_DVBT : + maxBitRate = state->m_DVBTBitrate; + fecOcTmdMode =3 ; + fecOcRcnCtlRate =0xC00000 ; + staticCLK = state->m_DVBTStaticCLK; +break ; +case OM_QAM_ITU_A :/* fallthrough */ +case OM_QAM_ITU_C : + fecOcTmdMode =0x0004 ; + fecOcRcnCtlRate =0xD2B4EE ;/* good for >63 Mb/s */ + maxBitRate = state->m_DVBCBitrate; + staticCLK = state->m_DVBCStaticCLK; +break ; +default : + status = -EINVAL ; + }/* switch (standard) */ +if (status <0 ) + goto error; -/* Rational DTO for MCLK source (static MCLK rate), -Dynamic DTO for optimal grouping -(avoid intra-packet gaps), -DTO offset enable to sync TS burst with MSTRT */ - fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | -FEC_OC_DTO_MODE_OFFSET_ENABLE__M ); - fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | -FEC_OC_FCT_MODE_VIRT_ENA__M ); +/* Configure DTO's */ +if (staticCLK) { +u32 bitRate =0 ; -/* Check user defined bitrate */ - bitRate = maxBitRate; -if (bitRate >75900000UL ) {/* max is 75.9 Mb/s */ - bitRate =75900000UL ; - } -/* Rational DTO period: -dto_period = (Fsys / bitrate) - 2 +/* Rational DTO for MCLK source (static MCLK rate), +Dynamic DTO for optimal grouping +(avoid intra-packet gaps), +DTO offset enable to sync TS burst with MSTRT */ + fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | +FEC_OC_DTO_MODE_OFFSET_ENABLE__M ); + fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | +FEC_OC_FCT_MODE_VIRT_ENA__M ); -Result should be floored, -to make sure >= requested bitrate -*/ - fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) - *1000 ) / bitRate); -if (fecOcDtoPeriod <=2 ) - fecOcDtoPeriod =0 ; -else - fecOcDtoPeriod -=2 ; - fecOcTmdIntUpdRate =8 ; - }else { -/* (commonAttr->staticCLK == false) => dynamic mode */ - fecOcDtoMode =FEC_OC_DTO_MODE_DYNAMIC__M ; - fecOcFctMode =FEC_OC_FCT_MODE__PRE ; - fecOcTmdIntUpdRate =5 ; +/* Check user defined bitrate */ + bitRate = maxBitRate; +if (bitRate >75900000UL ) {/* max is 75.9 Mb/s */ + bitRate =75900000UL ; } +/* Rational DTO period: +dto_period = (Fsys / bitrate) - 2 + +Result should be floored, +to make sure >= requested bitrate +*/ + fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) + *1000 ) / bitRate); +if (fecOcDtoPeriod <=2 ) + fecOcDtoPeriod =0 ; +else + fecOcDtoPeriod -=2 ; + fecOcTmdIntUpdRate =8 ; + }else { +/* (commonAttr->staticCLK == false) => dynamic mode */ + fecOcDtoMode =FEC_OC_DTO_MODE_DYNAMIC__M ; + fecOcFctMode =FEC_OC_FCT_MODE__PRE ; + fecOcTmdIntUpdRate =5 ; + } -/* Write appropriate registers with requested configuration */ - status =write16 (state,FEC_OC_DTO_BURST_LEN__A , fecOcDtoBurstLen); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_DTO_PERIOD__A , fecOcDtoPeriod); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_DTO_MODE__A , fecOcDtoMode); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_FCT_MODE__A , fecOcFctMode); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_MODE__A , fecOcRegMode); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_IPR_MODE__A , fecOcRegIprMode); -if (status <0 ) -break ; +/* Write appropriate registers with requested configuration */ + status =write16 (state,FEC_OC_DTO_BURST_LEN__A , fecOcDtoBurstLen); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_DTO_PERIOD__A , fecOcDtoPeriod); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_DTO_MODE__A , fecOcDtoMode); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_FCT_MODE__A , fecOcFctMode); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_MODE__A , fecOcRegMode); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_IPR_MODE__A , fecOcRegIprMode); +if (status <0 ) + goto error; -/* Rate integration settings */ - status =write32 (state,FEC_OC_RCN_CTL_RATE_LO__A , fecOcRcnCtlRate); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_TMD_INT_UPD_RATE__A , fecOcTmdIntUpdRate); -if (status <0 ) -break ; - status =write16 (state,FEC_OC_TMD_MODE__A , fecOcTmdMode); -if (status <0 ) -break ; - }while (0 ); +/* Rate integration settings */ + status =write32 (state,FEC_OC_RCN_CTL_RATE_LO__A , fecOcRcnCtlRate); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_TMD_INT_UPD_RATE__A , fecOcTmdIntUpdRate); +if (status <0 ) + goto error; + status =write16 (state,FEC_OC_TMD_MODE__A , fecOcTmdMode); +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }static int MPEGTSConfigurePolarity (struct drxk_state *state) { -int status;u16 fecOcRegIprInvert =0 ; -dprintk (1 ,"\n" ); -/* Data mask for the output data byte */ u16 InvertDataMask = FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
@@ -2143,6 +2165,8 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)FEC_OC_IPR_INVERT_MD3__M |FEC_OC_IPR_INVERT_MD2__M |FEC_OC_IPR_INVERT_MD1__M |FEC_OC_IPR_INVERT_MD0__M ; +dprintk (1 ,"\n" ); +/* Control selective inversion of output bits */ fecOcRegIprInvert &= (~(InvertDataMask));if (state->m_invertDATA == true)
@@ -2159,8 +2183,8 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state) fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M ));if (state->m_invertCLK == true) fecOcRegIprInvert |=FEC_OC_IPR_INVERT_MCLK__M ; - status =write16 (state,FEC_OC_IPR_INVERT__A , fecOcRegIprInvert); -return status; + +return write16 (state,FEC_OC_IPR_INVERT__A , fecOcRegIprInvert); }#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
@@ -2168,145 +2192,145 @@ static int MPEGTSConfigurePolarity(struct drxk_state *state)static int SetAgcRf (struct drxk_state *state,struct SCfgAgc *pAgcCfg,bool isDTV) { -int status =0 ; +int status = -EINVAL ; +u16 data =0 ;struct SCfgAgc *pIfAgcSettings;dprintk (1 ,"\n" );if (pAgcCfg ==NULL ) -return -1 ; - -do { -u16 data =0 ; - -switch (pAgcCfg->ctrlMode) { -case DRXK_AGC_CTRL_AUTO : - -/* Enable RF AGC DAC */ - status =read16 (state,IQM_AF_STDBY__A , &data); -if (status <0 ) -break ; - data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; - status =write16 (state,IQM_AF_STDBY__A , data); -if (status <0 ) -break ; - - status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); -if (status <0 ) -break ; - -/* Enable SCU RF AGC loop */ - data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M ; - -/* Polarity */ -if (state->m_RfAgcPol) - data |=SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; -else - data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; - status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); -if (status <0 ) -break ; - -/* Set speed (using complementary reduction value) */ - status =read16 (state,SCU_RAM_AGC_KI_RED__A , &data); -if (status <0 ) -break ; - - data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M ; - data |= (~(pAgcCfg->speed << -SCU_RAM_AGC_KI_RED_RAGC_RED__B ) - &SCU_RAM_AGC_KI_RED_RAGC_RED__M ); - - status =write16 (state,SCU_RAM_AGC_KI_RED__A , data); -if (status <0 ) -break ; - -if (IsDVBT (state)) - pIfAgcSettings = &state->m_dvbtIfAgcCfg; -else if (IsQAM (state)) - pIfAgcSettings = &state->m_qamIfAgcCfg; -else - pIfAgcSettings = &state->m_atvIfAgcCfg; -if (pIfAgcSettings ==NULL ) -return -1 ; - -/* Set TOP, only if IF-AGC is in AUTO mode */ -if (pIfAgcSettings->ctrlMode ==DRXK_AGC_CTRL_AUTO ) - status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pAgcCfg->top); -if (status <0 ) -break ; - -/* Cut-Off current */ - status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI_CO__A , pAgcCfg->cutOffCurrent); -if (status <0 ) -break ; - -/* Max. output level */ - status =write16 (state,SCU_RAM_AGC_RF_MAX__A , pAgcCfg->maxOutputLevel); -if (status <0 ) -break ; - -break ; - -case DRXK_AGC_CTRL_USER : -/* Enable RF AGC DAC */ - status =read16 (state,IQM_AF_STDBY__A , &data); -if (status <0 ) -break ; - data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; - status =write16 (state,IQM_AF_STDBY__A , data); -if (status <0 ) -break ; - -/* Disable SCU RF AGC loop */ - status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); -if (status <0 ) -break ; - data |=SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M ; -if (state->m_RfAgcPol) - data |=SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; -else - data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; - status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); -if (status <0 ) -break ; - -/* SCU c.o.c. to 0, enabling full control range */ - status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI_CO__A ,0 ); -if (status <0 ) -break ; - -/* Write value to output pin */ - status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI__A , pAgcCfg->outputLevel); -if (status <0 ) -break ; -break ; - -case DRXK_AGC_CTRL_OFF : -/* Disable RF AGC DAC */ - status =read16 (state,IQM_AF_STDBY__A , &data); -if (status <0 ) -break ; - data |=IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; - status =write16 (state,IQM_AF_STDBY__A , data); -if (status <0 ) -break ; - -/* Disable SCU RF AGC loop */ - status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); -if (status <0 ) -break ; - data |=SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M ; - status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); -if (status <0 ) -break ; -break ; - -default : -return -1 ; - - }/* switch (agcsettings->ctrlMode) */ - }while (0 ); + goto error; + +switch (pAgcCfg->ctrlMode) { +case DRXK_AGC_CTRL_AUTO : +/* Enable RF AGC DAC */ + status =read16 (state,IQM_AF_STDBY__A , &data); +if (status <0 ) + goto error; + data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; + status =write16 (state,IQM_AF_STDBY__A , data); +if (status <0 ) + goto error; + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); +if (status <0 ) + goto error; + +/* Enable SCU RF AGC loop */ + data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M ; + +/* Polarity */ +if (state->m_RfAgcPol) + data |=SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; +else + data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); +if (status <0 ) + goto error; + +/* Set speed (using complementary reduction value) */ + status =read16 (state,SCU_RAM_AGC_KI_RED__A , &data); +if (status <0 ) + goto error; + + data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M ; + data |= (~(pAgcCfg->speed << +SCU_RAM_AGC_KI_RED_RAGC_RED__B ) + &SCU_RAM_AGC_KI_RED_RAGC_RED__M ); + + status =write16 (state,SCU_RAM_AGC_KI_RED__A , data); +if (status <0 ) + goto error; + +if (IsDVBT (state)) + pIfAgcSettings = &state->m_dvbtIfAgcCfg; +else if (IsQAM (state)) + pIfAgcSettings = &state->m_qamIfAgcCfg; +else + pIfAgcSettings = &state->m_atvIfAgcCfg; +if (pIfAgcSettings ==NULL ) { + status = -EINVAL ; + goto error; + } + +/* Set TOP, only if IF-AGC is in AUTO mode */ +if (pIfAgcSettings->ctrlMode ==DRXK_AGC_CTRL_AUTO ) + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pAgcCfg->top); +if (status <0 ) + goto error; + +/* Cut-Off current */ + status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI_CO__A , pAgcCfg->cutOffCurrent); +if (status <0 ) + goto error; + +/* Max. output level */ + status =write16 (state,SCU_RAM_AGC_RF_MAX__A , pAgcCfg->maxOutputLevel); +if (status <0 ) + goto error; + +break ; + +case DRXK_AGC_CTRL_USER : +/* Enable RF AGC DAC */ + status =read16 (state,IQM_AF_STDBY__A , &data); +if (status <0 ) + goto error; + data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; + status =write16 (state,IQM_AF_STDBY__A , data); +if (status <0 ) + goto error; + +/* Disable SCU RF AGC loop */ + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); +if (status <0 ) + goto error; + data |=SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M ; +if (state->m_RfAgcPol) + data |=SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; +else + data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M ; + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); +if (status <0 ) + goto error; + +/* SCU c.o.c. to 0, enabling full control range */ + status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI_CO__A ,0 ); +if (status <0 ) + goto error; + +/* Write value to output pin */ + status =write16 (state,SCU_RAM_AGC_RF_IACCU_HI__A , pAgcCfg->outputLevel); +if (status <0 ) + goto error; +break ; + +case DRXK_AGC_CTRL_OFF : +/* Disable RF AGC DAC */ + status =read16 (state,IQM_AF_STDBY__A , &data); +if (status <0 ) + goto error; + data |=IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY ; + status =write16 (state,IQM_AF_STDBY__A , data); +if (status <0 ) + goto error; + +/* Disable SCU RF AGC loop */ + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); +if (status <0 ) + goto error; + data |=SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M ; + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); +if (status <0 ) + goto error; +break ; + +default : + status = -EINVAL ; + + } +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -2321,144 +2345,146 @@ static int SetAgcIf(struct drxk_state *state,dprintk (1 ,"\n" ); -do { -switch (pAgcCfg->ctrlMode) { -case DRXK_AGC_CTRL_AUTO : - -/* Enable IF AGC DAC */ - status =read16 (state,IQM_AF_STDBY__A , &data); -if (status <0 ) -break ; - data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; - status =write16 (state,IQM_AF_STDBY__A , data); -if (status <0 ) -break ; - - status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); -if (status <0 ) -break ; - -/* Enable SCU IF AGC loop */ - data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M ; - -/* Polarity */ -if (state->m_IfAgcPol) - data |=SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; -else - data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; - status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); -if (status <0 ) -break ; - -/* Set speed (using complementary reduction value) */ - status =read16 (state,SCU_RAM_AGC_KI_RED__A , &data); -if (status <0 ) -break ; - data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M ; - data |= (~(pAgcCfg->speed << -SCU_RAM_AGC_KI_RED_IAGC_RED__B ) - &SCU_RAM_AGC_KI_RED_IAGC_RED__M ); - - status =write16 (state,SCU_RAM_AGC_KI_RED__A , data); -if (status <0 ) -break ; - -if (IsQAM (state)) - pRfAgcSettings = &state->m_qamRfAgcCfg; -else - pRfAgcSettings = &state->m_atvRfAgcCfg; -if (pRfAgcSettings ==NULL ) -return -1 ; -/* Restore TOP */ - status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pRfAgcSettings->top); -if (status <0 ) -break ; -break ; - -case DRXK_AGC_CTRL_USER : - -/* Enable IF AGC DAC */ - status =read16 (state,IQM_AF_STDBY__A , &data); -if (status <0 ) -break ; - data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; - status =write16 (state,IQM_AF_STDBY__A , data); -if (status <0 ) -break ; - - status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); -if (status <0 ) -break ; - -/* Disable SCU IF AGC loop */ - data |=SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M ; - -/* Polarity */ -if (state->m_IfAgcPol) - data |=SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; -else - data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; - status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); -if (status <0 ) -break ; - -/* Write value to output pin */ - status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pAgcCfg->outputLevel); -if (status <0 ) -break ; -break ; - -case DRXK_AGC_CTRL_OFF : - -/* Disable If AGC DAC */ - status =read16 (state,IQM_AF_STDBY__A , &data); -if (status <0 ) -break ; - data |=IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; - status =write16 (state,IQM_AF_STDBY__A , data); -if (status <0 ) -break ; - -/* Disable SCU IF AGC loop */ - status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); -if (status <0 ) -break ; - data |=SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M ; - status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); -if (status <0 ) -break ; -break ; - }/* switch (agcSettingsIf->ctrlMode) */ - -/* always set the top to support -configurations without if-loop */ - status =write16 (state,SCU_RAM_AGC_INGAIN_TGT_MIN__A , pAgcCfg->top); -if (status <0 ) -break ; - - - }while (0 ); +switch (pAgcCfg->ctrlMode) { +case DRXK_AGC_CTRL_AUTO : + +/* Enable IF AGC DAC */ + status =read16 (state,IQM_AF_STDBY__A , &data); +if (status <0 ) + goto error; + data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; + status =write16 (state,IQM_AF_STDBY__A , data); +if (status <0 ) + goto error; + + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); +if (status <0 ) + goto error; + +/* Enable SCU IF AGC loop */ + data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M ; + +/* Polarity */ +if (state->m_IfAgcPol) + data |=SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; +else + data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); +if (status <0 ) + goto error; + +/* Set speed (using complementary reduction value) */ + status =read16 (state,SCU_RAM_AGC_KI_RED__A , &data); +if (status <0 ) + goto error; + data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M ; + data |= (~(pAgcCfg->speed << +SCU_RAM_AGC_KI_RED_IAGC_RED__B ) + &SCU_RAM_AGC_KI_RED_IAGC_RED__M ); + + status =write16 (state,SCU_RAM_AGC_KI_RED__A , data); +if (status <0 ) + goto error; + +if (IsQAM (state)) + pRfAgcSettings = &state->m_qamRfAgcCfg; +else + pRfAgcSettings = &state->m_atvRfAgcCfg; +if (pRfAgcSettings ==NULL ) +return -1 ; +/* Restore TOP */ + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pRfAgcSettings->top); +if (status <0 ) + goto error; +break ; + +case DRXK_AGC_CTRL_USER : + +/* Enable IF AGC DAC */ + status =read16 (state,IQM_AF_STDBY__A , &data); +if (status <0 ) + goto error; + data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; + status =write16 (state,IQM_AF_STDBY__A , data); +if (status <0 ) + goto error; + + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); +if (status <0 ) + goto error; + +/* Disable SCU IF AGC loop */ + data |=SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M ; + +/* Polarity */ +if (state->m_IfAgcPol) + data |=SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; +else + data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M ; + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); +if (status <0 ) + goto error; + +/* Write value to output pin */ + status =write16 (state,SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A , pAgcCfg->outputLevel); +if (status <0 ) + goto error; +break ; + +case DRXK_AGC_CTRL_OFF : + +/* Disable If AGC DAC */ + status =read16 (state,IQM_AF_STDBY__A , &data); +if (status <0 ) + goto error; + data |=IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY ; + status =write16 (state,IQM_AF_STDBY__A , data); +if (status <0 ) + goto error; + +/* Disable SCU IF AGC loop */ + status =read16 (state,SCU_RAM_AGC_CONFIG__A , &data); +if (status <0 ) + goto error; + data |=SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M ; + status =write16 (state,SCU_RAM_AGC_CONFIG__A , data); +if (status <0 ) + goto error; +break ; + }/* switch (agcSettingsIf->ctrlMode) */ + +/* always set the top to support +configurations without if-loop */ + status =write16 (state,SCU_RAM_AGC_INGAIN_TGT_MIN__A , pAgcCfg->top); +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }static int ReadIFAgc (struct drxk_state *state,u32 *pValue) {u16 agcDacLvl; -int status =read16 (state,IQM_AF_AGC_IF__A , &agcDacLvl); +int status; +u16 Level =0 ;dprintk (1 ,"\n" ); + status =read16 (state,IQM_AF_AGC_IF__A , &agcDacLvl); +if (status <0 ) { +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); +return status; + } + *pValue =0 ; -if (status ==0 ) { -u16 Level =0 ; -if (agcDacLvl >DRXK_AGC_DAC_OFFSET ) - Level = agcDacLvl -DRXK_AGC_DAC_OFFSET ; -if (Level <14000 ) - *pValue = (14000 - Level) /4 ; -else - *pValue =0 ; - } +if (agcDacLvl >DRXK_AGC_DAC_OFFSET ) + Level = agcDacLvl -DRXK_AGC_DAC_OFFSET ; +if (Level <14000 ) + *pValue = (14000 - Level) /4 ; +else + *pValue =0 ; +return status; }
@@ -2466,55 +2492,55 @@ static int GetQAMSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) {int status =0 ; +u16 qamSlErrPower =0 ;/* accum. error between +raw and sliced symbols */ +u32 qamSlSigPower =0 ;/* used for MER, depends of +QAM constellation */ +u32 qamSlMer =0 ;/* QAM MER */ dprintk (1 ,"\n" ); -do { -/* MER calculation */ -u16 qamSlErrPower =0 ;/* accum. error between -raw and sliced symbols */ -u32 qamSlSigPower =0 ;/* used for MER, depends of -QAM constellation */ -u32 qamSlMer =0 ;/* QAM MER */ +/* MER calculation */ -/* get the register value needed for MER */ - status =read16 (state,QAM_SL_ERR_POWER__A , &qamSlErrPower); -if (status <0 ) -break ; +/* get the register value needed for MER */ + status =read16 (state,QAM_SL_ERR_POWER__A , &qamSlErrPower); +if (status <0 ) { +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); +return -EINVAL ; + } -switch (state->param.u.qam.modulation) { -case QAM_16 : - qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM16 <<2 ; -break ; -case QAM_32 : - qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM32 <<2 ; -break ; -case QAM_64 : - qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM64 <<2 ; -break ; -case QAM_128 : - qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM128 <<2 ; -break ; -default : -case QAM_256 : - qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM256 <<2 ; -break ; - } +switch (state->param.u.qam.modulation) { +case QAM_16 : + qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM16 <<2 ; +break ; +case QAM_32 : + qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM32 <<2 ; +break ; +case QAM_64 : + qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM64 <<2 ; +break ; +case QAM_128 : + qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM128 <<2 ; +break ; +default : +case QAM_256 : + qamSlSigPower =DRXK_QAM_SL_SIG_POWER_QAM256 <<2 ; +break ; + } + +if (qamSlErrPower >0 ) { + qamSlMer =Log10Times100 (qamSlSigPower) - +Log10Times100 ((u32 ) qamSlErrPower); + } + *pSignalToNoise = qamSlMer; -if (qamSlErrPower >0 ) { - qamSlMer =Log10Times100 (qamSlSigPower) - -Log10Times100 ((u32 ) qamSlErrPower); - } - *pSignalToNoise = qamSlMer; - }while (0 );return status; }static int GetDVBTSignalToNoise (struct drxk_state *state,s32 *pSignalToNoise) { -int status =0 ; - +int status;u16 regData =0 ;u32 EqRegTdSqrErrI =0 ;u32 EqRegTdSqrErrQ =0 ;
@@ -2530,86 +2556,88 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,u16 transmissionParams =0 ;dprintk (1 ,"\n" ); -do { - status =read16 (state,OFDM_EQ_TOP_TD_TPS_PWR_OFS__A , &EqRegTdTpsPwrOfs); -if (status <0 ) -break ; - status =read16 (state,OFDM_EQ_TOP_TD_REQ_SMB_CNT__A , &EqRegTdReqSmbCnt); -if (status <0 ) -break ; - status =read16 (state,OFDM_EQ_TOP_TD_SQR_ERR_EXP__A , &EqRegTdSqrErrExp); -if (status <0 ) -break ; - status =read16 (state,OFDM_EQ_TOP_TD_SQR_ERR_I__A , ®Data); -if (status <0 ) -break ; -/* Extend SQR_ERR_I operational range */ - EqRegTdSqrErrI = (u32 ) regData; -if ((EqRegTdSqrErrExp >11 ) && - (EqRegTdSqrErrI <0x00000FFFUL )) { - EqRegTdSqrErrI +=0x00010000UL ; - } - status =read16 (state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A , ®Data); -if (status <0 ) -break ; -/* Extend SQR_ERR_Q operational range */ - EqRegTdSqrErrQ = (u32 ) regData; -if ((EqRegTdSqrErrExp >11 ) && - (EqRegTdSqrErrQ <0x00000FFFUL )) - EqRegTdSqrErrQ +=0x00010000UL ; - status =read16 (state,OFDM_SC_RA_RAM_OP_PARAM__A , &transmissionParams); -if (status <0 ) -break ; + status =read16 (state,OFDM_EQ_TOP_TD_TPS_PWR_OFS__A , &EqRegTdTpsPwrOfs); +if (status <0 ) + goto error; + status =read16 (state,OFDM_EQ_TOP_TD_REQ_SMB_CNT__A , &EqRegTdReqSmbCnt); +if (status <0 ) + goto error; + status =read16 (state,OFDM_EQ_TOP_TD_SQR_ERR_EXP__A , &EqRegTdSqrErrExp); +if (status <0 ) + goto error; + status =read16 (state,OFDM_EQ_TOP_TD_SQR_ERR_I__A , ®Data); +if (status <0 ) + goto error; +/* Extend SQR_ERR_I operational range */ + EqRegTdSqrErrI = (u32 ) regData; +if ((EqRegTdSqrErrExp >11 ) && + (EqRegTdSqrErrI <0x00000FFFUL )) { + EqRegTdSqrErrI +=0x00010000UL ; + } + status =read16 (state,OFDM_EQ_TOP_TD_SQR_ERR_Q__A , ®Data); +if (status <0 ) + goto error; +/* Extend SQR_ERR_Q operational range */ + EqRegTdSqrErrQ = (u32 ) regData; +if ((EqRegTdSqrErrExp >11 ) && + (EqRegTdSqrErrQ <0x00000FFFUL )) + EqRegTdSqrErrQ +=0x00010000UL ; -/* Check input data for MER */ + status =read16 (state,OFDM_SC_RA_RAM_OP_PARAM__A , &transmissionParams); +if (status <0 ) + goto error; -/* MER calculation (in 0.1 dB) without math.h */ -if ((EqRegTdTpsPwrOfs ==0 ) || (EqRegTdReqSmbCnt ==0 )) - iMER =0 ; -else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) ==0 ) { -/* No error at all, this must be the HW reset value -* Apparently no first measurement yet -* Set MER to 0.0 */ - iMER =0 ; - }else { - SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << - EqRegTdSqrErrExp; -if ((transmissionParams & -OFDM_SC_RA_RAM_OP_PARAM_MODE__M ) - ==OFDM_SC_RA_RAM_OP_PARAM_MODE_2K ) - tpsCnt =17 ; -else - tpsCnt =68 ; +/* Check input data for MER */ -/* IMER = 100 * log10 (x) -where x = (EqRegTdTpsPwrOfs^2 * -EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ +/* MER calculation (in 0.1 dB) without math.h */ +if ((EqRegTdTpsPwrOfs ==0 ) || (EqRegTdReqSmbCnt ==0 )) + iMER =0 ; +else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) ==0 ) { +/* No error at all, this must be the HW reset value +* Apparently no first measurement yet +* Set MER to 0.0 */ + iMER =0 ; + }else { + SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << + EqRegTdSqrErrExp; +if ((transmissionParams & +OFDM_SC_RA_RAM_OP_PARAM_MODE__M ) + ==OFDM_SC_RA_RAM_OP_PARAM_MODE_2K ) + tpsCnt =17 ; +else + tpsCnt =68 ; -=> IMER = a + b -c -where a = 100 * log10 (EqRegTdTpsPwrOfs^2) -b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) -c = 100 * log10 (SqrErrIQ) -*/ +/* IMER = 100 * log10 (x) +where x = (EqRegTdTpsPwrOfs^2 * +EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ -/* log(x) x = 9bits * 9bits->18 bits */ - a =Log10Times100 (EqRegTdTpsPwrOfs * - EqRegTdTpsPwrOfs); -/* log(x) x = 16bits * 7bits->23 bits */ - b =Log10Times100 (EqRegTdReqSmbCnt * tpsCnt); -/* log(x) x = (16bits + 16bits) << 15 ->32 bits */ - c =Log10Times100 (SqrErrIQ); +=> IMER = a + b -c +where a = 100 * log10 (EqRegTdTpsPwrOfs^2) +b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) +c = 100 * log10 (SqrErrIQ) +*/ - iMER = a + b; -/* No negative MER, clip to zero */ -if (iMER > c) - iMER -= c; -else - iMER =0 ; - } - *pSignalToNoise = iMER; - }while (0 ); +/* log(x) x = 9bits * 9bits->18 bits */ + a =Log10Times100 (EqRegTdTpsPwrOfs * + EqRegTdTpsPwrOfs); +/* log(x) x = 16bits * 7bits->23 bits */ + b =Log10Times100 (EqRegTdReqSmbCnt * tpsCnt); +/* log(x) x = (16bits + 16bits) << 15 ->32 bits */ + c =Log10Times100 (SqrErrIQ); + + iMER = a + b; +/* No negative MER, clip to zero */ +if (iMER > c) + iMER -= c; +else + iMER =0 ; + } + *pSignalToNoise = iMER; +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -2775,50 +2803,54 @@ static int GetQuality(struct drxk_state *state, s32 *pQuality)static int ConfigureI2CBridge (struct drxk_state *state,bool bEnableBridge) { -int status; +int status = -EINVAL ;dprintk (1 ,"\n" );if (state->m_DrxkState ==DRXK_UNINITIALIZED ) -return -1 ; + goto error;if (state->m_DrxkState ==DRXK_POWERED_DOWN ) -return -1 ; + goto error;if (state->no_i2c_bridge)return 0 ; -do { - status =write16 (state,SIO_HI_RA_RAM_PAR_1__A ,SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY ); -if (status <0 ) -break ; -if (bEnableBridge) { - status =write16 (state,SIO_HI_RA_RAM_PAR_2__A ,SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED ); -if (status <0 ) -break ; - }else { - status =write16 (state,SIO_HI_RA_RAM_PAR_2__A ,SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN ); -if (status <0 ) -break ; - } - status =HI_Command (state,SIO_HI_RA_RAM_CMD_BRDCTRL ,0 ); + status =write16 (state,SIO_HI_RA_RAM_PAR_1__A ,SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY ); +if (status <0 ) + goto error; +if (bEnableBridge) { + status =write16 (state,SIO_HI_RA_RAM_PAR_2__A ,SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED ); +if (status <0 ) + goto error; + }else { + status =write16 (state,SIO_HI_RA_RAM_PAR_2__A ,SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN );if (status <0 ) -break ; - }while (0 ); + goto error; + } + + status =HI_Command (state,SIO_HI_RA_RAM_CMD_BRDCTRL ,0 ); + +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }static int SetPreSaw (struct drxk_state *state,struct SCfgPreSaw *pPreSawCfg) { -int status; +int status = -EINVAL ;dprintk (1 ,"\n" );if ((pPreSawCfg ==NULL ) || (pPreSawCfg->reference >IQM_AF_PDREF__M )) -return -1 ; + goto error; status =write16 (state,IQM_AF_PDREF__A , pPreSawCfg->reference); +error: +if (status <0 ) +printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);return status; }
@@ -2834,38 +2866,40 @@ static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,dprintk (1 ,"\n" );mutex_lock (&state->mutex); - do { - status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); - if (status < 0) - break; - status = write16(state, SIO_BL_TGT_HDR__A, blockbank); - if (status < 0) - break; - status = write16(state, SIO_BL_TGT_ADDR__A, offset); - if (status < 0) - break; - status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); - if (status < 0) - break; - status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); - if (status < 0) - break; - status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); - if (status < 0) - break; + status =write16 (state,SIO_BL_MODE__A ,SIO_BL_MODE_DIRECT ); +if (status <0 ) + goto error; + status =write16 (state,SIO_BL_TGT_HDR__A , blockbank); +if (status <0 ) + goto error; + status =write16 (state,SIO_BL_TGT_ADDR__A , offset); +if (status <0 ) + goto error; + status =write16 (state,SIO_BL_SRC_ADDR__A , romOffset); +if (status <0 ) + goto error; + status =write16 (state,SIO_BL_SRC_LEN__A , nrOfElements); +if (status <0 ) + goto error; + status =write16 (state,SIO_BL_ENABLE__A ,SIO_BL_ENABLE_ON );
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Signature · 1 line
1.7.1
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PATCH 14/21 drxk: change mode before calling the set mode routines
In reply to a message not in the archiveThe set mode routines assume that state were changed to the new mode, otherwise, they'll fail.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +2 -2
@@ -1837,17 +1837,17 @@ static int SetOperationMode(struct drxk_state *state,*/ switch (oMode) {case OM_DVBT : + state->m_OperationMode = oMode; status =SetDVBTStandard (state, oMode);if (status <0 ) goto error; - state->m_OperationMode = oMode;break ;case OM_QAM_ITU_A :/* fallthrough */ case OM_QAM_ITU_C : + state->m_OperationMode = oMode; status =SetQAMStandard (state, oMode);if (status <0 ) goto error; - state->m_OperationMode = oMode;break ;case OM_QAM_ITU_B :default :
Signature · 1 line
1.7.1
PATCH 15/21 drxk: Fix the antenna switch logic
In reply to a message not in the archiveTerratec H5 doesn't require to switch mode, but generates an error due to this logic. Also, GPIO's are board-dependent.
So, add it at the board config struct.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk.h +18 -3
@@ -4,10 +4,25 @@#include <linux/types.h> #include <linux/i2c.h> +/** +* struct drxk_config - Configure the initial parameters for DRX-K +* +* adr: I2C Address of the DRX-K +* single_master: Device is on the single master mode +* no_i2c_bridge: Don't switch the I2C bridge to talk with tuner +* antenna_uses_gpio: Use GPIO to control the antenna +* antenna_dvbc: GPIO for changing antenna to DVB-C +* antenna_dvbt: GPIO for changing antenna to DVB-T +* microcode_name: Name of the firmware file with the microcode +*/ struct drxk_config { -u8 adr; -u32 single_master :1 ; -u32 no_i2c_bridge :1 ; +u8 adr; +bool single_master; +bool no_i2c_bridge; + +bool antenna_uses_gpio; +u16 antenna_dvbc, antenna_dvbt; +const char *microcode_name; };
drivers/media/dvb/frontends/drxk_hard.c +10 -11
@@ -618,6 +618,10 @@ error:static int init_state (struct drxk_state *state) { +/* +* FIXME: most (all?) of the values bellow should be moved into +* struct drxk_config, as they are probably board-specific +*/ u32 ulVSBIfAgcMode =DRXK_AGC_CTRL_AUTO ;u32 ulVSBIfAgcOutputLevel =0 ;u32 ulVSBIfAgcMinLevel =0 ;
@@ -672,10 +676,6 @@ static int init_state(struct drxk_state *state)u32 ulRfMirror =1 ;u32 ulPowerDown =0 ; -u32 ulAntennaDVBT =1 ; -u32 ulAntennaDVBC =0 ; -u32 ulAntennaSwitchDVBTDVBC =0 ; -dprintk (1 ,"\n" ); state->m_hasLNA = false;
@@ -858,11 +858,6 @@ static int init_state(struct drxk_state *state) state->m_GPIOCfg = (ulGPIOCfg); state->m_GPIO = (ulGPIO ==0 ?0 :1 ); - state->m_AntennaDVBT = (ulAntennaDVBT ==0 ?0 :1 ); - state->m_AntennaDVBC = (ulAntennaDVBC ==0 ?0 :1 ); - state->m_AntennaSwitchDVBTDVBC = - (ulAntennaSwitchDVBTDVBC ==0 ?0 :1 ); - state->m_bPowerDown = false; state->m_currentPowerMode =DRX_POWER_DOWN ;
@@ -5819,9 +5814,10 @@ error:static int SwitchAntennaToQAM (struct drxk_state *state) { -int status = -EINVAL ; +int status =0 ;dprintk (1 ,"\n" ); +if (state->m_AntennaSwitchDVBTDVBC !=0 ) {if (state->m_GPIO != state->m_AntennaDVBC) { state->m_GPIO = state->m_AntennaDVBC;
@@ -5835,7 +5831,7 @@ static int SwitchAntennaToQAM(struct drxk_state *state)static int SwitchAntennaToDVBT (struct drxk_state *state) { -int status = -EINVAL ; +int status =0 ;dprintk (1 ,"\n" );if (state->m_AntennaSwitchDVBTDVBC !=0 ) {
@@ -6344,6 +6340,9 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, state->single_master = config->single_master; state->microcode_name = config->microcode_name; state->no_i2c_bridge = config->no_i2c_bridge; + state->m_AntennaSwitchDVBTDVBC = config->antenna_uses_gpio; + state->m_AntennaDVBC = config->antenna_dvbc; + state->m_AntennaDVBT = config->antenna_dvbt;mutex_init (&state->mutex);mutex_init (&state->ctlock);
drivers/media/dvb/frontends/drxk_hard.h +5 -4
@@ -321,16 +321,17 @@ struct drxk_state {u8 m_deviceSpin;u32 m_iqmRcRate; -u16 m_AntennaDVBC; -u16 m_AntennaDVBT; -u16 m_AntennaSwitchDVBTDVBC; -enum DRXPowerMode m_currentPowerMode;/* Configurable parameters at the driver */ +bool m_AntennaSwitchDVBTDVBC; +u16 m_AntennaDVBC; +u16 m_AntennaDVBT; + u32 single_master : 1; /* Use single master i2c mode */ u32 no_i2c_bridge : 1; /* Tuner is not on port 1, don't use I2C bridge */ +const char *microcode_name; };
Signature · 1 line
1.7.1
PATCH 16/21 drxk: Print detected configuration
In reply to a message not in the archiveDRX-K configuration is interesting when writing/testing new devices. Add an info line showing the discovered info.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +10 -0
@@ -905,6 +905,7 @@ static int GetDeviceCapabilities(struct drxk_state *state)u16 sioPdrOhwCfg =0 ;u32 sioTopJtagidLo =0 ;int status; +const char *spin ="" ;dprintk (1 ,"\n" );
@@ -954,12 +955,15 @@ static int GetDeviceCapabilities(struct drxk_state *state)switch ((sioTopJtagidLo >>29 ) &0xF ) {case 0 : state->m_deviceSpin =DRXK_SPIN_A1 ; + spin ="A1" ;break ;case 2 : state->m_deviceSpin =DRXK_SPIN_A2 ; + spin ="A2" ;break ;case 3 : state->m_deviceSpin =DRXK_SPIN_A3 ; + spin ="A3" ;break ;default : state->m_deviceSpin =DRXK_SPIN_UNKNOWN ;
@@ -1079,6 +1083,12 @@ static int GetDeviceCapabilities(struct drxk_state *state) goto error2; } +printk (KERN_INFO +"drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n" , + ((sioTopJtagidLo >>12 ) &0xFF ), spin, + state->m_oscClockFreq /1000 , + state->m_oscClockFreq %1000 ); + error:if (status <0 )printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__);
Signature · 1 line
1.7.1
PATCH 17/21 drxk: Improves the UIO handling
In reply to a message not in the archiveThe driver is too limited: it assumes that UIO is used only for controlling the antenna, and that only UIO-1 is in usage. However, from Terratec H7 driver [1], 3 UIO's can be used. In fact, it seems that H7 needs to use all 3. So, make the code generic enough to handle the most complex scenario. For now, only antena GPIO can be specified, but is is easier now to add the other GPIO/UIO needs.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk.h +8 -5
@@ -10,18 +10,21 @@* adr: I2C Address of the DRX-K * single_master: Device is on the single master mode * no_i2c_bridge: Don't switch the I2C bridge to talk with tuner -* antenna_uses_gpio: Use GPIO to control the antenna -* antenna_dvbc: GPIO for changing antenna to DVB-C -* antenna_dvbt: GPIO for changing antenna to DVB-T +* antenna_gpio: GPIO bit used to control the antenna +* antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1 +* means that 1=DVBC, 0 = DVBT. Zero means the opposite. * microcode_name: Name of the firmware file with the microcode +* +* On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is +* UIO-3. */ struct drxk_config {u8 adr;bool single_master;bool no_i2c_bridge; -bool antenna_uses_gpio; -u16 antenna_dvbc, antenna_dvbt; +bool antenna_dvbt; +u16 antenna_gpio;const char *microcode_name; };
drivers/media/dvb/frontends/drxk_hard.c +93 -30
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drivers/media/dvb/frontends/drxk_hard.h +9 -7
@@ -323,17 +323,19 @@ struct drxk_state {enum DRXPowerMode m_currentPowerMode; -/* Configurable parameters at the driver */ +/* +* Configurable parameters at the driver. They stores the values found +* at struct drxk_config. +*/ -bool m_AntennaSwitchDVBTDVBC; -u16 m_AntennaDVBC; -u16 m_AntennaDVBT; +u16 UIO_mask;/* Bits used by UIO */ - u32 single_master : 1; /* Use single master i2c mode */ - u32 no_i2c_bridge : 1; /* Tuner is not on port 1, don't use I2C bridge */ +bool single_master; +bool no_i2c_bridge; +bool antenna_dvbt; +u16 antenna_gpio;const char *microcode_name; - };#define NEVER_LOCK 0
Signature · 1 line
1.7.1
PATCH 18/21 drxk: Fix driver removal
In reply to a message not in the archiveSigned-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +12 -0
@@ -6431,6 +6431,18 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config,if (init_drxk (state) <0 ) goto error; *fe_t = &state->t_frontend; + +#ifdef CONFIG_MEDIA_ATTACH +/* +* HACK: As this function initializes both DVB-T and DVB-C fe symbols, +* and calling it twice would create the state twice, leading into +* memory leaks, the right way is to call it only once. However, dvb +* release functions will call symbol_put twice. So, the solution is to +* artificially increment the usage count, in order to allow the +* driver to be released. +*/ +symbol_get (drxk_attach); +#endif return &state->c_frontend; error:
Signature · 1 line
1.7.1
PATCH 19/21 drxk: Simplify the DVB-C set mode logic
In reply to a message not in the archiveSigned-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +81 -84
@@ -1806,57 +1806,59 @@ static int SetOperationMode(struct drxk_state *state,if (status <0 ) goto error; -if (state->m_OperationMode != oMode) { -switch (state->m_OperationMode) { -/* OM_NONE was added for start up */ -case OM_NONE : -break ; -case OM_DVBT : - status =MPEGTSStop (state); -if (status <0 ) - goto error; - status =PowerDownDVBT (state, true); -if (status <0 ) - goto error; - state->m_OperationMode =OM_NONE ; -break ; -case OM_QAM_ITU_A :/* fallthrough */ -case OM_QAM_ITU_C : - status =MPEGTSStop (state); -if (status <0 ) - goto error; - status =PowerDownQAM (state); -if (status <0 ) - goto error; - state->m_OperationMode =OM_NONE ; -break ; -case OM_QAM_ITU_B : -default : - status = -EINVAL ; +/* Device is already at the required mode */ +if (state->m_OperationMode == oMode) +return 0 ; + +switch (state->m_OperationMode) { +/* OM_NONE was added for start up */ +case OM_NONE : +break ; +case OM_DVBT : + status =MPEGTSStop (state); +if (status <0 ) + goto error; + status =PowerDownDVBT (state, true); +if (status <0 ) + goto error; + state->m_OperationMode =OM_NONE ; +break ; +case OM_QAM_ITU_A :/* fallthrough */ +case OM_QAM_ITU_C : + status =MPEGTSStop (state); +if (status <0 ) goto error; - } + status =PowerDownQAM (state); +if (status <0 ) + goto error; + state->m_OperationMode =OM_NONE ; +break ; +case OM_QAM_ITU_B : +default : + status = -EINVAL ; + goto error; + } -/* -Power up new standard -*/ -switch (oMode) { -case OM_DVBT : - state->m_OperationMode = oMode; - status =SetDVBTStandard (state, oMode); -if (status <0 ) - goto error; -break ; -case OM_QAM_ITU_A :/* fallthrough */ -case OM_QAM_ITU_C : - state->m_OperationMode = oMode; - status =SetQAMStandard (state, oMode); -if (status <0 ) - goto error; -break ; -case OM_QAM_ITU_B : -default : - status = -EINVAL ; - } +/* +Power up new standard +*/ +switch (oMode) { +case OM_DVBT : + state->m_OperationMode = oMode; + status =SetDVBTStandard (state, oMode); +if (status <0 ) + goto error; +break ; +case OM_QAM_ITU_A :/* fallthrough */ +case OM_QAM_ITU_C : + state->m_OperationMode = oMode; + status =SetQAMStandard (state, oMode); +if (status <0 ) + goto error; +break ; +case OM_QAM_ITU_B : +default : + status = -EINVAL ; } error:if (status <0 )
@@ -3086,35 +3088,28 @@ static int InitAGC(struct drxk_state *state, bool isDTV) clpCyclen =500 ; clpSumMax =1023 ; -if (IsQAM (state)) { -/* Standard specific settings */ - clpSumMin =8 ; - clpDirTo = (u16) -9 ; - clpCtrlMode =0 ; - snsSumMin =8 ; - snsDirTo = (u16) -9 ; - kiInnergainMin = (u16) -1030 ; - }else { - status = -EINVAL ; - goto error; - } -if (IsQAM (state)) { - ifIaccuHiTgtMax =0x2380 ; - ifIaccuHiTgt =0x2380 ; - ingainTgtMin =0x0511 ; - ingainTgt =0x0511 ; - ingainTgtMax =5119 ; - fastClpCtrlDelay = - state->m_qamIfAgcCfg.FastClipCtrlDelay; - }else { - ifIaccuHiTgtMax =0x1200 ; - ifIaccuHiTgt =0x1200 ; - ingainTgtMin =13424 ; - ingainTgt =13424 ; - ingainTgtMax =30000 ; - fastClpCtrlDelay = - state->m_dvbtIfAgcCfg.FastClipCtrlDelay; +/* AGCInit() not available for DVBT; init done in microcode */ +if (!IsQAM (state)) { +printk (KERN_ERR "drxk: %s: mode %d is not DVB-C\n" , __func__, state->m_OperationMode); +return -EINVAL ; } + +/* FIXME: Analog TV AGC require different settings */ + +/* Standard specific settings */ + clpSumMin =8 ; + clpDirTo = (u16) -9 ; + clpCtrlMode =0 ; + snsSumMin =8 ; + snsDirTo = (u16) -9 ; + kiInnergainMin = (u16) -1030 ; + ifIaccuHiTgtMax =0x2380 ; + ifIaccuHiTgt =0x2380 ; + ingainTgtMin =0x0511 ; + ingainTgt =0x0511 ; + ingainTgtMax =5119 ; + fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay; + status =write16 (state,SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A , fastClpCtrlDelay);if (status <0 ) goto error;
@@ -3238,13 +3233,13 @@ static int InitAGC(struct drxk_state *state, bool isDTV) status =read16 (state,SCU_RAM_AGC_KI__A , &data);if (status <0 ) goto error; -if (IsQAM (state)) { - data =0x0657 ; - data &= ~SCU_RAM_AGC_KI_RF__M ; - data |= (DRXK_KI_RAGC_QAM <<SCU_RAM_AGC_KI_RF__B ); - data &= ~SCU_RAM_AGC_KI_IF__M ; - data |= (DRXK_KI_IAGC_QAM <<SCU_RAM_AGC_KI_IF__B ); - } + + data =0x0657 ; + data &= ~SCU_RAM_AGC_KI_RF__M ; + data |= (DRXK_KI_RAGC_QAM <<SCU_RAM_AGC_KI_RF__B ); + data &= ~SCU_RAM_AGC_KI_IF__M ; + data |= (DRXK_KI_IAGC_QAM <<SCU_RAM_AGC_KI_IF__B ); + status =write16 (state,SCU_RAM_AGC_KI__A , data); error:if (status <0 )
@@ -5627,6 +5622,8 @@ static int SetQAMStandard(struct drxk_state *state,#undef DRXK_QAMA_TAPS_SELECT#endif +dprintk (1 ,"\n" ); +/* added antenna switch */ SwitchAntennaToQAM (state);
Signature · 1 line
1.7.1
PATCH 20/21 drxk: Improve the scu_command error message
In reply to a message not in the archiveNow, it outputs:
[10927.639641] drxk: SCU_RESULT_INVPAR while sending cmd 0x0203 with params: [10927.646283] drxk: 02 00 00 00 10 00 07 00 03 02 ..........
Better than ERROR -3. This happens with Terratec H5 firmware.
It adds 2 new error conditions, and something useful to track what the heck is that.
I suspect that the scu_command is dependent on the firmware revision.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +25 -18
@@ -1521,6 +1521,8 @@ static int scu_command(struct drxk_state *state,unsigned long end;u8 buffer[34 ];int cnt =0 , ii; +const char *p; +char errname[30 ];dprintk (1 ,"\n" );
@@ -1567,31 +1569,36 @@ static int scu_command(struct drxk_state *state,/* Check if an error was reported by SCU */ err = (s16 )result[0 ]; +if (err >=0 ) + goto error; -/* check a few fixed error codes */ -if (err ==SCU_RESULT_UNKSTD ) { -printk (KERN_ERR "drxk: SCU_RESULT_UNKSTD\n" ); - status = -EINVAL ; - goto error2; - }else if (err ==SCU_RESULT_UNKCMD ) { -printk (KERN_ERR "drxk: SCU_RESULT_UNKCMD\n" ); - status = -EINVAL ; - goto error2; - }else if (err <0 ) { -/* -* here it is assumed that a nagative result means -* error, and positive no error -*/ -printk (KERN_ERR "drxk: %s ERROR: %d\n" , __func__, err); - status = -EINVAL ; - goto error2; +/* check for the known error codes */ +switch (err) { +case SCU_RESULT_UNKCMD : + p ="SCU_RESULT_UNKCMD" ; +break ; +case SCU_RESULT_UNKSTD : + p ="SCU_RESULT_UNKSTD" ; +break ; +case SCU_RESULT_SIZE : + p ="SCU_RESULT_SIZE" ; +break ; +case SCU_RESULT_INVPAR : + p ="SCU_RESULT_INVPAR" ; +break ; +default :/* Other negative values are errors */ +sprintf (errname,"ERROR: %d\n" , err); + p = errname; } +printk (KERN_ERR "drxk: %s while sending cmd 0x%04x with params:" , p, cmd); +print_hex_dump_bytes ("drxk: " ,DUMP_PREFIX_NONE , buffer, cnt); + status = -EINVAL ; + goto error2; } error:if (status <0 )printk (KERN_ERR "drxk: Error %d on %s\n" , status, __func__); - error2:mutex_unlock (&state->mutex);return status;
drivers/media/dvb/frontends/drxk_hard.h +2 -0
@@ -20,6 +20,8 @@#define DRX_SCU_READY 0#define DRXK_MAX_WAITTIME (200)#define SCU_RESULT_OK 0 +#define SCU_RESULT_SIZE -4 +#define SCU_RESULT_INVPAR -3#define SCU_RESULT_UNKSTD -2#define SCU_RESULT_UNKCMD -1
Signature · 1 line
1.7.1
PATCH 21/21 drxk: Add a fallback method for QAM parameter setting
In reply to a message not in the archiveThe QAM standard is set using this scu_command:
SCU_RAM_COMMAND_STANDARD_QAM |
SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM
The driver implements a version that has 4 parameters, however, Terratec H5 needs to break this into two separate commands, otherwise, DVB-C doesn't work.
With this fix, scan is now properly working and getting the channel list:
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
tune to: 609000000:INVERSION_AUTO:5217000:FEC_3_4:QAM_256 tuning status ==
0x00
tuning status ==0x07
tuning status ==0x1f
0x0093 0x0026: pmt_pid 0x0758 (null) -- SporTV2 (running, scrambled) 0x0093 0x0027: pmt_pid 0x0748 (null) -- SporTV (running, scrambled) 0x0093 0x0036: pmt_pid 0x0768 (null) -- FX (running, scrambled) 0x0093 0x0052: pmt_pid 0x0788 (null) -- The History Channel (running, scrambled)
Signed-off-by Mauro Carvalho Chehab <[email protected]>
drivers/media/dvb/frontends/drxk_hard.c +17 -1
@@ -5389,7 +5389,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, {int status;u8 parameterLen; -u16 setEnvParameters[5 ]; +u16 setEnvParameters[5 ] = {0 ,0 ,0 ,0 ,0 };u16 setParamParameters[4 ] = {0 ,0 ,0 ,0 };u16 cmdResult;
@@ -5456,9 +5456,25 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, setParamParameters[1 ] =DRXK_QAM_I12_J17 ;/* interleave mode */ status =scu_command (state,SCU_RAM_COMMAND_STANDARD_QAM |SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM ,4 , setParamParameters,1 , &cmdResult); +if (status <0 ) { +/* Fall-back to the simpler call */ + setParamParameters[0 ] =QAM_TOP_ANNEX_A ; +if (state->m_OperationMode ==OM_QAM_ITU_C ) + setEnvParameters[0 ] =QAM_TOP_ANNEX_C ;/* Annex */ +else + setEnvParameters[0 ] =0 ; + + status =scu_command (state,SCU_RAM_COMMAND_STANDARD_QAM |SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV ,1 , setEnvParameters,1 , &cmdResult);if (status <0 ) goto error; + setParamParameters[0 ] = state->m_Constellation;/* constellation */ + setParamParameters[1 ] =DRXK_QAM_I12_J17 ;/* interleave mode */ + + status =scu_command (state,SCU_RAM_COMMAND_STANDARD_QAM |SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM ,2 , setParamParameters,1 , &cmdResult); + } +if (status <0 ) + goto error;/* STEP 3: enable the system in a mode where the ADC provides valid signal setup constellation independent registers */
Signature · 1 line
1.7.1