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OMAP DSS HWMOD fixes

PATCH New Paul Walmsley 2 participants 9 messages Aug 21, 2011 – Aug 23, 2011

Subsystems (5)
Arm (32-bit) Arm sub-architectures Framebuffer layer OMAP2+ support +1 more subsystems
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Paul Walmsley

author maintainer
#0 lore raw

v3 cover OMAP DSS HWMOD fixes

Just ensuring that this series is copied to lakml. The fifth patch has been revised slightly from Tomi's original posting. This series is targeted for 3.1-rc.

- Paul

Date: Mon, 8 Aug 2011 12:15:09 +0300
From: Tomi Valkeinen <[email protected]>
To: paul at pwsan.com, linux-omap at vger.kernel.org, b-cousson at ti.com
Cc: archit at ti.com, Tomi Valkeinen <[email protected]>
Subject: [PATCHv2 0/5] OMAP DSS HWMOD fixes

Second try with the DSS HWMODs

This set fixes the DSS clocks in HWMOD data, and implements a new reset mechanism for dss_core.

The new dss_reset function doesn't actually do a reset, it just enables all DSS clocks and waits for the reset to complete. This should be better approach than actually doing a reset, because:

OMAP4 - dss_core HW doesn't contain a SW reset bit so doing a reset is impossible. But after power-on we need to enable all DSS clocks and wait for the power-on reset to complete.

OMAP2/3 - dss_core does have a SW reset bit, but resetting dss_core also resets all the other DSS modules. This means that the other modules could be left uninitialized, as the hwmod code handles all modules independently, and in this case initializes only dss_core's registers. Thus dss_core's reset shouldn't be used, and we should only verify that the power-on reset has completed.

Tested on OMAP4 and OMAP3.

The first two HWMOD patches (for OMAP2/3) are not changed since v1.

Tomi

---

Tomi Valkeinen (5):
OMAP2xxx: HWMOD: fix DSS opt clocks
OMAP3: HWMOD: fix DSS opt clocks
OMAP4: HWMOD: fix DSS opt clocks OMAP2/3: HWMOD: Add SYSS_HAS_RESET_STATUS for dss
OMAP: HWMOD: Unify DSS resets for all OMAPs

 arch/arm/mach-omap2/Makefile                       |    5 +--
 arch/arm/mach-omap2/display.c                      |   35 ++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |   15 +++++++--
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |   15 +++++++--
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |    5 ++-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |   35 ++++++++++++++++++--
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |   18 +++-------
 arch/arm/plat-omap/include/plat/common.h           |    3 ++
 include/video/omapdss.h                            |    7 ----
 9 files changed, 106 insertions(+), 32 deletions(-)
author maintainer
#1 lore raw

PATCH v3 1/5 OMAP2xxx: HWMOD: fix DSS opt clocks

From: Tomi Valkeinen <[email protected]>

Set HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core to allow DSS reset properly.

Add missing ick opt-clock for rfbi. Rfbi uses the ick to calculate timings.

Fix the venc iclk and fclk.

Signed-off-by Tomi Valkeinen <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |   15 +++++++++++++--
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |   15 +++++++++++++--
 2 files changed, 26 insertions(+), 4 deletions(-)
arch/arm/mach-omap2/omap_hwmod_2420_data.c +13 -2
index a015c69..09d9395 100644
@@ -874,12 +874,17 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+	/*
+	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+	 * driver does not use these clocks.
+	 */
 	{ .role = "tv_clk", .clk = "dss_54m_fck" },
 	{ .role = "sys_clk", .clk = "dss2_fck" },
 };
 
 static struct omap_hwmod omap2420_dss_core_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_dss_hwmod_class,
 	.main_clk	= "dss1_fck", /* instead of dss_fck */
 	.sdma_reqs	= omap2xxx_dss_sdma_chs,

@@ -962,6 +967,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
 	&omap2420_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+	{ .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 	.name		= "dss_rfbi",
 	.class		= &omap2_rfbi_hwmod_class,

@@ -973,6 +982,8 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 			.module_offs = CORE_MOD,
 		},
 	},
+	.opt_clks	= dss_rfbi_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 	.slaves		= omap2420_dss_rfbi_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap2420_dss_rfbi_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

@@ -983,7 +994,7 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
 	.master		= &omap2420_l4_core_hwmod,
 	.slave		= &omap2420_dss_venc_hwmod,
-	.clk		= "dss_54m_fck",
+	.clk		= "dss_ick",
 	.addr		= omap2_dss_venc_addrs,
 	.fw = {
 		.omap2 = {

@@ -1003,7 +1014,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
 static struct omap_hwmod omap2420_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap2_venc_hwmod_class,
-	.main_clk	= "dss1_fck",
+	.main_clk	= "dss_54m_fck",
 	.prcm		= {
 		.omap2 = {
 			.prcm_reg_id = 1,
arch/arm/mach-omap2/omap_hwmod_2430_data.c +13 -2
index 16743c7..67aff19 100644
@@ -940,12 +940,17 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+	/*
+	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+	 * driver does not use these clocks.
+	 */
 	{ .role = "tv_clk", .clk = "dss_54m_fck" },
 	{ .role = "sys_clk", .clk = "dss2_fck" },
 };
 
 static struct omap_hwmod omap2430_dss_core_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_dss_hwmod_class,
 	.main_clk	= "dss1_fck", /* instead of dss_fck */
 	.sdma_reqs	= omap2xxx_dss_sdma_chs,

@@ -1016,6 +1021,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
 	&omap2430_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+	{ .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 	.name		= "dss_rfbi",
 	.class		= &omap2_rfbi_hwmod_class,

@@ -1027,6 +1036,8 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 			.module_offs = CORE_MOD,
 		},
 	},
+	.opt_clks	= dss_rfbi_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 	.slaves		= omap2430_dss_rfbi_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap2430_dss_rfbi_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),

@@ -1037,7 +1048,7 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
 	.master		= &omap2430_l4_core_hwmod,
 	.slave		= &omap2430_dss_venc_hwmod,
-	.clk		= "dss_54m_fck",
+	.clk		= "dss_ick",
 	.addr		= omap2_dss_venc_addrs,
 	.flags		= OCPIF_SWSUP_IDLE,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,

@@ -1051,7 +1062,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
 static struct omap_hwmod omap2430_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap2_venc_hwmod_class,
-	.main_clk	= "dss1_fck",
+	.main_clk	= "dss_54m_fck",
 	.prcm		= {
 		.omap2 = {
 			.prcm_reg_id = 1,
maintainer
#2 lore raw

PATCH 1/5 OMAP2xxx: HWMOD: fix DSS opt clocks

Quoted 4 lines · Paul Walmsley

From: Tomi Valkeinen <[email protected]>

Set HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core to allow DSS reset properly.

Can you please add what this fixes so this can be justified as a fix?

Quoted 2 lines

Add missing ick opt-clock for rfbi. Rfbi uses the ick to calculate timings.

Here too.

Quoted 1 line

Fix the venc iclk and fclk.

And here.

Regards,

Tony

maintainer
#3 lore raw

PATCH 1/5 OMAP2xxx: HWMOD: fix DSS opt clocks

Quoted 8 lines · Tony Lindgren
Quoted 4 lines · Paul Walmsley

From: Tomi Valkeinen <[email protected]>

Set HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core to allow DSS reset properly.

Can you please add what this fixes so this can be justified as a fix?

Quoted 8 lines
Quoted 2 lines

Add missing ick opt-clock for rfbi. Rfbi uses the ick to calculate timings.

Here too.

Quoted 1 line

Fix the venc iclk and fclk.

And here.

Looks like the comments for the whole series should be improved so it's clear to everybody what issues these fix and what caused the breakage.

Tony

author maintainer
#4 lore raw

PATCH v3 1/5 OMAP2xxx: HWMOD: fix DSS opt clocks

In reply to Tony Lindgren

Hi Tomi,

Quoted 8 lines · Tony Lindgren
Quoted 4 lines · Paul Walmsley

From: Tomi Valkeinen <[email protected]>

Set HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core to allow DSS reset properly.

Can you please add what this fixes so this can be justified as a fix?

Quoted 8 lines
Quoted 2 lines

Add missing ick opt-clock for rfbi. Rfbi uses the ick to calculate timings.

Here too.

Quoted 1 line

Fix the venc iclk and fclk.

And here.

Could you please update the patch changelogs per Tony's request?

thanks,

- Paul

author maintainer
#5 lore raw

PATCH v3 2/5 OMAP3: HWMOD: fix DSS opt clocks

In reply to Paul Walmsley

From: Tomi Valkeinen <[email protected]>

Set HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core to allow DSS reset properly.

Add missing dss_96m_fck, which is used by venc on OMAP3430.

Add missing ick and sys_clk for dsi.

Add missing ick for rfbi.

Signed-off-by Tomi Valkeinen <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   35 +++++++++++++++++++++++++---
 1 files changed, 31 insertions(+), 4 deletions(-)
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +31 -4
index 25bf43b..4a02cc3 100644
@@ -1365,13 +1365,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
 };
 
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-	{ .role = "tv_clk", .clk = "dss_tv_fck" },
-	{ .role = "video_clk", .clk = "dss_96m_fck" },
+	/*
+	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+	 * driver does not use these clocks.
+	 */
 	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
+	{ .role = "tv_clk", .clk = "dss_tv_fck" },
+	/* required only on OMAP3430 */
+	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 };
 
 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_dss_hwmod_class,
 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
 	.sdma_reqs	= omap3xxx_dss_sdma_chs,

@@ -1396,6 +1402,7 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 
 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_dss_hwmod_class,
 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
 	.sdma_reqs	= omap3xxx_dss_sdma_chs,

@@ -1488,6 +1495,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
 	.master		= &omap3xxx_l4_core_hwmod,
 	.slave		= &omap3xxx_dss_dsi1_hwmod,
+	.clk		= "dss_ick",
 	.addr		= omap3xxx_dss_dsi1_addrs,
 	.fw = {
 		.omap2 = {

@@ -1504,6 +1512,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
 	&omap3xxx_l4_core__dss_dsi1,
 };
 
+static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
+	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
+};
+
 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 	.name		= "dss_dsi1",
 	.class		= &omap3xxx_dsi_hwmod_class,

@@ -1516,6 +1528,8 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 			.module_offs = OMAP3430_DSS_MOD,
 		},
 	},
+	.opt_clks	= dss_dsi1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
 	.slaves		= omap3xxx_dss_dsi1_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |

@@ -1545,6 +1559,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
 	&omap3xxx_l4_core__dss_rfbi,
 };
 
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+	{ .role = "ick", .clk = "dss_ick" },
+};
+
 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 	.name		= "dss_rfbi",
 	.class		= &omap2_rfbi_hwmod_class,

@@ -1556,6 +1574,8 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 			.module_offs = OMAP3430_DSS_MOD,
 		},
 	},
+	.opt_clks	= dss_rfbi_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 	.slaves		= omap3xxx_dss_rfbi_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |

@@ -1568,7 +1588,7 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
 	.master		= &omap3xxx_l4_core_hwmod,
 	.slave		= &omap3xxx_dss_venc_hwmod,
-	.clk		= "dss_tv_fck",
+	.clk		= "dss_ick",
 	.addr		= omap2_dss_venc_addrs,
 	.fw = {
 		.omap2 = {

@@ -1586,10 +1606,15 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
 	&omap3xxx_l4_core__dss_venc,
 };
 
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+	/* required only on OMAP3430 */
+	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
+};
+
 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap2_venc_hwmod_class,
-	.main_clk	= "dss1_alwon_fck",
+	.main_clk	= "dss_tv_fck",
 	.prcm		= {
 		.omap2 = {
 			.prcm_reg_id = 1,

@@ -1597,6 +1622,8 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 			.module_offs = OMAP3430_DSS_MOD,
 		},
 	},
+	.opt_clks	= dss_venc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
 	.slaves		= omap3xxx_dss_venc_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_dss_venc_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
author maintainer
#6 lore raw

PATCH v3 3/5 OMAP4: HWMOD: fix DSS opt clocks

In reply to Paul Walmsley

From: Tomi Valkeinen <[email protected]>

Remove the extra dss_dss_clk from dss_core's opt-clocks. dss_dss_clk is the fck, and thus not an opt-clock.

Add HWMOD_CONTROL_OPT_CLKS_IN_RESET for dss_core so that dss_core's reset can finish.

Remove the opt clocks for dispc, as they are not needed.

Change the main_clk for hdmi and venc to dss_48mhz_clk and dss_tv_clk, respectively.

Cc Benoit Cousson <[email protected]>
Signed-off-by Tomi Valkeinen <[email protected]>
Acked-by Benoit Cousson <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   16 ++++------------
 1 files changed, 4 insertions(+), 12 deletions(-)
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +4 -12
index 6201422..8b74058 100644
@@ -1257,12 +1257,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 	{ .role = "tv_clk", .clk = "dss_tv_clk" },
-	{ .role = "dss_clk", .clk = "dss_dss_clk" },
-	{ .role = "video_clk", .clk = "dss_48mhz_clk" },
+	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 };
 
 static struct omap_hwmod omap44xx_dss_hwmod = {
 	.name		= "dss_core",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap44xx_dss_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
 	.main_clk	= "dss_dss_clk",

@@ -1358,12 +1358,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
 	&omap44xx_l4_per__dss_dispc,
 };
 
-static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
-	{ .role = "sys_clk", .clk = "dss_sys_clk" },
-	{ .role = "tv_clk", .clk = "dss_tv_clk" },
-	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 	.name		= "dss_dispc",
 	.class		= &omap44xx_dispc_hwmod_class,

@@ -1377,8 +1371,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 		},
 	},
-	.opt_clks	= dss_dispc_opt_clks,
-	.opt_clks_cnt	= ARRAY_SIZE(dss_dispc_opt_clks),
 	.slaves		= omap44xx_dss_dispc_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_slaves),
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

@@ -1645,7 +1637,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 	.clkdm_name	= "l3_dss_clkdm",
 	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
 	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
-	.main_clk	= "dss_dss_clk",
+	.main_clk	= "dss_48mhz_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,

@@ -1808,7 +1800,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 	.name		= "dss_venc",
 	.class		= &omap44xx_venc_hwmod_class,
 	.clkdm_name	= "l3_dss_clkdm",
-	.main_clk	= "dss_dss_clk",
+	.main_clk	= "dss_tv_clk",
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
author maintainer
#7 lore raw

PATCH v3 4/5 OMAP2/3: HWMOD: Add SYSS_HAS_RESET_STATUS for dss

In reply to Paul Walmsley

From: Tomi Valkeinen <[email protected]>

OMAP2/3 dss_core has a reset status flag in sysstatus register. Add SYSS_HAS_RESET_STATUS flag to HWMOD data so it can be used.

Signed-off-by Tomi Valkeinen <[email protected]>
Signed-off-by Paul Walmsley <[email protected]>
---
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +2 -1
index c451729..d78c132 100644
@@ -43,7 +43,8 @@ static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
 	.rev_offs	= 0x0000,
 	.sysc_offs	= 0x0010,
 	.syss_offs	= 0x0014,
-	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+			   SYSS_HAS_RESET_STATUS),
 	.sysc_fields	= &omap_hwmod_sysc_type1,
 };
author maintainer
#8 lore raw

PATCH v3 5/5 OMAP: HWMOD: Unify DSS resets for all OMAPs

In reply to Paul Walmsley

From: Tomi Valkeinen <[email protected]>

This patch adds a custom DSS reset function used on all OMAP's.

The function doesn't actually do a reset, it only waits for the reset to complete. The reason for this is that on OMAP4 there is no possibility to do a SW reset, and on OMAP2/3 doing a SW reset for dss_core resets all the other DSS modules also, thus breaking the HWMOD model where every DSS module is independent.

Signed-off-by Tomi Valkeinen <[email protected]>

[paul at pwsan.com: modified to build arch/arm/mach-omap2/display.o
unconditionally to avoid an error when !CONFIG_OMAP2_DSS]

Signed-off-by Paul Walmsley <[email protected]>
---
 arch/arm/mach-omap2/Makefile                       |    5 +--
 arch/arm/mach-omap2/display.c                      |   35 ++++++++++++++++++++
 .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c |    2 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    2 +
 arch/arm/plat-omap/include/plat/common.h           |    3 ++
 include/video/omapdss.h                            |    7 ----
 6 files changed, 43 insertions(+), 11 deletions(-)
arch/arm/mach-omap2/Makefile +1 -4
index f343365..bf85539 100644
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-	 common.o gpio.o dma.o wd_timer.o
+	 common.o gpio.o dma.o wd_timer.o display.o
 
 omap-2-3-common				= irq.o sdrc.o
 hwmod-common				= omap_hwmod.o \

@@ -276,7 +276,4 @@ smsc911x-$(CONFIG_SMSC911X)		:= gpmc-smsc911x.o
 obj-y					+= $(smsc911x-m) $(smsc911x-y)
 obj-$(CONFIG_ARCH_OMAP4)		+= hwspinlock.o
 
-disp-$(CONFIG_OMAP2_DSS)		:= display.o
-obj-y					+= $(disp-m) $(disp-y)
-
 obj-y					+= common-board-devices.o twl-common.o
arch/arm/mach-omap2/display.c +35 -0
index a5b7a23..cdb675a 100644
@@ -26,6 +26,7 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
+#include <plat/common.h>
 
 static struct platform_device omap_display_device = {
 	.name          = "omapdss",

@@ -126,3 +127,37 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
 
 	return r;
 }
+
+#define MAX_MODULE_SOFTRESET_WAIT	10000
+int omap_dss_reset(struct omap_hwmod *oh)
+{
+	struct omap_hwmod_opt_clk *oc;
+	int c = 0;
+	int i, r;
+
+	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
+		pr_err("dss_core: hwmod data doesn't contain reset data\n");
+		return -EINVAL;
+	}
+
+	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+		if (oc->_clk)
+			clk_enable(oc->_clk);
+
+	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
+				& SYSS_RESETDONE_MASK),
+			MAX_MODULE_SOFTRESET_WAIT, c);
+
+	if (c == MAX_MODULE_SOFTRESET_WAIT)
+		pr_warning("dss_core: waiting for reset to finish failed\n");
+	else
+		pr_debug("dss_core: softreset done\n");
+
+	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+		if (oc->_clk)
+			clk_disable(oc->_clk);
+
+	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
+
+	return r;
+}
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +2 -0
index d78c132..c11273d 100644
@@ -11,6 +11,7 @@
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
 #include <plat/dma.h>
+#include <plat/common.h>
 
 #include <mach/irqs.h>
 

@@ -51,6 +52,7 @@ static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
 struct omap_hwmod_class omap2_dss_hwmod_class = {
 	.name	= "dss",
 	.sysc	= &omap2_dss_sysc,
+	.reset	= omap_dss_reset,
 };
 
 /*
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +2 -0
index 8b74058..7a7489e 100644
@@ -29,6 +29,7 @@
 #include <plat/mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/i2c.h>
+#include <plat/common.h>
 
 #include "omap_hwmod_common_data.h"
 

@@ -1204,6 +1205,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 	.name	= "dss",
 	.sysc	= &omap44xx_dss_sysc,
+	.reset	= omap_dss_reset,
 };
 
 /* dss */
arch/arm/plat-omap/include/plat/common.h +3 -0
index 4564cc6..a822685 100644
@@ -30,6 +30,7 @@
 #include <linux/delay.h>
 
 #include <plat/i2c.h>
+#include <plat/omap_hwmod.h>
 
 struct sys_timer;
 

@@ -45,6 +46,8 @@ extern unsigned long long notrace omap_32k_sched_clock(void);
 
 extern void omap_reserve(void);
 
+extern int omap_dss_reset(struct omap_hwmod *);
+
 /*
  * IO bases for various OMAP processors
  * Except the tap base, rest all the io bases
include/video/omapdss.h +0 -7
index 3b55ef2..105b05d 100644
@@ -245,15 +245,8 @@ struct omap_dss_board_info {
 	void (*dsi_mux_pads)(bool enable);
 };
 
-#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
 /* Init with the board info */
 extern int omap_display_init(struct omap_dss_board_info *board_data);
-#else
-static inline int omap_display_init(struct omap_dss_board_info *board_data)
-{
-	return 0;
-}
-#endif
 
 struct omap_display_platform_data {
 	struct omap_dss_board_info *board_data;