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at91: add Atmel ISI and ov2640 support on m10/g45 board.

PATCH New Josh Wu 2 participants 4 messages Sep 2, 2011 – Sep 6, 2011

Subsystems (4)
Arm (32-bit) Media (V4L/DVB) Arm sub-architectures Arm/Microchip (AT91) SoC support
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Josh Wu

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#0 lore raw

PATCH 1/1 at91: add Atmel ISI and ov2640 support on m10/g45 board.

AT91: m10/g45: add Atmel ISI device and OV2640 on board.

Signed-off-by Josh Wu <[email protected]>
---
 arch/arm/mach-at91/at91sam9g45_devices.c |   66 ++++++++++++++++++++
 arch/arm/mach-at91/board-sam9m10g45ek.c  |   97 ++++++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/board.h  |    3 +-
 3 files changed, 165 insertions(+), 1 deletions(-)
arch/arm/mach-at91/at91sam9g45_devices.c +66 -0
index 1e8f275..ea9a161 100644
@@ -28,6 +28,8 @@
 #include <mach/at_hdmac.h>
 #include <mach/atmel-mci.h>
 
+#include <media/atmel-isi.h>
+
 #include "generic.h"
 
 

@@ -872,6 +874,70 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 #endif
 
+/* --------------------------------------------------------------------
+ *  Image Sensor Interface
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
+static u64 isi_dmamask = DMA_BIT_MASK(32);
+static struct isi_platform_data isi_data;
+
+struct resource isi_resources[] = {
+	[0] = {
+		.start	= AT91SAM9G45_BASE_ISI,
+		.end	= AT91SAM9G45_BASE_ISI + SZ_16K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= AT91SAM9G45_ID_ISI,
+		.end	= AT91SAM9G45_ID_ISI,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device at91sam9g45_isi_device = {
+	.name		= "atmel_isi",
+	.id		= 0,
+	.dev		= {
+			.dma_mask		= &isi_dmamask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+			.platform_data		= &isi_data,
+	},
+	.resource	= isi_resources,
+	.num_resources	= ARRAY_SIZE(isi_resources),
+};
+
+void __init at91_add_device_isi(struct isi_platform_data * data)
+{
+	struct platform_device *pdev;
+
+	if (!data)
+		return;
+	isi_data = *data;
+
+	at91_set_A_periph(AT91_PIN_PB20, 0);	/* ISI_D0 */
+	at91_set_A_periph(AT91_PIN_PB21, 0);	/* ISI_D1 */
+	at91_set_A_periph(AT91_PIN_PB22, 0);	/* ISI_D2 */
+	at91_set_A_periph(AT91_PIN_PB23, 0);	/* ISI_D3 */
+	at91_set_A_periph(AT91_PIN_PB24, 0);	/* ISI_D4 */
+	at91_set_A_periph(AT91_PIN_PB25, 0);	/* ISI_D5 */
+	at91_set_A_periph(AT91_PIN_PB26, 0);	/* ISI_D6 */
+	at91_set_A_periph(AT91_PIN_PB27, 0);	/* ISI_D7 */
+	at91_set_A_periph(AT91_PIN_PB28, 0);	/* ISI_PCK */
+	at91_set_A_periph(AT91_PIN_PB30, 0);	/* ISI_HSYNC */
+	at91_set_A_periph(AT91_PIN_PB29, 0);	/* ISI_VSYNC */
+	at91_set_B_periph(AT91_PIN_PB31, 0);	/* ISI_MCK (PCK1) */
+	at91_set_B_periph(AT91_PIN_PB8, 0);	/* ISI_PD8 */
+	at91_set_B_periph(AT91_PIN_PB9, 0);	/* ISI_PD9 */
+	at91_set_B_periph(AT91_PIN_PB10, 0);	/* ISI_PD10 */
+	at91_set_B_periph(AT91_PIN_PB11, 0);	/* ISI_PD11 */
+
+	pdev = &at91sam9g45_isi_device;
+	platform_device_register(pdev);
+}
+#else
+void __init at91_add_device_isi(struct isi_platform_data * data) { }
+#endif
+
 
 /* --------------------------------------------------------------------
  *  LCD Controller
arch/arm/mach-at91/board-sam9m10g45ek.c +97 -0

118 lines not on this page · raw message

arch/arm/mach-at91/include/mach/board.h +2 -1
index 2b499eb..099c4f7 100644
@@ -182,7 +182,8 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
 
  /* ISI */
-extern void __init at91_add_device_isi(void);
+struct isi_platform_data;
+extern void __init at91_add_device_isi(struct isi_platform_data *data);
 
  /* Touchscreen Controller */
 struct at91_tsadcc_data {
Signature · 1 line
1.6.3.3
#1 lore raw

PATCH 1/1 at91: add Atmel ISI and ov2640 support on m10/g45 board.

Quoted 24 lines

#include <asm/setup.h>
#include <asm/mach-types.h>

arch/arm/mach-at91/board-sam9m10g45ek.c +17 -0
@@ -194,6 +197,95 @@ static void __init ek_add_device_nand(void)
 	at91_add_device_nand(&ek_nand_data);
 }
 
+/*
+ *  ISI
+ */
+#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
+static struct isi_platform_data __initdata isi_data = {
+	.frate		= ISI_CFG1_FRATE_CAPTURE_ALL,
+	.has_emb_sync	= 0,
+	.emb_crc_sync = 0,
+	.hsync_act_low = 0,
+	.vsync_act_low = 0,
+	.pclk_act_falling = 0,
+	/* to use codec and preview path simultaneously */
+	.isi_full_mode = 1,
+	.data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
+};
+
+static void __init isi_set_clk(void)

arch/arm/mach-at91/board-sam9m10g45ek.c static void __init ek_add_device_nand(void) · line 226

Quoted 10 lines
arch/arm/mach-at91/board-sam9m10g45ek.c +10 -0
+{
+	struct clk *pck1;
+	struct clk *plla;
+
+	pck1 = clk_get(NULL, "pck1");
+	plla = clk_get(NULL, "plla");
+
+	clk_set_parent(pck1, plla);
+	clk_set_rate(pck1, 25000000);
+	clk_enable(pck1);

you must not enable the clock always

you must enable it just when you need it

and manage the clock at the board level really so so

Best Regards,
J.

author
#2 lore raw

PATCH 1/1 at91: add Atmel ISI and ov2640 support on m10/g45 board.

Quoted 37 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 24 lines

#include <asm/setup.h>
#include <asm/mach-types.h>

arch/arm/mach-at91/board-sam9m10g45ek.c +17 -0
@@ -194,6 +197,95 @@ static void __init ek_add_device_nand(void)
 	at91_add_device_nand(&ek_nand_data);
 }
 
+/*
+ *  ISI
+ */
+#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
+static struct isi_platform_data __initdata isi_data = {
+	.frate		= ISI_CFG1_FRATE_CAPTURE_ALL,
+	.has_emb_sync	= 0,
+	.emb_crc_sync = 0,
+	.hsync_act_low = 0,
+	.vsync_act_low = 0,
+	.pclk_act_falling = 0,
+	/* to use codec and preview path simultaneously */
+	.isi_full_mode = 1,
+	.data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
+};
+
+static void __init isi_set_clk(void)

arch/arm/mach-at91/board-sam9m10g45ek.c static void __init ek_add_device_nand(void) · line 226

Quoted 10 lines
arch/arm/mach-at91/board-sam9m10g45ek.c +10 -0
+{
+	struct clk *pck1;
+	struct clk *plla;
+
+	pck1 = clk_get(NULL, "pck1");
+	plla = clk_get(NULL, "plla");
+
+	clk_set_parent(pck1, plla);
+	clk_set_rate(pck1, 25000000);
+	clk_enable(pck1);

you must not enable the clock always

Quoted 3 lines

you must enable it just when you need it

and manage the clock at the board level really so so

I see, I will move such clock code to atmel_isi.c driver and add clock name, clock frequence to isi_platform_data structure in next version.

Thanks.
Best Regards,
Josh Wu

Quoted 2 lines

Best Regards,
J.

#3 lore raw

PATCH 1/1 at91: add Atmel ISI and ov2640 support on m10/g45 board.

Quoted 41 lines · Josh
Quoted 36 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 24 lines

#include <asm/setup.h>
#include <asm/mach-types.h>

arch/arm/mach-at91/board-sam9m10g45ek.c +17 -0
@@ -194,6 +197,95 @@ static void __init ek_add_device_nand(void)
 	at91_add_device_nand(&ek_nand_data);
 }
 
+/*
+ *  ISI
+ */
+#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
+static struct isi_platform_data __initdata isi_data = {
+	.frate		= ISI_CFG1_FRATE_CAPTURE_ALL,
+	.has_emb_sync	= 0,
+	.emb_crc_sync = 0,
+	.hsync_act_low = 0,
+	.vsync_act_low = 0,
+	.pclk_act_falling = 0,
+	/* to use codec and preview path simultaneously */
+	.isi_full_mode = 1,
+	.data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
+};
+
+static void __init isi_set_clk(void)

arch/arm/mach-at91/board-sam9m10g45ek.c static void __init ek_add_device_nand(void) · line 226

Quoted 10 lines
arch/arm/mach-at91/board-sam9m10g45ek.c +10 -0
+{
+	struct clk *pck1;
+	struct clk *plla;
+
+	pck1 = clk_get(NULL, "pck1");
+	plla = clk_get(NULL, "plla");
+
+	clk_set_parent(pck1, plla);
+	clk_set_rate(pck1, 25000000);
+	clk_enable(pck1);

you must not enable the clock always

Quoted 5 lines
Quoted 3 lines

you must enable it just when you need it

and manage the clock at the board level really so so

I see, I will move such clock code to atmel_isi.c driver and add clock name, clock frequence to isi_platform_data structure in next version.

no you miss the idea bind the clkdev

you manage the clock at soc level and then only if it's mandatory at board level

for the clock rate you pass it to the driver

and let the driver manage when it want to enable/disable the clock

the driver need to have a abtraction of the clock constraint and just request it and use it

Best Regards,
J.