tegra2: Enable data cache

board/nvidia/common/board.c +0 -0

@@ -307,3 +307,11 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 	return 0;

Quoted 7 lines · On Thursday, September 08, 2011 18:20:16 Simon Glass wrote:

board/nvidia/common/board.c +0 -0

@@ -307,3 +307,11 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 
 	return 0;
 
 }

board/nvidia/common/board.c int board_mmc_getcd(u8 *cd, struct mmc *mmc) · line 317

Quoted 10 lines

board/nvidia/common/board.c +8 -0

 #endif
 
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif

not specific to your patch, but this seems kind of dumb to copy & paste the same thing between all the arm sub arches/boards. why cant the default enable_caches() look like this for arm:
void enable_caches(void)
{

#ifndef CONFIG_SYS_DCACHE_OFF
	dcache_enable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
	icache_enable();

#endif
}
-mike

Quoted 24 lines · Mike Frysinger

Quoted 9 lines · On Thursday, September 08, 2011 18:20:16 Simon Glass wrote:

board/nvidia/common/board.c +0 -0

@@ -307,3 +307,11 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 
 ? ? return 0;
 

?}
?#endif

board/nvidia/common/board.c int board_mmc_getcd(u8 *cd, struct mmc *mmc) · line 317

Quoted 8 lines

board/nvidia/common/board.c +8 -0

+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ ? /* Enable D-cache. I-cache is already enabled in start.S */
+ ? dcache_enable();
+}
+#endif

not specific to your patch, but this seems kind of dumb to copy & paste the same thing between all the arm sub arches/boards. ?why cant the default enable_caches() look like this for arm:
void enable_caches(void)
{

Quoted 8 lines

#ifndef CONFIG_SYS_DCACHE_OFF
? ? ? dcache_enable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
? ? ? icache_enable();
#endif
}
-mike

Makes sense ... and also, we won't eventually need this "enable_caches()" at all in cpu-directories. It can then be moved to lib/.

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Quoted 4 lines · On Thursday, September 08, 2011 18:20:16 Simon Glass wrote:

board/nvidia/common/board.c +0 -0

@@ -307,3 +307,11 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 	return 0;

board/nvidia/common/board.c int board_mmc_getcd(u8 *cd, struct mmc *mmc) · line 317

Quoted 10 lines

board/nvidia/common/board.c +8 -0

 }
 #endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif

not specific to your patch, but this seems kind of dumb to copy & paste the same thing between all the arm sub arches/boards. why cant the default enable_caches() look like this for arm:
void enable_caches(void)
{

#ifndef CONFIG_SYS_DCACHE_OFF
	dcache_enable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
	icache_enable();

#endif
}

Quoted 4 lines

not specific to your patch, but this seems kind of dumb to copy & paste the same thing between all the arm sub arches/boards. ?why cant the default enable_caches() look like this for arm:
void enable_caches(void)

Quoted 8 lines

{
#ifndef CONFIG_SYS_DCACHE_OFF
? ? ? dcache_enable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
? ? ? icache_enable();
#endif
}

That was how it was earlier. But then many boards were not cache ready and still didn't define CONFIG_SYS_DCACHE_OFF, so they were broken. So, the current situation is that the absence of CONFIG_SYS_DCACHE_OFF doesn't mean that the board is cache-ready.

I like the suggestion made by Jason Liu, that of using CONFIG_SYS_DCACHE_ON instead. In the present situation ARM cpus that properly support cache handling seems to be in the minority, so CONFIG_SYS_DCACHE_ON may be more appropriate. But Wolfgang doesn't seem to like this.

best regards,
Aneesh

Quoted 18 lines · Aneesh V

Quoted 5 lines

not specific to your patch, but this seems kind of dumb to copy & paste the same thing between all the arm sub arches/boards. why cant the default enable_caches() look like this for arm:
void enable_caches(void)
{

Quoted 7 lines

#ifndef CONFIG_SYS_DCACHE_OFF
      dcache_enable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
      icache_enable();

#endif
}

That was how it was earlier. But then many boards were not cache ready and still didn't define CONFIG_SYS_DCACHE_OFF, so they were broken. So, the current situation is that the absence of CONFIG_SYS_DCACHE_OFF doesn't mean that the board is cache-ready.

Quoted 5 lines

I like the suggestion made by Jason Liu, that of using CONFIG_SYS_DCACHE_ON instead. In the present situation ARM cpus that properly support cache handling seems to be in the minority, so CONFIG_SYS_DCACHE_ON may be more appropriate. But Wolfgang doesn't seem to like this.

My concern with this is that the situation will never improve. At least this way there will be an incentive to sort things out, since one day the cache enable code will be in arch/arm/lib/board.c. I hope it is soon, but it will need more driver support first.

Quoted 25 lines · Aneesh V

Quoted 18 lines

Quoted 5 lines

not specific to your patch, but this seems kind of dumb to copy& paste the same thing between all the arm sub arches/boards. why cant the default enable_caches() look like this for arm:
void enable_caches(void)
{

Quoted 7 lines

#ifndef CONFIG_SYS_DCACHE_OFF
       dcache_enable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
       icache_enable();

#endif
}

That was how it was earlier. But then many boards were not cache ready and still didn't define CONFIG_SYS_DCACHE_OFF, so they were broken. So, the current situation is that the absence of CONFIG_SYS_DCACHE_OFF doesn't mean that the board is cache-ready.

Quoted 5 lines

I like the suggestion made by Jason Liu, that of using CONFIG_SYS_DCACHE_ON instead. In the present situation ARM cpus that properly support cache handling seems to be in the minority, so CONFIG_SYS_DCACHE_ON may be more appropriate. But Wolfgang doesn't seem to like this.

Quoted 4 lines

My concern with this is that the situation will never improve. At least this way there will be an incentive to sort things out, since one day the cache enable code will be in arch/arm/lib/board.c. I hope it is soon, but it will need more driver support first.

right ... this sounds like the sort of thing that takes much longer than it should. i'm not the arm maintainer, but it seems like it'd have been better to add CONFIG_SYS_{I,D}CACHE_OFF to all the arm board configs and leave it up to the maintainers to turn off. then there'd be no duplication in core code and no long term migration need.

until that happens, CONFIG_SYS_{D,I}CACHE_ON sounds like a reasonable way to get things back under control.

-mike

Le 15/09/2011 05:03, Mike Frysinger a ?crit :

Quoted 31 lines · On Wednesday, September 14, 2011 11:13:40 Simon Glass wrote:

Quoted 25 lines · Aneesh V

Quoted 18 lines

Quoted 5 lines

not specific to your patch, but this seems kind of dumb to copy& paste the same thing between all the arm sub arches/boards. why cant the default enable_caches() look like this for arm:
void enable_caches(void)
{

Quoted 7 lines

#ifndef CONFIG_SYS_DCACHE_OFF
       dcache_enable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
       icache_enable();

#endif
}

That was how it was earlier. But then many boards were not cache ready and still didn't define CONFIG_SYS_DCACHE_OFF, so they were broken. So, the current situation is that the absence of CONFIG_SYS_DCACHE_OFF doesn't mean that the board is cache-ready.

Quoted 5 lines

I like the suggestion made by Jason Liu, that of using CONFIG_SYS_DCACHE_ON instead. In the present situation ARM cpus that properly support cache handling seems to be in the minority, so CONFIG_SYS_DCACHE_ON may be more appropriate. But Wolfgang doesn't seem to like this.

Quoted 4 lines

My concern with this is that the situation will never improve. At least this way there will be an incentive to sort things out, since one day the cache enable code will be in arch/arm/lib/board.c. I hope it is soon, but it will need more driver support first.

Quoted 5 lines

right ... this sounds like the sort of thing that takes much longer than it should. i'm not the arm maintainer, but it seems like it'd have been better to add CONFIG_SYS_{I,D}CACHE_OFF to all the arm board configs and leave it up to the maintainers to turn off. then there'd be no duplication in core code and no long term migration need.

Actually, the idea was rather to have the config options control whether the code for caches is compiled or not, and the default code for caches does nothing but emit a warning on the console, thereby persistently nagging board msaintainers and developers to fix the issue -- whereas adding CACHE_OFF on config files would not cause any message and may cause the board to remain with caches off for as long as nobody complains enough.

Quoted 2 lines

until that happens, CONFIG_SYS_{D,I}CACHE_ON sounds like a reasonable way to get things back under control.

Nak. The right way is to make sure we have an ARM-wide default implementation (in arch/arm/lib) that does nothing and warns on the console about caches NOT being actually enabled, and cpu or SoC implementations (e.g. in arch/arm/cpu/arm926ejs) that actually enable caches on hardware on which it works.

Quoted 38 lines

Le 15/09/2011 05:03, Mike Frysinger a ?crit :

Quoted 31 lines · On Wednesday, September 14, 2011 11:13:40 Simon Glass wrote:

Quoted 25 lines · Aneesh V

Quoted 18 lines

Quoted 5 lines

not specific to your patch, but this seems kind of dumb to copy& paste the same thing between all the arm sub arches/boards. why cant the default enable_caches() look like this for arm:
void enable_caches(void)
{

Quoted 7 lines

#ifndef CONFIG_SYS_DCACHE_OFF
        dcache_enable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
        icache_enable();

#endif
}

That was how it was earlier. But then many boards were not cache ready and still didn't define CONFIG_SYS_DCACHE_OFF, so they were broken. So, the current situation is that the absence of CONFIG_SYS_DCACHE_OFF doesn't mean that the board is cache-ready.

Quoted 5 lines

I like the suggestion made by Jason Liu, that of using CONFIG_SYS_DCACHE_ON instead. In the present situation ARM cpus that properly support cache handling seems to be in the minority, so CONFIG_SYS_DCACHE_ON may be more appropriate. But Wolfgang doesn't seem to like this.

Quoted 4 lines

My concern with this is that the situation will never improve. At least this way there will be an incentive to sort things out, since one day the cache enable code will be in arch/arm/lib/board.c. I hope it is soon, but it will need more driver support first.

Quoted 5 lines

right ... this sounds like the sort of thing that takes much longer than it should. i'm not the arm maintainer, but it seems like it'd have been better to add CONFIG_SYS_{I,D}CACHE_OFF to all the arm board configs and leave it up to the maintainers to turn off. then there'd be no duplication in core code and no long term migration need.

Quoted 7 lines

Actually, the idea was rather to have the config options control whether the code for caches is compiled or not, and the default code for caches does nothing but emit a warning on the console, thereby persistently nagging board msaintainers and developers to fix the issue -- whereas adding CACHE_OFF on config files would not cause any message and may cause the board to remain with caches off for as long as nobody complains enough.

runtime warnings are useful only if someone actually executes that code. build time warnings however are much more prominent.

Quoted 8 lines

Quoted 2 lines

until that happens, CONFIG_SYS_{D,I}CACHE_ON sounds like a reasonable way to get things back under control.

Nak. The right way is to make sure we have an ARM-wide default implementation (in arch/arm/lib) that does nothing and warns on the console about caches NOT being actually enabled, and cpu or SoC implementations (e.g. in arch/arm/cpu/arm926ejs) that actually enable caches on hardware on which it works.

and now we're forced to copy& paste the same chunk of code everywhere for people who went through the effort to make things work. caches not working is a matter of the software not handling it, not the hardware being incapable of supporting things.

the state of arm systems not supporting cache should be considered legacy cruft, not the default starting state. when people add new SoC's, they should be defaulting to using cache, and if they dont want it, they have to manually add to their board configs "turn it off".

-mike

I agree on the need and interest to support cache. I disagree on the way to get there. Turning cache off indiscriminately and hoping that board developers/maintainer turn their caches off will only lead to U-Boot failing in interesting ways and cluttering the mailing list with requests for help until someone figures out the cache is the culprit.

We have started outlining a solution (weak generic cache (non-)functions in arch/arm/lib/cache.c which only warn about cache not being enabled, and cpu/SoC/board specific versions that enable cache where it works.

We also have started discussing minimizing cache code copy -- admittedly spinned off a patch submission discussion, so it may have been missed, and I will repost the RFC in its own thread -- whereby the cache functions would be defined as weak function in the lib, and could be overriden by ISA-level function, which themselves could be overriden by CPU-level functions, and SoC (or even board) level functions could override them all.

Quoted 5 lines · On Thursday, September 15, 2011 13:30:09 Albert ARIBAUD wrote:

I agree on the need and interest to support cache. I disagree on the way to get there. Turning cache off indiscriminately and hoping that board developers/maintainer turn their caches off will only lead to U-Boot failing in interesting ways and cluttering the mailing list with requests for help until someone figures out the cache is the culprit.

if code only works when cache is turned on, that usually means the code is broken and is missing appropriate barriers/flushes. ?turning cache on doesnt fix the underlying issue, it ignores it. ?ive seen this in the past with Blackfin parts where our testers will do some operation with caches on, and then try things with caches off, and trigger bugs in drivers due to missing syncs but things work due to implicit timings with cache on.

Quoted 3 lines

We have started outlining a solution (weak generic cache (non-)functions in arch/arm/lib/cache.c which only warn about cache not being enabled, and cpu/SoC/board specific versions that enable cache where it works.

which is causing the copy & paste i'm whining about

Quoted 7 lines

We also have started discussing minimizing cache code copy -- admittedly spinned off a patch submission discussion, so it may have been missed, and I will repost the RFC in its own thread -- whereby the cache functions ?would be defined as weak function in the lib, and could be overriden by ISA-level function, which themselves could be overriden by CPU-level functions, and SoC (or even board) level functions could override them all.

i guess i did miss it. ?it doesnt matter to me how we get to the ultimate destination ({I,D}CACHE_ON/etc...), just that ultimately the crappy/dead SoC's are not bogging down the modern/maintained ones by forcing the common implementation to suck.
-mike