Fix compile when MIPS_DEBUG_DISAS is defined.
PATCH 1/1 Fix compile when MIPS_DEBUG_DISAS is defined.
When MIPS_DEBUG_DISAS is defined the gen_logic_imm, gen_slt_imm, gen_cond_move, gen_logic and gen_slt functions cause errors because ctx is not defined. Fixed the functions by passing in the DisasContext.
Signed-off-by Eric Johnson <[email protected]>
--- target-mips/translate.c | 72 +++++++++++++++++++++++++--------------------- 1 files changed, 39 insertions(+), 33 deletions(-)
This patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641.
target-mips/translate.c +44 -33
@@ -1420,7 +1420,8 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, }/* Logic with immediate operand */ -static void gen_logic_imm (CPUState *env,uint32_t opc,int rt,int rs,int16_t imm) +static void gen_logic_imm (CPUState *env,DisasContext *ctx,uint32_t opc, +int rt,int rs,int16_t imm) {target_ulong uimm;const char *opn ="imm logic" ;
@@ -1463,7 +1464,8 @@ static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t }/* Set on less than with immediate operand */ -static void gen_slt_imm (CPUState *env,uint32_t opc,int rt,int rs,int16_t imm) +static void gen_slt_imm (CPUState *env,DisasContext *ctx,uint32_t opc, +int rt,int rs,int16_t imm) {target_ulong uimm = (target_long )imm;/* Sign extend to 32/64 bits */ const char *opn ="imm arith" ;
@@ -1764,7 +1766,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, }/* Conditional move */ -static void gen_cond_move (CPUState *env,uint32_t opc,int rd,int rs,int rt) +static void gen_cond_move (CPUState *env,DisasContext *ctx,uint32_t opc, +int rd,int rs,int rt) {const char *opn ="cond move" ;int l1;
@@ -1802,7 +1805,8 @@ static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt) }/* Logic */ -static void gen_logic (CPUState *env,uint32_t opc,int rd,int rs,int rt) +static void gen_logic (CPUState *env,DisasContext *ctx,uint32_t opc,int rd, +int rs,int rt) {const char *opn ="logic" ;
@@ -1863,7 +1867,8 @@ static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt) }/* Set on lower than */ -static void gen_slt (CPUState *env,uint32_t opc,int rd,int rs,int rt) +static void gen_slt (CPUState *env,DisasContext *ctx,uint32_t opc,int rd, +int rs,int rt) {const char *opn ="slt" ;TCGv t0, t1;
@@ -8763,10 +8768,10 @@ static int decode_extended_mips16_opc (CPUState *env, DisasContext *ctx,gen_arith_imm (env, ctx,OPC_ADDIU , rx, rx, imm);break ;case M16_OPC_SLTI : -gen_slt_imm (env,OPC_SLTI ,24 , rx, imm); +gen_slt_imm (env, ctx,OPC_SLTI ,24 , rx, imm);break ;case M16_OPC_SLTIU : -gen_slt_imm (env,OPC_SLTIU ,24 , rx, imm); +gen_slt_imm (env, ctx,OPC_SLTIU ,24 , rx, imm);break ;case M16_OPC_I8 :switch (funct) {
@@ -8978,14 +8983,14 @@ static int decode_mips16_opc (CPUState *env, DisasContext *ctx, {int16_t imm = (uint8_t ) ctx->opcode; -gen_slt_imm (env,OPC_SLTI ,24 , rx, imm); +gen_slt_imm (env, ctx,OPC_SLTI ,24 , rx, imm); }break ;case M16_OPC_SLTIU : {int16_t imm = (uint8_t ) ctx->opcode; -gen_slt_imm (env,OPC_SLTIU ,24 , rx, imm); +gen_slt_imm (env, ctx,OPC_SLTIU ,24 , rx, imm); }break ;case M16_OPC_I8 :
@@ -9061,7 +9066,7 @@ static int decode_mips16_opc (CPUState *env, DisasContext *ctx, {int16_t imm = (uint8_t ) ctx->opcode; -gen_logic_imm (env,OPC_XORI ,24 , rx, imm); +gen_logic_imm (env, ctx,OPC_XORI ,24 , rx, imm); }break ;#if defined(TARGET_MIPS64 )
@@ -9173,10 +9178,10 @@ static int decode_mips16_opc (CPUState *env, DisasContext *ctx, }break ;case RR_SLT : -gen_slt (env,OPC_SLT ,24 , rx, ry); +gen_slt (env, ctx,OPC_SLT ,24 , rx, ry);break ;case RR_SLTU : -gen_slt (env,OPC_SLTU ,24 , rx, ry); +gen_slt (env, ctx,OPC_SLTU ,24 , rx, ry);break ;case RR_BREAK :generate_exception (ctx,EXCP_BREAK );
@@ -9197,22 +9202,22 @@ static int decode_mips16_opc (CPUState *env, DisasContext *ctx,break ;#endif case RR_CMP : -gen_logic (env,OPC_XOR ,24 , rx, ry); +gen_logic (env, ctx,OPC_XOR ,24 , rx, ry);break ;case RR_NEG :gen_arith (env, ctx,OPC_SUBU , rx,0 , ry);break ;case RR_AND : -gen_logic (env,OPC_AND , rx, rx, ry); +gen_logic (env, ctx,OPC_AND , rx, rx, ry);break ;case RR_OR : -gen_logic (env,OPC_OR , rx, rx, ry); +gen_logic (env, ctx,OPC_OR , rx, rx, ry);break ;case RR_XOR : -gen_logic (env,OPC_XOR , rx, rx, ry); +gen_logic (env, ctx,OPC_XOR , rx, rx, ry);break ;case RR_NOT : -gen_logic (env,OPC_NOR , rx, ry,0 ); +gen_logic (env, ctx,OPC_NOR , rx, ry,0 );break ;case RR_MFHI :gen_HILO (ctx,OPC_MFHI , rx);
@@ -9834,12 +9839,13 @@ static void gen_andi16 (CPUState *env, DisasContext *ctx)int rs =mmreg (uMIPS_RS (ctx->opcode));int encoded =ZIMM (ctx->opcode,0 ,4 ); -gen_logic_imm (env,OPC_ANDI , rd, rs, decoded_imm[encoded]); +gen_logic_imm (env, ctx,OPC_ANDI , rd, rs, decoded_imm[encoded]); }static void gen_ldst_multiple (DisasContext *ctx,uint32_t opc,int reglist,int base,int16_t offset) { +const char *opn ="ldst_multiple" ;TCGv t0, t1;TCGv_i32 t2;
@@ -9858,20 +9864,25 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,save_cpu_state (ctx,1 );switch (opc) {case LWM32 : + opn ="lwm" ;gen_helper_lwm (t0, t1, t2);break ;case SWM32 : + opn ="swm" ;gen_helper_swm (t0, t1, t2);break ;#ifdef TARGET_MIPS64 case LDM : + opn ="ldm" ;gen_helper_ldm (t0, t1, t2);break ;case SDM : + opn ="sdm" ;gen_helper_sdm (t0, t1, t2);break ;#endif } + (void )opn;/* avoid a compiler warning */ MIPS_DEBUG ("%s, %x, %d(%s)" , opn, reglist, offset, regnames[base]);tcg_temp_free (t0);tcg_temp_free (t1);
@@ -9890,25 +9901,25 @@ static void gen_pool16c_insn (CPUState *env, DisasContext *ctx, int *is_branch)case NOT16 +1 :case NOT16 +2 :case NOT16 +3 : -gen_logic (env,OPC_NOR , rd, rs,0 ); +gen_logic (env, ctx,OPC_NOR , rd, rs,0 );break ;case XOR16 +0 :case XOR16 +1 :case XOR16 +2 :case XOR16 +3 : -gen_logic (env,OPC_XOR , rd, rd, rs); +gen_logic (env, ctx,OPC_XOR , rd, rd, rs);break ;case AND16 +0 :case AND16 +1 :case AND16 +2 :case AND16 +3 : -gen_logic (env,OPC_AND , rd, rd, rs); +gen_logic (env, ctx,OPC_AND , rd, rd, rs);break ;case OR16 +0 :case OR16 +1 :case OR16 +2 :case OR16 +3 : -gen_logic (env,OPC_OR , rd, rd, rs); +gen_logic (env, ctx,OPC_OR , rd, rd, rs);break ;case LWM16 +0 :case LWM16 +1 :
@@ -10708,7 +10719,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,case XOR32 : mips32_op =OPC_XOR ; do_logic: -gen_logic (env, mips32_op, rd, rs, rt); +gen_logic (env, ctx, mips32_op, rd, rs, rt);break ;/* Set less than */ case SLT :
@@ -10717,7 +10728,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,case SLTU : mips32_op =OPC_SLTU ; do_slt: -gen_slt (env, mips32_op, rd, rs, rt); +gen_slt (env, ctx, mips32_op, rd, rs, rt);break ;default : goto pool32a_invalid;
@@ -10733,7 +10744,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,case MOVZ : mips32_op =OPC_MOVZ ; do_cmov: -gen_cond_move (env, mips32_op, rd, rs, rt); +gen_cond_move (env, ctx, mips32_op, rd, rs, rt);break ;case LWXS :gen_ldxs (ctx, rs, rt, rd);
@@ -11145,7 +11156,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,target. */ break ;case LUI : -gen_logic_imm (env,OPC_LUI , rs,-1 , imm); +gen_logic_imm (env, ctx,OPC_LUI , rs,-1 , imm);break ;case SYNCI :break ;
@@ -11264,7 +11275,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,case ANDI32 : mips32_op =OPC_ANDI ; do_logici: -gen_logic_imm (env, mips32_op, rt, rs, imm); +gen_logic_imm (env, ctx, mips32_op, rt, rs, imm);break ;/* Set less than immediate */
@@ -11274,7 +11285,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,case SLTIU32 : mips32_op =OPC_SLTIU ; do_slti: -gen_slt_imm (env, mips32_op, rt, rs, imm); +gen_slt_imm (env, ctx, mips32_op, rt, rs, imm);break ;case JALX32 : offset = (int32_t )(ctx->opcode &0x3FFFFFF ) <<2 ;
@@ -11751,7 +11762,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)case OPC_MOVZ :check_insn (env, ctx,ISA_MIPS4 |ISA_MIPS32 |INSN_LOONGSON2E |INSN_LOONGSON2F ); -gen_cond_move (env, op1, rd, rs, rt); +gen_cond_move (env, ctx, op1, rd, rs, rt);break ; case OPC_ADD ... OPC_SUBU:gen_arith (env, ctx, op1, rd, rs, rt);
@@ -11778,13 +11789,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)break ;case OPC_SLT :/* Set on less than */ case OPC_SLTU : -gen_slt (env, op1, rd, rs, rt); +gen_slt (env, ctx, op1, rd, rs, rt);break ;case OPC_AND :/* Logic*/ case OPC_OR :case OPC_NOR :case OPC_XOR : -gen_logic (env, op1, rd, rs, rt); +gen_logic (env, ctx, op1, rd, rs, rt);break ; case OPC_MULT ... OPC_DIVU:if (sa) {
@@ -12185,13 +12196,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)break ;case OPC_SLTI :/* Set on less than with immediate opcode */ case OPC_SLTIU : -gen_slt_imm (env, op, rt, rs, imm); +gen_slt_imm (env, ctx, op, rt, rs, imm);break ;case OPC_ANDI :/* Arithmetic with immediate opcode */ case OPC_LUI :case OPC_ORI :case OPC_XORI : -gen_logic_imm (env, op, rt, rs, imm); +gen_logic_imm (env, ctx, op, rt, rs, imm);break ; case OPC_J ... OPC_JAL: /* Jump */ offset = (int32_t )(ctx->opcode &0x3FFFFFF ) <<2 ;