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Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

RFC PATCH Superseded Marc Zyngier 5 participants 20 messages Sep 23, 2011 – Sep 26, 2011

Subsystems (9)
Arm (32-bit) Arm sub-architectures Arm Samsung Exynos Tegra architecture support +5 more subsystems

v1 of 3 Superseded Latest is v3 →

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Marc Zyngier

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#0 lore raw

cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

In order to support multiple primary interrupt controllers in the same image, it is necessary to use the MULTI_IRQ_HANDLER config option.

This patch series makes a first step in that direction by:
- having the GIC code to provides a global handler,
- make GIC users to provide this handler from their machine descriptor.

A side effect of this is that it forces OMAP2/3 platforms to be converted too in order to preserve the MULTI_OMAP feature. This leads to a certain simplification of the interrupt handling for the OMAP2/3/4 platforms.

The primary IRQ handlers have been written in C, and the performance degradation is hardly noticeable. Should some tests reveal a major increase in latency, it is always possible to restore the ASM version.

This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-2011 plus my PPI series.

Marc Zyngier (14):
ARM: GIC: Add global gic_handle_irq() function
ARM: RealView: convert to CONFIG_MULTI_IRQ_HANDLER
ARM: VExpress: convert to CONFIG_MULTI_IRQ_HANDLER
ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLER
ARM: GIC: Add global gic_handle_irq_offset() function
ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER
ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER
ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER
ARM: shmobile: convert smp platforms to gic_handle_irq()
ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLER
ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER
ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions
ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER
ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

 arch/arm/Kconfig                                  |    2 +
 arch/arm/common/Kconfig                           |    1 +
 arch/arm/common/gic.c                             |   49 +++++++-
 arch/arm/include/asm/hardware/entry-macro-gic.S   |   60 ---------
 arch/arm/include/asm/hardware/gic.h               |    3 +-
 arch/arm/mach-cns3xxx/cns3420vb.c                 |    2 +
 arch/arm/mach-cns3xxx/include/mach/entry-macro.S  |    2 -
 arch/arm/mach-exynos4/include/mach/entry-macro.S  |   62 ---------
 arch/arm/mach-exynos4/mach-armlex4210.c           |    2 +
 arch/arm/mach-exynos4/mach-nuri.c                 |    2 +
 arch/arm/mach-exynos4/mach-origen.c               |    2 +
 arch/arm/mach-exynos4/mach-smdk4212.c             |    2 +
 arch/arm/mach-exynos4/mach-smdkv310.c             |    2 +
 arch/arm/mach-exynos4/mach-universal_c210.c       |    2 +
 arch/arm/mach-msm/board-msm8960.c                 |    2 +
 arch/arm/mach-msm/board-msm8x60.c                 |    4 +
 arch/arm/mach-msm/include/mach/entry-macro-qgic.S |   17 ---
 arch/arm/mach-msm/include/mach/entry-macro-vic.S  |   37 ------
 arch/arm/mach-msm/include/mach/entry-macro.S      |   27 ++++-
 arch/arm/mach-omap2/Kconfig                       |    2 +
 arch/arm/mach-omap2/board-2430sdp.c               |    1 +
 arch/arm/mach-omap2/board-3430sdp.c               |    1 +
 arch/arm/mach-omap2/board-3630sdp.c               |    1 +
 arch/arm/mach-omap2/board-4430sdp.c               |    2 +
 arch/arm/mach-omap2/board-am3517crane.c           |    1 +
 arch/arm/mach-omap2/board-am3517evm.c             |    1 +
 arch/arm/mach-omap2/board-apollon.c               |    1 +
 arch/arm/mach-omap2/board-cm-t35.c                |    2 +
 arch/arm/mach-omap2/board-cm-t3517.c              |    1 +
 arch/arm/mach-omap2/board-devkit8000.c            |    1 +
 arch/arm/mach-omap2/board-generic.c               |    1 +
 arch/arm/mach-omap2/board-h4.c                    |    1 +
 arch/arm/mach-omap2/board-igep0020.c              |    2 +
 arch/arm/mach-omap2/board-ldp.c                   |    1 +
 arch/arm/mach-omap2/board-n8x0.c                  |    3 +
 arch/arm/mach-omap2/board-omap3beagle.c           |    1 +
 arch/arm/mach-omap2/board-omap3evm.c              |    1 +
 arch/arm/mach-omap2/board-omap3logic.c            |    2 +
 arch/arm/mach-omap2/board-omap3pandora.c          |    1 +
 arch/arm/mach-omap2/board-omap3stalker.c          |    1 +
 arch/arm/mach-omap2/board-omap3touchbook.c        |    1 +
 arch/arm/mach-omap2/board-omap4panda.c            |    2 +
 arch/arm/mach-omap2/board-overo.c                 |    1 +
 arch/arm/mach-omap2/board-rm680.c                 |    1 +
 arch/arm/mach-omap2/board-rx51.c                  |    1 +
 arch/arm/mach-omap2/board-zoom.c                  |    2 +
 arch/arm/mach-omap2/include/mach/entry-macro.S    |  137 ---------------------
 arch/arm/mach-omap2/irq.c                         |   49 ++++++++
 arch/arm/mach-realview/include/mach/entry-macro.S |    2 -
 arch/arm/mach-realview/realview_eb.c              |    1 +
 arch/arm/mach-realview/realview_pb1176.c          |    1 +
 arch/arm/mach-realview/realview_pb11mp.c          |    1 +
 arch/arm/mach-realview/realview_pba8.c            |    1 +
 arch/arm/mach-realview/realview_pbx.c             |    1 +
 arch/arm/mach-shmobile/Makefile                   |    1 -
 arch/arm/mach-shmobile/board-ag5evm.c             |    2 +-
 arch/arm/mach-shmobile/entry-gic.S                |   18 ---
 arch/arm/mach-shmobile/include/mach/common.h      |    1 -
 arch/arm/mach-tegra/board-dt.c                    |    2 +
 arch/arm/mach-tegra/board-harmony.c               |    2 +
 arch/arm/mach-tegra/board-paz00.c                 |    2 +
 arch/arm/mach-tegra/board-seaboard.c              |    4 +
 arch/arm/mach-tegra/board-trimslice.c             |    2 +
 arch/arm/mach-tegra/include/mach/entry-macro.S    |   22 +---
 arch/arm/mach-ux500/board-mop500.c                |    4 +
 arch/arm/mach-ux500/board-u5500.c                 |    2 +
 arch/arm/mach-ux500/include/mach/entry-macro.S    |    2 -
 arch/arm/mach-vexpress/include/mach/entry-macro.S |    2 -
 arch/arm/mach-vexpress/v2m.c                      |    2 +
 arch/arm/mach-zynq/common.c                       |    1 +
 arch/arm/mach-zynq/include/mach/entry-macro.S     |    3 -
 arch/arm/plat-omap/include/plat/irqs.h            |    2 +
 72 files changed, 212 insertions(+), 371 deletions(-)
 delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-qgic.S
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-vic.S
 delete mode 100644 arch/arm/mach-shmobile/entry-gic.S
author
#1 lore raw

RFC PATCH 1/14 ARM: GIC: Add global gic_handle_irq() function

Provide the GIC code with a low level handler that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handler is written in C, the compiled code doesn't feel much slower than its assembly counterpart (at least with my gcc 4.4.1).

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/common/gic.c               |   23 +++++++++++++++++++++++
 arch/arm/include/asm/hardware/gic.h |    1 +
 2 files changed, 24 insertions(+), 0 deletions(-)
arch/arm/common/gic.c +23 -0
index a3f335c..a7b2a4a 100644
@@ -209,6 +209,29 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
 #define gic_set_wake	NULL
 #endif
 
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+		irqnr = irqstat & ~0x1c00;
+
+		if (likely(irqnr > 15 && irqnr < 1021)) {
+			handle_IRQ(irqnr, regs);
+			continue;
+		}
+		if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+			do_IPI(irqnr, regs);
+#endif
+			continue;
+		}
+		break;
+	} while (1);
+}
+
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
 	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
arch/arm/include/asm/hardware/gic.h +1 -0
index 2dadd50..45e4ab4 100644
@@ -38,6 +38,7 @@ extern struct irq_chip gic_arch_extn;
 
 void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
 void gic_secondary_init(unsigned int);
+void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
Signature · 1 line
1.7.0.4
#2 lore raw

RFC PATCH 1/14 ARM: GIC: Add global gic_handle_irq() function

arch/arm/common/gic.c static int gic_set_wake(struct irq_data *d, unsigned int on) · line 228

Quoted 5 lines · Marc Zyngier
arch/arm/common/gic.c +5 -0
+		if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+			do_IPI(irqnr, regs);
+#endif

This doesn't work. do_IPI is marked as an entry function, and so expects to be called with the precondition that the pt_regs are stored immediately above its stack frame, without another function's stack frame in the way.

author
#3 lore raw

RFC PATCH 1/14 ARM: GIC: Add global gic_handle_irq() function

Quoted 11 lines · Russell King - ARM Linux

arch/arm/common/gic.c static int gic_set_wake(struct irq_data *d, unsigned int on) · line 228

Quoted 5 lines · Marc Zyngier
arch/arm/common/gic.c +5 -0
+		if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+			do_IPI(irqnr, regs);
+#endif

This doesn't work. do_IPI is marked as an entry function, and so expects to be called with the precondition that the pt_regs are stored immediately above its stack frame, without another function's stack frame in the way.

Good point. I'll add a handle_IPI() function, modeled after handle_IRQ().

Thanks for pointing this out.

	M.
Signature · 1 line
Jazz is not dead. It just smells funny...
author
#4 lore raw

RFC PATCH 2/14 ARM: RealView: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the RealView platforms to be using the gic_handle_irq function as their primary interrupt handler.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                  |    1 +
 arch/arm/mach-realview/include/mach/entry-macro.S |    2 --
 arch/arm/mach-realview/realview_eb.c              |    1 +
 arch/arm/mach-realview/realview_pb1176.c          |    1 +
 arch/arm/mach-realview/realview_pb11mp.c          |    1 +
 arch/arm/mach-realview/realview_pba8.c            |    1 +
 arch/arm/mach-realview/realview_pbx.c             |    1 +
 7 files changed, 6 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
index 472a7f8..6c31cc2 100644
@@ -262,6 +262,7 @@ config ARCH_REALVIEW
 	select PLAT_VERSATILE_CLCD
 	select ARM_TIMER_SP804
 	select GPIO_PL061 if GPIOLIB
+	select MULTI_IRQ_HANDLER
 	help
 	  This enables support for ARM Ltd RealView boards.
arch/arm/mach-realview/include/mach/entry-macro.S +0 -2
index 4071164..e8a5179 100644
@@ -7,8 +7,6 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
arch/arm/mach-realview/realview_eb.c +1 -0
index 427e44e..f01e332 100644
@@ -470,6 +470,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_eb_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_eb_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
arch/arm/mach-realview/realview_pb1176.c +1 -0
index 863f286..539cde3 100644
@@ -365,6 +365,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pb1176_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pb1176_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
arch/arm/mach-realview/realview_pb11mp.c +1 -0
index 6cb8318..32d18e5 100644
@@ -367,6 +367,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pb11mp_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pb11mp_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
arch/arm/mach-realview/realview_pba8.c +1 -0
index 3db72c5..0896cc4 100644
@@ -317,6 +317,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pba8_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pba8_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
arch/arm/mach-realview/realview_pbx.c +1 -0
index 7e5d540..eaedeaa 100644
@@ -400,6 +400,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pbx_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pbx_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
Signature · 1 line
1.7.0.4
author
#5 lore raw

RFC PATCH 3/14 ARM: VExpress: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the VExpress platform to be using the gic_handle_irq function as its primary interrupt handler.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                  |    1 +
 arch/arm/mach-vexpress/include/mach/entry-macro.S |    2 --
 arch/arm/mach-vexpress/v2m.c                      |    2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
index 6c31cc2..d3e246c 100644
@@ -295,6 +295,7 @@ config ARCH_VEXPRESS
 	select ICST
 	select PLAT_VERSATILE
 	select PLAT_VERSATILE_CLCD
+	select MULTI_IRQ_HANDLER
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
arch/arm/mach-vexpress/include/mach/entry-macro.S +0 -2
index 73c1129..a14f9e6 100644
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
-
 	.macro	disable_fiq
 	.endm
arch/arm/mach-vexpress/v2m.c +2 -0
index 47bca2a..d540a1b 100644
@@ -24,6 +24,7 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/sp810.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/ct-ca9x4.h>
 #include <mach/motherboard.h>

@@ -457,5 +458,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
 	.init_early	= v2m_init_early,
 	.init_irq	= v2m_init_irq,
 	.timer		= &v2m_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= v2m_init,
 MACHINE_END
Signature · 1 line
1.7.0.4
author
#6 lore raw

RFC PATCH 4/14 ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the SMP msm platforms to be using the gic_handle_irq function as their primary interrupt handler.

Cc David Brown <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-msm/Kconfig                         |    2 +
 arch/arm/mach-msm/board-msm8960.c                 |    2 +
 arch/arm/mach-msm/board-msm8x60.c                 |    4 ++
 arch/arm/mach-msm/include/mach/entry-macro-qgic.S |   17 ---------
 arch/arm/mach-msm/include/mach/entry-macro-vic.S  |   37 ---------------------
 arch/arm/mach-msm/include/mach/entry-macro.S      |   27 +++++++++++++--
 6 files changed, 31 insertions(+), 58 deletions(-)
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-qgic.S
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-vic.S
arch/arm/mach-msm/Kconfig +2 -0
index ebde97f..ba36b74 100644
@@ -50,6 +50,7 @@ config ARCH_MSM8X60
 	select GPIO_MSM_V2
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
+	select MULTI_IRQ_HANDLER
 
 config ARCH_MSM8960
 	bool "MSM8960"

@@ -60,6 +61,7 @@ config ARCH_MSM8960
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
+	select MULTI_IRQ_HANDLER
 
 endchoice
arch/arm/mach-msm/board-msm8960.c +2 -0
index c811e29..7af9a6d 100644
@@ -101,6 +101,7 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
 	.map_io = msm8960_map_io,
 	.init_irq = msm8960_init_irq,
 	.timer = &msm_timer,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8960_sim_init,
 MACHINE_END
 

@@ -111,6 +112,7 @@ MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
 	.map_io = msm8960_map_io,
 	.init_irq = msm8960_init_irq,
 	.timer = &msm_timer,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8960_rumi3_init,
 MACHINE_END
arch/arm/mach-msm/board-msm8x60.c +4 -0
index 30c6b58..1eca320 100644
@@ -111,6 +111,7 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END

@@ -121,6 +122,7 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END

@@ -131,6 +133,7 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END

@@ -141,6 +144,7 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END
arch/arm/mach-msm/include/mach/entry-macro-qgic.S deleted +0 -17
deleted file mode 100644
index 717076f..0000000
@@ -1,17 +0,0 @@
-/*
- * Low-level IRQ helper macros
- *
- * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/entry-macro-gic.S>
-
-	.macro	disable_fiq
-	.endm
-
-	.macro  arch_ret_to_user, tmp1, tmp2
-	.endm
arch/arm/mach-msm/include/mach/entry-macro-vic.S deleted +0 -37
deleted file mode 100644
index 70563ed..0000000
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <[email protected]>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/msm_iomap.h>
-
-	.macro	disable_fiq
-	.endm
-
-	.macro	get_irqnr_preamble, base, tmp
-	@ enable imprecise aborts
-	cpsie	a
-	mov	\base, #MSM_VIC_BASE
-	.endm
-
-	.macro	arch_ret_to_user, tmp1, tmp2
-	.endm
-
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-	@ 0xD0 has irq# or old irq# if the irq has been handled
-	@ 0xD4 has irq# or -1 if none pending *but* if you just
-	@ read 0xD4 you never get the first irq for some reason
-	ldr	\irqnr, [\base, #0xD0]
-	ldr	\irqnr, [\base, #0xD4]
-	cmp	\irqnr, #0xffffffff
-	.endm
arch/arm/mach-msm/include/mach/entry-macro.S +23 -4
index b16f082..41f7003 100644
@@ -16,8 +16,27 @@
  *
  */
 
-#if defined(CONFIG_ARM_GIC)
-#include <mach/entry-macro-qgic.S>
-#else
-#include <mach/entry-macro-vic.S>
+	.macro	disable_fiq
+	.endm
+
+	.macro	arch_ret_to_user, tmp1, tmp2
+	.endm
+
+#if !defined(CONFIG_ARM_GIC)
+#include <mach/msm_iomap.h>
+
+	.macro	get_irqnr_preamble, base, tmp
+	@ enable imprecise aborts
+	cpsie	a
+	mov	\base, #MSM_VIC_BASE
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+	@ 0xD0 has irq# or old irq# if the irq has been handled
+	@ 0xD4 has irq# or -1 if none pending *but* if you just
+	@ read 0xD4 you never get the first irq for some reason
+	ldr	\irqnr, [\base, #0xD0]
+	ldr	\irqnr, [\base, #0xD4]
+	cmp	\irqnr, #0xffffffff
+	.endm
 #endif
Signature · 1 line
1.7.0.4
author
#7 lore raw

RFC PATCH 5/14 ARM: GIC: Add global gic_handle_irq_offset() function

In reply to Marc Zyngier

Similar to gic_handle_irq(), gic_handle_irq_offset() is provided for those platform who insist on having their GIC base interrupt at something different from zero. At the moment, Exynos4 is the only one...

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/common/gic.c               |   24 ++++++++++++++++++++++++
 arch/arm/include/asm/hardware/gic.h |    1 +
 2 files changed, 25 insertions(+), 0 deletions(-)
arch/arm/common/gic.c +24 -0
index a7b2a4a..ea8bfc5 100644
@@ -232,6 +232,30 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 	} while (1);
 }
 
+asmlinkage void __exception_irq_entry gic_handle_irq_offset(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+	u32 offset = gic_data[0].irq_offset;
+
+	do {
+		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+		irqnr = irqstat & ~0x1c00;
+
+		if (likely(irqnr > 15 && irqnr < 1021)) {
+			handle_IRQ(irqnr + offset, regs);
+			continue;
+		}
+		if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+			do_IPI(irqnr, regs);
+#endif
+			continue;
+		}
+		break;
+	} while (1);
+}
+
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
 	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
arch/arm/include/asm/hardware/gic.h +1 -0
index 45e4ab4..0f454c6 100644
@@ -39,6 +39,7 @@ extern struct irq_chip gic_arch_extn;
 void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
 void gic_secondary_init(unsigned int);
 void gic_handle_irq(struct pt_regs *regs);
+void gic_handle_irq_offset(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
Signature · 1 line
1.7.0.4
author
#8 lore raw

RFC PATCH 6/14 ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the Exynos4 platforms to be using the gic_handle_irq_offset() function as their primary interrupt handler.

Cc Ben Dooks <[email protected]>
Cc Kukjin Kim <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                 |    1 +
 arch/arm/mach-exynos4/include/mach/entry-macro.S |   62 ----------------------
 arch/arm/mach-exynos4/mach-armlex4210.c          |    2 +
 arch/arm/mach-exynos4/mach-nuri.c                |    2 +
 arch/arm/mach-exynos4/mach-origen.c              |    2 +
 arch/arm/mach-exynos4/mach-smdk4212.c            |    2 +
 arch/arm/mach-exynos4/mach-smdkv310.c            |    2 +
 arch/arm/mach-exynos4/mach-universal_c210.c      |    2 +
 8 files changed, 13 insertions(+), 62 deletions(-)
arch/arm/Kconfig +1 -0
index d3e246c..e32a4d3 100644
@@ -787,6 +787,7 @@ config ARCH_EXYNOS4
 	select HAVE_S3C_RTC if RTC_CLASS
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select MULTI_IRQ_HANDLER
 	help
 	  Samsung EXYNOS4 series based systems
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -62

71 lines not on this page · raw message

arch/arm/mach-exynos4/mach-armlex4210.c +2 -0
index 8c82c6b..969e04c 100644
@@ -15,6 +15,7 @@
 #include <linux/serial_core.h>
 #include <linux/smsc911x.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -213,6 +214,7 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= armlex4210_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= armlex4210_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
arch/arm/mach-exynos4/mach-nuri.c +2 -0
index 5780ee3..5e133ae 100644
@@ -28,6 +28,7 @@
 
 #include <video/platform_lcd.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -1192,6 +1193,7 @@ MACHINE_START(NURI, "NURI")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= nuri_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= nuri_machine_init,
 	.timer		= &exynos4_timer,
 	.reserve        = &nuri_reserve,
arch/arm/mach-exynos4/mach-origen.c +2 -0
index 06250fc..7ede5fc 100644
@@ -17,6 +17,7 @@
 #include <linux/pwm_backlight.h>
 #include <linux/gpio_keys.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -215,6 +216,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= origen_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= origen_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
arch/arm/mach-exynos4/mach-smdk4212.c +2 -0
index cf92514..84a0446 100644
@@ -20,6 +20,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/serial_core.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -290,6 +291,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= smdk4212_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= smdk4212_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
arch/arm/mach-exynos4/mach-smdkv310.c +2 -0
index 088644e..8e11eaa 100644
@@ -20,6 +20,7 @@
 #include <linux/input.h>
 #include <linux/pwm_backlight.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -351,6 +352,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= smdkv310_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= smdkv310_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
arch/arm/mach-exynos4/mach-universal_c210.c +2 -0
index 39c34a1..43f156d 100644
@@ -23,6 +23,7 @@
 #include <linux/i2c/mcs.h>
 #include <linux/i2c/atmel_mxt_ts.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -876,6 +877,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= universal_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= universal_machine_init,
 	.timer		= &exynos4_timer,
 	.reserve        = &universal_reserve,
Signature · 1 line
1.7.0.4
author
#9 lore raw

RFC PATCH 7/14 ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the tegra2 platforms to be using the gic_handle_irq function as their primary interrupt handler.

Tested on harmony.

Cc Stephen Warren <[email protected]>
Cc Colin Cross <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-tegra/Kconfig                    |    1 +
 arch/arm/mach-tegra/board-dt.c                 |    2 ++
 arch/arm/mach-tegra/board-harmony.c            |    2 ++
 arch/arm/mach-tegra/board-paz00.c              |    2 ++
 arch/arm/mach-tegra/board-seaboard.c           |    4 ++++
 arch/arm/mach-tegra/board-trimslice.c          |    2 ++
 arch/arm/mach-tegra/include/mach/entry-macro.S |   22 ++--------------------
 7 files changed, 15 insertions(+), 20 deletions(-)
arch/arm/mach-tegra/Kconfig +1 -0
index d82ebab..ba0ac3f 100644
@@ -13,6 +13,7 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
arch/arm/mach-tegra/board-dt.c +2 -0
index 0b3f937..cfa39c5 100644
@@ -32,6 +32,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>

@@ -115,6 +116,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
 	.soc		= &tegra_soc_desc,
 	.init_early	= tegra_init_early,
 	.init_irq	= tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer		= &tegra_timer,
 	.init_machine	= tegra_dt_init,
 	.dt_compat	= tegra_dt_board_compat,
arch/arm/mach-tegra/board-harmony.c +2 -0
index 10f7ce0..da4f768 100644
@@ -31,6 +31,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
 #include <asm/setup.h>
 
 #include <mach/tegra_wm8903_pdata.h>

@@ -189,6 +190,7 @@ MACHINE_START(HARMONY, "harmony")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_harmony_init,
 MACHINE_END
arch/arm/mach-tegra/board-paz00.c +2 -0
index 5b0b839..b14f517 100644
@@ -28,6 +28,7 @@
 #include <linux/i2c.h>
 #include <linux/rfkill-gpio.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>

@@ -192,6 +193,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_paz00_init,
 MACHINE_END
arch/arm/mach-tegra/board-seaboard.c +4 -0
index dfd9c95..7fd71cf 100644
@@ -34,6 +34,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 
 #include "board.h"
 #include "board-seaboard.h"

@@ -286,6 +287,7 @@ MACHINE_START(SEABOARD, "seaboard")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_seaboard_init,
 MACHINE_END

@@ -296,6 +298,7 @@ MACHINE_START(KAEN, "kaen")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_kaen_init,
 MACHINE_END

@@ -306,6 +309,7 @@ MACHINE_START(WARIO, "wario")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_wario_init,
 MACHINE_END
arch/arm/mach-tegra/board-trimslice.c +2 -0
index 2ce45a6..730f77a 100644
@@ -26,6 +26,7 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>

@@ -179,6 +180,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_trimslice_init,
 MACHINE_END
arch/arm/mach-tegra/include/mach/entry-macro.S +2 -20
index dd165c5..ac11262 100644
@@ -12,30 +12,15 @@
  * GNU General Public License for more details.
  *
  */
-#include <mach/iomap.h>
-#include <mach/io.h>
-
-#if defined(CONFIG_ARM_GIC)
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-
-	/* Uses the GIC interrupt controller built into the cpu */
-#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
 
 	.macro	disable_fiq
 	.endm
 
-	.macro	get_irqnr_preamble, base, tmp
-	movw \base, #(ICTRL_BASE & 0x0000ffff)
-	movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
+	.macro	arch_ret_to_user, tmp1, tmp2
 	.endm
 
-	.macro  arch_ret_to_user, tmp1, tmp2
-	.endm
-#else
+#if !defined(CONFIG_ARM_GIC)
 	/* legacy interrupt controller for AP16 */
-	.macro	disable_fiq
-	.endm
 
 	.macro	get_irqnr_preamble, base, tmp
 	@ enable imprecise aborts

@@ -46,9 +31,6 @@
 	orr \base, #0x0000f000
 	.endm
 
-	.macro	arch_ret_to_user, tmp1, tmp2
-	.endm
-
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	ldr \irqnr, [\base, #0x20]	@ EVT_IRQ_STS
 	cmp \irqnr, #0x80
Signature · 1 line
1.7.0.4
#10 lore raw

RFC PATCH 7/14 ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER

Marc Zyngier wrote at Friday, September 23, 2011 10:51 AM:

Quoted 8 lines

Convert the tegra2 platforms to be using the gic_handle_irq function as their primary interrupt handler.

Tested on harmony.

Cc Stephen Warren <[email protected]>
Cc Colin Cross <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>

I'm not experienced in this area of the kernel, but I traced through the old assembly and new C code, and they appear to be doing the same thing, and be hooked together sanely, so:

Acked-by Stephen Warren <[email protected]>
Signature · 1 line
nvpublic
author
#11 lore raw

RFC PATCH 8/14 ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the ux500 platforms to be using the gic_handle_irq function as their primary interrupt handler.

Cc Linus Walleij <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-ux500/Kconfig                    |    1 +
 arch/arm/mach-ux500/board-mop500.c             |    4 ++++
 arch/arm/mach-ux500/board-u5500.c              |    2 ++
 arch/arm/mach-ux500/include/mach/entry-macro.S |    2 --
 4 files changed, 7 insertions(+), 2 deletions(-)
arch/arm/mach-ux500/Kconfig +1 -0
index a3e0c86..bb2b52b 100644
@@ -7,6 +7,7 @@ config UX500_SOC_COMMON
 	select HAS_MTU
 	select ARM_ERRATA_753970
 	select ARM_ERRATA_754322
+	select MULTI_IRQ_HANDLER
 
 menu "Ux500 SoC"
arch/arm/mach-ux500/board-mop500.c +4 -0
index f0b1a00..2539b0b 100644
@@ -33,6 +33,7 @@
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 
 #include <plat/i2c.h>
 #include <plat/ste_dma40.h>

@@ -696,6 +697,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
 	.init_irq	= ux500_init_irq,
 	/* we re-use nomadik timer here */
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= mop500_init_machine,
 MACHINE_END
 

@@ -705,6 +707,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
 	.map_io		= u8500_map_io,
 	.init_irq	= ux500_init_irq,
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= hrefv60_init_machine,
 MACHINE_END
 

@@ -715,5 +718,6 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
 	.init_irq	= ux500_init_irq,
 	/* we re-use nomadik timer here */
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= snowball_init_machine,
 MACHINE_END
arch/arm/mach-ux500/board-u5500.c +2 -0
index ddfad36..c4c90a3 100644
@@ -11,6 +11,7 @@
 #include <linux/irq.h>
 #include <linux/i2c.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -123,5 +124,6 @@ MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
 	.map_io		= u5500_map_io,
 	.init_irq	= ux500_init_irq,
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= u5500_init_machine,
 MACHINE_END
arch/arm/mach-ux500/include/mach/entry-macro.S +0 -2
index 071bba9..e16299e 100644
@@ -10,8 +10,6 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
Signature · 1 line
1.7.0.4
author
#12 lore raw

RFC PATCH 9/14 ARM: shmobile: convert smp platforms to gic_handle_irq()

In reply to Marc Zyngier

Convert the SMP shmobile platforms to use gic_handle_irq() instead of the assembly macro.

Cc Paul Mundt <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-shmobile/Makefile              |    1 -
 arch/arm/mach-shmobile/board-ag5evm.c        |    2 +-
 arch/arm/mach-shmobile/entry-gic.S           |   18 ------------------
 arch/arm/mach-shmobile/include/mach/common.h |    1 -
 4 files changed, 1 insertions(+), 21 deletions(-)
 delete mode 100644 arch/arm/mach-shmobile/entry-gic.S
arch/arm/mach-shmobile/Makefile +0 -1
index 612b270..f58ef1e 100644
@@ -28,7 +28,6 @@ pfc-$(CONFIG_ARCH_SH73A0)	+= pfc-sh73a0.o
 obj-$(CONFIG_ARCH_SH7367)	+= entry-intc.o
 obj-$(CONFIG_ARCH_SH7377)	+= entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)	+= entry-intc.o
-obj-$(CONFIG_ARCH_SH73A0)	+= entry-gic.o
 
 # PM objects
 obj-$(CONFIG_SUSPEND)		+= suspend.o
arch/arm/mach-shmobile/board-ag5evm.c +1 -1
index 475342b..145473e 100644
@@ -602,7 +602,7 @@ struct sys_timer ag5evm_timer = {
 MACHINE_START(AG5EVM, "ag5evm")
 	.map_io		= ag5evm_map_io,
 	.init_irq	= ag5evm_init_irq,
-	.handle_irq	= shmobile_handle_irq_gic,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= ag5evm_init,
 	.timer		= &ag5evm_timer,
 MACHINE_END
arch/arm/mach-shmobile/entry-gic.S deleted +0 -18
deleted file mode 100644
index e20239b..0000000
@@ -1,18 +0,0 @@
-/*
- * ARM Interrupt demux handler using GIC
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2011 Paul Mundt
- * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/assembler.h>
-#include <asm/entry-macro-multi.S>
-#include <asm/hardware/gic.h>
-#include <asm/hardware/entry-macro-gic.S>
-
-	arch_irq_handler shmobile_handle_irq_gic
arch/arm/mach-shmobile/include/mach/common.h +0 -1
index 06aecb3..29d3876 100644
@@ -7,7 +7,6 @@ extern void shmobile_secondary_vector(void);
 struct clk;
 extern int clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
-extern void shmobile_handle_irq_gic(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_device;
 extern void (*shmobile_cpuidle_modes[])(void);
Signature · 1 line
1.7.0.4
author
#13 lore raw

RFC PATCH 10/14 ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the cns3xxx platform to be using the gic_handle_irq function as its primary interrupt handler.

Cc Anton Vorontsov <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                 |    1 +
 arch/arm/mach-cns3xxx/cns3420vb.c                |    2 ++
 arch/arm/mach-cns3xxx/include/mach/entry-macro.S |    2 --
 3 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
index e32a4d3..70a947e 100644
@@ -334,6 +334,7 @@ config ARCH_CNS3XXX
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
 	select PCI_DOMAINS if PCI
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for Cavium Networks CNS3XXX platform.
arch/arm/mach-cns3xxx/cns3420vb.c +2 -0
index 55f7b4b..594852f 100644
@@ -26,6 +26,7 @@
 #include <linux/mtd/partitions.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>

@@ -201,5 +202,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
 	.map_io		= cns3420_map_io,
 	.init_irq	= cns3xxx_init_irq,
 	.timer		= &cns3xxx_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= cns3420_init,
 MACHINE_END
arch/arm/mach-cns3xxx/include/mach/entry-macro.S +0 -2
index d87bfc3..01c57df 100644
@@ -8,8 +8,6 @@
  * published by the Free Software Foundation.
  */
 
-#include <asm/hardware/entry-macro-gic.S>
-
 		.macro	disable_fiq
 		.endm
Signature · 1 line
1.7.0.4
author
#15 lore raw

RFC PATCH 11/14 ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the zynq platform to be using the gic_handle_irq function as its primary interrupt handler.

Cc John Linn <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                              |    1 +
 arch/arm/mach-zynq/common.c                   |    1 +
 arch/arm/mach-zynq/include/mach/entry-macro.S |    3 ---
 3 files changed, 2 insertions(+), 3 deletions(-)
arch/arm/Kconfig +1 -0
index 70a947e..0514264 100644
@@ -911,6 +911,7 @@ config ARCH_ZYNQ
 	select ARM_AMBA
 	select ICST
 	select USE_OF
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
arch/arm/mach-zynq/common.c +1 -0
index 73e9368..ab5cfdd 100644
@@ -112,6 +112,7 @@ static const char *xilinx_dt_match[] = {
 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
 	.map_io		= xilinx_map_io,
 	.init_irq	= xilinx_irq_init,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= xilinx_init_machine,
 	.timer		= &xttcpss_sys_timer,
 	.dt_compat	= xilinx_dt_match,
arch/arm/mach-zynq/include/mach/entry-macro.S +0 -3
index 3cfc01b..d621fb7 100644
@@ -20,9 +20,6 @@
  * GNU General Public License for more details.
  */
 
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
-
 		.macro  disable_fiq
 		.endm
Signature · 1 line
1.7.0.4
#16 lore raw

RFC PATCH 11/14 ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER

Quoted 8 lines

-----Original Message-----
From: Marc Zyngier [mailto:marc.zyngier at arm.com]
Sent: Friday, September 23, 2011 10:51 AM
To: linux-arm-kernel at lists.infradead.org
Cc: John Linn
Subject: [RFC PATCH 11/14] ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER

Quoted 5 lines

Convert the zynq platform to be using the gic_handle_irq function as its primary interrupt handler.

Cc John Linn <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>

It seems like if I see any issues I can always go back to the previous solution as this is not required for our platform. But it's nice to stay in sync with everyone else.

Acked-by John Linn <[email protected]>

Thanks,
John

Please ignore the following legal footer that I'm trying to get taken off.

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

author
#17 lore raw

RFC PATCH 12/14 ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions

In reply to Marc Zyngier

Provide the OMAP2/3 IRQ code with low level handlers that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handlers are written in C, the compiled code looks very similar to its assembly counterpart (at least with my gcc 4.4.1).

Cc Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-omap2/irq.c              |   49 ++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/irqs.h |    2 +
 2 files changed, 51 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/irq.c +49 -0
index 3a12f75..0a48b33 100644
@@ -35,6 +35,11 @@
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG	32
 
+#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
+#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
+
 /*
  * OMAP2 has a number of different interrupt controllers, each interrupt
  * controller is identified as its own "bank". Register definitions are

@@ -191,6 +196,44 @@ void __init ti816x_init_irq(void)
 	omap_init_irq(OMAP34XX_IC_BASE, 128);
 }
 
+static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
+{
+	u32 irqnr;
+
+	do {
+		irqnr = readl_relaxed(base_addr + 0x98);
+		if (irqnr)
+			goto out;
+
+		irqnr = readl_relaxed(base_addr + 0xb8);
+		if (irqnr)
+			goto out;
+
+		irqnr = readl_relaxed(base_addr + 0xd8);
+#ifdef CONFIG_SOC_OMAPTI816X
+		if (irqnr)
+			goto out;
+		irqnr = readl_relaxed(base_addr + 0xf8);
+#endif
+
+out:
+		if (!irqnr)
+			break;
+
+		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
+		irqnr &= ACTIVEIRQ_MASK;
+
+		if (irqnr)
+			handle_IRQ(irqnr, regs);
+	} while (irqnr);
+}
+
+asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
+{
+	void __iomem *base_addr = OMAP2_IRQ_BASE;
+	omap_intc_handle_irq(base_addr, regs);
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 

@@ -263,4 +306,10 @@ void omap3_intc_resume_idle(void)
 	/* Re-enable autoidle */
 	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
 }
+
+asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
+{
+	void __iomem *base_addr = OMAP3_IRQ_BASE;
+	omap_intc_handle_irq(base_addr, regs);
+}
 #endif /* CONFIG_ARCH_OMAP3 */
arch/arm/plat-omap/include/plat/irqs.h +2 -0
index 30e1071..8b19a63 100644
@@ -448,6 +448,8 @@ void omap_intc_restore_context(void);
 void omap3_intc_suspend(void);
 void omap3_intc_prepare_idle(void);
 void omap3_intc_resume_idle(void);
+void omap2_intc_handle_irq(struct pt_regs *regs);
+void omap3_intc_handle_irq(struct pt_regs *regs);
 #endif
 
 #include <mach/hardware.h>
Signature · 1 line
1.7.0.4
author
#18 lore raw

RFC PATCH 13/14 ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the omap2plus platforms to be using CONFIG_MULTI_IRQ_HANDLER. Each machine is modified to provide either omap2_intc_handle_irq(), omap3_intc_handle_irq() or gic_handle_irq().

This allows for a major cleanup, removing the MULTI_OMAP setup from the interrupt path.

Tested on both Panda and IGEPv2 (single kernel image)

Cc Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-omap2/Kconfig                    |    1 +
 arch/arm/mach-omap2/board-2430sdp.c            |    1 +
 arch/arm/mach-omap2/board-3430sdp.c            |    1 +
 arch/arm/mach-omap2/board-3630sdp.c            |    1 +
 arch/arm/mach-omap2/board-4430sdp.c            |    2 +
 arch/arm/mach-omap2/board-am3517crane.c        |    1 +
 arch/arm/mach-omap2/board-am3517evm.c          |    1 +
 arch/arm/mach-omap2/board-apollon.c            |    1 +
 arch/arm/mach-omap2/board-cm-t35.c             |    2 +
 arch/arm/mach-omap2/board-cm-t3517.c           |    1 +
 arch/arm/mach-omap2/board-devkit8000.c         |    1 +
 arch/arm/mach-omap2/board-generic.c            |    1 +
 arch/arm/mach-omap2/board-h4.c                 |    1 +
 arch/arm/mach-omap2/board-igep0020.c           |    2 +
 arch/arm/mach-omap2/board-ldp.c                |    1 +
 arch/arm/mach-omap2/board-n8x0.c               |    3 +
 arch/arm/mach-omap2/board-omap3beagle.c        |    1 +
 arch/arm/mach-omap2/board-omap3evm.c           |    1 +
 arch/arm/mach-omap2/board-omap3logic.c         |    2 +
 arch/arm/mach-omap2/board-omap3pandora.c       |    1 +
 arch/arm/mach-omap2/board-omap3stalker.c       |    1 +
 arch/arm/mach-omap2/board-omap3touchbook.c     |    1 +
 arch/arm/mach-omap2/board-omap4panda.c         |    2 +
 arch/arm/mach-omap2/board-overo.c              |    1 +
 arch/arm/mach-omap2/board-rm680.c              |    1 +
 arch/arm/mach-omap2/board-rx51.c               |    1 +
 arch/arm/mach-omap2/board-zoom.c               |    2 +
 arch/arm/mach-omap2/include/mach/entry-macro.S |  137 ------------------------
 arch/arm/plat-omap/Kconfig                     |    1 +
 29 files changed, 36 insertions(+), 137 deletions(-)
arch/arm/mach-omap2/Kconfig +1 -0
index 1aee224..4c5b01d 100644
@@ -25,6 +25,7 @@ config ARCH_OMAP2
 	depends on ARCH_OMAP2PLUS
 	default y
 	select CPU_V6
+	select MULTI_IRQ_HANDLER
 
 config ARCH_OMAP3
 	bool "TI OMAP3"
arch/arm/mach-omap2/board-2430sdp.c +1 -0
index 4191743..56785c6 100644
@@ -256,6 +256,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
 	.map_io		= omap_2430sdp_map_io,
 	.init_early	= omap2430_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_2430sdp_init,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-3430sdp.c +1 -0
index 77142c1..1c17bd8 100644
@@ -728,6 +728,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_3430sdp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-3630sdp.c +1 -0
index f552305..b27aa85 100644
@@ -215,6 +215,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_sdp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-4430sdp.c +2 -0
index c404c5b..1b9e372 100644
@@ -28,6 +28,7 @@
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>

@@ -991,6 +992,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
 	.map_io		= omap_4430sdp_map_io,
 	.init_early	= omap4430_init_early,
 	.init_irq	= gic_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap_4430sdp_init,
 	.timer		= &omap4_timer,
 MACHINE_END
arch/arm/mach-omap2/board-am3517crane.c +1 -0
index 7834536..0166f4e 100644
@@ -98,6 +98,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= am3517_crane_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-am3517evm.c +1 -0
index d314f03..18cf2ce 100644
@@ -491,6 +491,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= am3517_evm_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-apollon.c +1 -0
index 868d5f0..ab6704f 100644
@@ -350,6 +350,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
 	.map_io		= omap_apollon_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_apollon_init,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-cm-t35.c +2 -0
index bd1bcac..21a2436 100644
@@ -634,6 +634,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= cm_t35_init,
 	.timer		= &omap3_timer,
 MACHINE_END

@@ -644,6 +645,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
 	.map_io         = omap3_map_io,
 	.init_early     = omap3630_init_early,
 	.init_irq       = omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine   = cm_t3730_init,
 	.timer          = &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-cm-t3517.c +1 -0
index 3f4dc66..1e2c52b 100644
@@ -299,6 +299,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= cm_t3517_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-devkit8000.c +1 -0
index 8d362dd..d8a02be 100644
@@ -666,6 +666,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= devkit8000_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= devkit8000_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
arch/arm/mach-omap2/board-generic.c +1 -0
index 7ac5462..dd2a5c2 100644
@@ -70,6 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
 	.map_io		= omap_generic_map_io,
 	.init_early	= omap_generic_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-h4.c +1 -0
index f0ddc27..e75f09f 100644
@@ -381,6 +381,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
 	.map_io		= omap_h4_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap_h4_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_h4_init,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-igep0020.c +2 -0
index d0a3f78..b45d48d 100644
@@ -672,6 +672,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= igep_init,
 	.timer		= &omap3_timer,
 MACHINE_END

@@ -682,6 +683,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= igep_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-ldp.c +1 -0
index 5797917..4a53582 100644
@@ -332,6 +332,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_ldp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-n8x0.c +3 -0
index 4373a6a..49d9cc3 100644
@@ -695,6 +695,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
 	.map_io		= n8x0_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END

@@ -705,6 +706,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
 	.map_io		= n8x0_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END

@@ -715,6 +717,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
 	.map_io		= n8x0_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3beagle.c +1 -0
index 0c49ee7..03af775 100644
@@ -569,6 +569,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3_beagle_init_early,
 	.init_irq	= omap3_beagle_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_beagle_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3evm.c +1 -0
index ec00b2e..f86c1e8 100644
@@ -681,6 +681,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_evm_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3logic.c +2 -0
index 7c0f193..bd65196 100644
@@ -208,6 +208,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3logic_init,
 	.timer		= &omap3_timer,
 MACHINE_END

@@ -217,6 +218,7 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3logic_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3pandora.c +1 -0
index f7811f4..caf607c 100644
@@ -606,6 +606,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3pandora_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3stalker.c +1 -0
index 8ab73af..ca02d2f 100644
@@ -459,6 +459,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
 	.map_io			= omap3_map_io,
 	.init_early		= omap35xx_init_early,
 	.init_irq		= omap3_stalker_init_irq,
+	.handle_irq		= omap3_intc_handle_irq,
 	.init_machine		= omap3_stalker_init,
 	.timer			= &omap3_secure_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3touchbook.c +1 -0
index 5e3e22f..7586e2c 100644
@@ -404,6 +404,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_touchbook_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_touchbook_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap4panda.c +2 -0
index 42d6168..41b2032 100644
@@ -31,6 +31,7 @@
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>

@@ -584,6 +585,7 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
 	.map_io		= omap4_panda_map_io,
 	.init_early	= omap4430_init_early,
 	.init_irq	= gic_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap4_panda_init,
 	.timer		= &omap4_timer,
 MACHINE_END
arch/arm/mach-omap2/board-overo.c +1 -0
index 4cf7aea..9865d8d 100644
@@ -562,6 +562,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= overo_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-rm680.c +1 -0
index d7c8f60..cf9e2db 100644
@@ -155,6 +155,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
 	.map_io		= rm680_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= rm680_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-rx51.c +1 -0
index e2e958a..f777d11 100644
@@ -158,6 +158,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
 	.map_io		= rx51_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= rx51_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-zoom.c +2 -0
index be6684d..011b2e3 100644
@@ -135,6 +135,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_zoom_init,
 	.timer		= &omap3_timer,
 MACHINE_END

@@ -145,6 +146,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_zoom_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/include/mach/entry-macro.S +0 -137

146 lines not on this page · raw message

arch/arm/plat-omap/Kconfig +1 -0
index fa62037..c39cbca 100644
@@ -22,6 +22,7 @@ config ARCH_OMAP2PLUS
 	select CLKDEV_LOOKUP
 	select GENERIC_IRQ_CHIP
 	select OMAP_DM_TIMER
+	select MULTI_IRQ_HANDLER
 	help
 	  "Systems based on OMAP2, OMAP3 or OMAP4"
Signature · 1 line
1.7.0.4
author
#19 lore raw

RFC PATCH 14/14 ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

In reply to Marc Zyngier

Now that MULTI_IRQ_HANDLER is selected by all the in-tree GIC users, make it mandatory and remove the unused macros.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                |    3 -
 arch/arm/common/Kconfig                         |    1 +
 arch/arm/common/gic.c                           |    2 +-
 arch/arm/include/asm/hardware/entry-macro-gic.S |   60 -----------------------
 arch/arm/include/asm/hardware/gic.h             |    1 -
 arch/arm/mach-msm/Kconfig                       |    2 -
 arch/arm/mach-omap2/Kconfig                     |    1 +
 arch/arm/mach-tegra/Kconfig                     |    1 -
 arch/arm/mach-ux500/Kconfig                     |    1 -
 arch/arm/plat-omap/Kconfig                      |    1 -
 10 files changed, 3 insertions(+), 70 deletions(-)
 delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/Kconfig +0 -3
index 0514264..d3e246c 100644
@@ -334,7 +334,6 @@ config ARCH_CNS3XXX
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
 	select PCI_DOMAINS if PCI
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for Cavium Networks CNS3XXX platform.
 

@@ -788,7 +787,6 @@ config ARCH_EXYNOS4
 	select HAVE_S3C_RTC if RTC_CLASS
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select MULTI_IRQ_HANDLER
 	help
 	  Samsung EXYNOS4 series based systems
 

@@ -911,7 +909,6 @@ config ARCH_ZYNQ
 	select ARM_AMBA
 	select ICST
 	select USE_OF
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
arch/arm/common/Kconfig +1 -0
index 114a432..de31997 100644
@@ -1,5 +1,6 @@
 config ARM_GIC
 	select IRQ_PERCPU_DEVID
+	select MULTI_IRQ_HANDLER
 	bool
 
 config ARM_VIC
arch/arm/common/gic.c +1 -1
index ea8bfc5..fd285e1 100644
@@ -39,7 +39,7 @@
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 
 /* Address of GIC 0 CPU interface */
-void __iomem *gic_cpu_base_addr __read_mostly;
+static void __iomem *gic_cpu_base_addr __read_mostly;
 
 /*
  * Supported arch specific GIC irq extension.
arch/arm/include/asm/hardware/entry-macro-gic.S deleted +0 -60

60 lines not on this page · raw message

arch/arm/include/asm/hardware/gic.h +0 -1
index 0f454c6..3411d37 100644
@@ -33,7 +33,6 @@
 #define GIC_DIST_SOFTINT		0xf00
 
 #ifndef __ASSEMBLY__
-extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
 
 void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
arch/arm/mach-msm/Kconfig +0 -2
index ba36b74..ebde97f 100644
@@ -50,7 +50,6 @@ config ARCH_MSM8X60
 	select GPIO_MSM_V2
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
-	select MULTI_IRQ_HANDLER
 
 config ARCH_MSM8960
 	bool "MSM8960"

@@ -61,7 +60,6 @@ config ARCH_MSM8960
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
-	select MULTI_IRQ_HANDLER
 
 endchoice
arch/arm/mach-omap2/Kconfig +1 -0
index 4c5b01d..9e29f9d 100644
@@ -36,6 +36,7 @@ config ARCH_OMAP3
 	select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
+	select MULTI_IRQ_HANDLER
 
 config ARCH_OMAP4
 	bool "TI OMAP4"
arch/arm/mach-tegra/Kconfig +0 -1
index ba0ac3f..d82ebab 100644
@@ -13,7 +13,6 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
arch/arm/mach-ux500/Kconfig +0 -1
index bb2b52b..a3e0c86 100644
@@ -7,7 +7,6 @@ config UX500_SOC_COMMON
 	select HAS_MTU
 	select ARM_ERRATA_753970
 	select ARM_ERRATA_754322
-	select MULTI_IRQ_HANDLER
 
 menu "Ux500 SoC"
arch/arm/plat-omap/Kconfig +0 -1
index c39cbca..fa62037 100644
@@ -22,7 +22,6 @@ config ARCH_OMAP2PLUS
 	select CLKDEV_LOOKUP
 	select GENERIC_IRQ_CHIP
 	select OMAP_DM_TIMER
-	select MULTI_IRQ_HANDLER
 	help
 	  "Systems based on OMAP2, OMAP3 or OMAP4"
Signature · 1 line
1.7.0.4