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i.MX: use CONFIG_MULTI_IRQ_HANDLER

PATCH Superseded Sascha Hauer 4 participants 12 messages Sep 20, 2011 – Sep 26, 2011

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape

v1 of 2 Superseded Latest is v2 →

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Sascha Hauer

author maintainer
#0 lore raw

PATCH 1/1 i.MX: use CONFIG_MULTI_IRQ_HANDLER

The following series switches the i.MX architecture to use CONFIG_MULTI_IRQ_HANDLER. This allows us to compile a kernel with i.MX3 and i.MX5 support in a later series. Also, it will help with the i.MX6 support which has a different irq controller.

Tested on i.MX27, i.MX35 and i.MX51.

Sascha

Sascha Hauer (4):
ARM i.MX avic: add handle_irq function ARM i.MX tzic: add handle_irq function ARM i.MX boards: use CONFIG_MULTI_IRQ_HANDLER ARM i.MX entry-macro.S: remove now unused code

 arch/arm/Kconfig                             |    1 +
 arch/arm/mach-imx/mach-apf9328.c             |    1 +
 arch/arm/mach-imx/mach-armadillo5x0.c        |    1 +
 arch/arm/mach-imx/mach-bug.c                 |    1 +
 arch/arm/mach-imx/mach-cpuimx27.c            |    1 +
 arch/arm/mach-imx/mach-cpuimx35.c            |    1 +
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c     |    1 +
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c  |    1 +
 arch/arm/mach-imx/mach-imx27ipcam.c          |    1 +
 arch/arm/mach-imx/mach-imx27lite.c           |    1 +
 arch/arm/mach-imx/mach-kzm_arm11_01.c        |    1 +
 arch/arm/mach-imx/mach-mx1ads.c              |    2 +
 arch/arm/mach-imx/mach-mx21ads.c             |    1 +
 arch/arm/mach-imx/mach-mx25_3ds.c            |    1 +
 arch/arm/mach-imx/mach-mx27_3ds.c            |    1 +
 arch/arm/mach-imx/mach-mx27ads.c             |    1 +
 arch/arm/mach-imx/mach-mx31_3ds.c            |    1 +
 arch/arm/mach-imx/mach-mx31ads.c             |    1 +
 arch/arm/mach-imx/mach-mx31lilly.c           |    1 +
 arch/arm/mach-imx/mach-mx31lite.c            |    1 +
 arch/arm/mach-imx/mach-mx31moboard.c         |    1 +
 arch/arm/mach-imx/mach-mx35_3ds.c            |    1 +
 arch/arm/mach-imx/mach-mxt_td60.c            |    1 +
 arch/arm/mach-imx/mach-pca100.c              |    1 +
 arch/arm/mach-imx/mach-pcm037.c              |    1 +
 arch/arm/mach-imx/mach-pcm038.c              |    1 +
 arch/arm/mach-imx/mach-pcm043.c              |    1 +
 arch/arm/mach-imx/mach-qong.c                |    1 +
 arch/arm/mach-imx/mach-scb9328.c             |    1 +
 arch/arm/mach-imx/mach-vpr200.c              |    1 +
 arch/arm/mach-mx5/board-cpuimx51.c           |    1 +
 arch/arm/mach-mx5/board-cpuimx51sd.c         |    1 +
 arch/arm/mach-mx5/board-mx50_rdp.c           |    1 +
 arch/arm/mach-mx5/board-mx51_3ds.c           |    1 +
 arch/arm/mach-mx5/board-mx51_babbage.c       |    1 +
 arch/arm/mach-mx5/board-mx51_efikamx.c       |    1 +
 arch/arm/mach-mx5/board-mx51_efikasb.c       |    1 +
 arch/arm/mach-mx5/board-mx53_ard.c           |    1 +
 arch/arm/mach-mx5/board-mx53_evk.c           |    1 +
 arch/arm/mach-mx5/board-mx53_loco.c          |    1 +
 arch/arm/mach-mx5/board-mx53_smd.c           |    1 +
 arch/arm/plat-mxc/avic.c                     |   13 ++++++
 arch/arm/plat-mxc/include/mach/common.h      |   14 ++++++
 arch/arm/plat-mxc/include/mach/entry-macro.S |   58 +-------------------------
 arch/arm/plat-mxc/tzic.c                     |   24 ++++++++++-
 45 files changed, 93 insertions(+), 58 deletions(-)
author maintainer
#1 lore raw

PATCH 1/4 ARM i.MX avic: add handle_irq function

Signed-off-by Sascha Hauer <[email protected]>
---
 arch/arm/plat-mxc/avic.c                |   13 +++++++++++++
 arch/arm/plat-mxc/include/mach/common.h |   10 ++++++++++
 2 files changed, 23 insertions(+), 0 deletions(-)
arch/arm/plat-mxc/avic.c +13 -0
index 55d2534..4d68c5a 100644
@@ -116,6 +116,19 @@ static struct mxc_irq_chip mxc_avic_chip = {
 #endif
 };
 
+asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
+{
+	u32 nivector;
+
+	do {
+		nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
+		if (nivector == 0xffff)
+			break;
+
+		handle_IRQ(nivector, regs);
+	} while (1);
+}
+
 /*
  * This function initializes the AVIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions
arch/arm/plat-mxc/include/mach/common.h +10 -0
index 4e3d978..8de0d0c 100644
@@ -72,4 +72,14 @@ extern void mxc_arch_reset_init(void __iomem *);
 extern void mx51_efikamx_reset(void);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
+
+void avic_handle_irq(struct pt_regs *);
+
+#define mx1_handle_irq avic_handle_irq
+#define mx21_handle_irq avic_handle_irq
+#define mx25_handle_irq avic_handle_irq
+#define mx27_handle_irq avic_handle_irq
+#define mx31_handle_irq avic_handle_irq
+#define mx35_handle_irq avic_handle_irq
+
 #endif
Signature · 1 line
1.7.6.3
author maintainer
#2 lore raw

PATCH 2/4 ARM i.MX tzic: add handle_irq function

In reply to Sascha Hauer
Signed-off-by Sascha Hauer <[email protected]>
---
 arch/arm/plat-mxc/include/mach/common.h |    4 ++++
 arch/arm/plat-mxc/tzic.c                |   24 +++++++++++++++++++++++-
 2 files changed, 27 insertions(+), 1 deletions(-)
arch/arm/plat-mxc/include/mach/common.h +4 -0
index 8de0d0c..2e8802b 100644
@@ -74,6 +74,7 @@ extern int mx53_revision(void);
 extern int mx53_display_revision(void);
 
 void avic_handle_irq(struct pt_regs *);
+void tzic_handle_irq(struct pt_regs *);
 
 #define mx1_handle_irq avic_handle_irq
 #define mx21_handle_irq avic_handle_irq

@@ -81,5 +82,8 @@ void avic_handle_irq(struct pt_regs *);
 #define mx27_handle_irq avic_handle_irq
 #define mx31_handle_irq avic_handle_irq
 #define mx35_handle_irq avic_handle_irq
+#define mx50_handle_irq tzic_handle_irq
+#define mx51_handle_irq tzic_handle_irq
+#define mx53_handle_irq tzic_handle_irq
 
 #endif
arch/arm/plat-mxc/tzic.c +23 -1
index f257fcc..b7a272d 100644
@@ -42,7 +42,7 @@
 #define TZIC_SRCCLAR0	0x0280	/* Source Clear Register 0 */
 #define TZIC_PRIORITY0	0x0400	/* Priority Register 0 */
 #define TZIC_PND0	0x0D00	/* Pending Register 0 */
-#define TZIC_HIPND0	0x0D80	/* High Priority Pending Register */
+#define TZIC_HIPND(i)	(0x0D80+ ((i) << 2))	/* High Priority Pending Register */
 #define TZIC_WAKEUP0(i)	(0x0E00 + ((i) << 2))	/* Wakeup Config Register */
 #define TZIC_SWINT	0x0F00	/* Software Interrupt Rigger Register */
 #define TZIC_ID0	0x0FD0	/* Indentification Register 0 */

@@ -96,6 +96,28 @@ static __init void tzic_init_gc(unsigned int irq_start)
 	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
 
+asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
+{
+	u32 stat;
+	int i, irqofs, handled;
+
+	do {
+		handled = 0;
+
+		for (i = 0; i < 4; i++) {
+			stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
+				__raw_readl(tzic_base + TZIC_INTSEC0(i));
+
+			while (stat) {
+				handled = 1;
+				irqofs = fls(stat) - 1;
+				handle_IRQ(irqofs + i * 32, regs);
+				stat &= ~(1 << irqofs);
+			}
+		}
+	} while (handled);
+}
+
 /*
  * This function initializes the TZIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions
Signature · 1 line
1.7.6.3
#3 lore raw

PATCH 2/4 ARM i.MX tzic: add handle_irq function

Quoted 19 lines · Sascha Hauer
Signed-off-by Sascha Hauer <[email protected]>
---
 arch/arm/plat-mxc/include/mach/common.h |    4 ++++
 arch/arm/plat-mxc/tzic.c                |   24 +++++++++++++++++++++++-
 2 files changed, 27 insertions(+), 1 deletions(-)
arch/arm/plat-mxc/include/mach/common.h +1 -0
index 8de0d0c..2e8802b 100644
@@ -74,6 +74,7 @@ extern int mx53_revision(void);
 extern int mx53_display_revision(void);
 
 void avic_handle_irq(struct pt_regs *);
+void tzic_handle_irq(struct pt_regs *);
 
 #define mx1_handle_irq avic_handle_irq
 #define mx21_handle_irq avic_handle_irq

arch/arm/plat-mxc/include/mach/common.h void avic_handle_irq(struct pt_regs *); · line 88

Quoted 7 lines
arch/arm/plat-mxc/include/mach/common.h +3 -0
@@ -81,5 +82,8 @@ void avic_handle_irq(struct pt_regs *);
 #define mx27_handle_irq avic_handle_irq
 #define mx31_handle_irq avic_handle_irq
 #define mx35_handle_irq avic_handle_irq
+#define mx50_handle_irq tzic_handle_irq
+#define mx51_handle_irq tzic_handle_irq
+#define mx53_handle_irq tzic_handle_irq

Can we start forcing the consistent file/function naming between mx* and imx*? I bet imx* will win :)

Signature · 2 lines
Regards,
Shawn
author maintainer
#4 lore raw

PATCH 3/4 ARM i.MX boards: use CONFIG_MULTI_IRQ_HANDLER

In reply to Sascha Hauer

Also, add handle_irq callbacks to machine descriptors.

Signed-off-by Sascha Hauer <[email protected]>
---
 arch/arm/Kconfig                            |    1 +
 arch/arm/mach-imx/mach-apf9328.c            |    1 +
 arch/arm/mach-imx/mach-armadillo5x0.c       |    1 +
 arch/arm/mach-imx/mach-bug.c                |    1 +
 arch/arm/mach-imx/mach-cpuimx27.c           |    1 +
 arch/arm/mach-imx/mach-cpuimx35.c           |    1 +
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c    |    1 +
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c |    1 +
 arch/arm/mach-imx/mach-imx27ipcam.c         |    1 +
 arch/arm/mach-imx/mach-imx27lite.c          |    1 +
 arch/arm/mach-imx/mach-kzm_arm11_01.c       |    1 +
 arch/arm/mach-imx/mach-mx1ads.c             |    2 ++
 arch/arm/mach-imx/mach-mx21ads.c            |    1 +
 arch/arm/mach-imx/mach-mx25_3ds.c           |    1 +
 arch/arm/mach-imx/mach-mx27_3ds.c           |    1 +
 arch/arm/mach-imx/mach-mx27ads.c            |    1 +
 arch/arm/mach-imx/mach-mx31_3ds.c           |    1 +
 arch/arm/mach-imx/mach-mx31ads.c            |    1 +
 arch/arm/mach-imx/mach-mx31lilly.c          |    1 +
 arch/arm/mach-imx/mach-mx31lite.c           |    1 +
 arch/arm/mach-imx/mach-mx31moboard.c        |    1 +
 arch/arm/mach-imx/mach-mx35_3ds.c           |    1 +
 arch/arm/mach-imx/mach-mxt_td60.c           |    1 +
 arch/arm/mach-imx/mach-pca100.c             |    1 +
 arch/arm/mach-imx/mach-pcm037.c             |    1 +
 arch/arm/mach-imx/mach-pcm038.c             |    1 +
 arch/arm/mach-imx/mach-pcm043.c             |    1 +
 arch/arm/mach-imx/mach-qong.c               |    1 +
 arch/arm/mach-imx/mach-scb9328.c            |    1 +
 arch/arm/mach-imx/mach-vpr200.c             |    1 +
 arch/arm/mach-mx5/board-cpuimx51.c          |    1 +
 arch/arm/mach-mx5/board-cpuimx51sd.c        |    1 +
 arch/arm/mach-mx5/board-mx50_rdp.c          |    1 +
 arch/arm/mach-mx5/board-mx51_3ds.c          |    1 +
 arch/arm/mach-mx5/board-mx51_babbage.c      |    1 +
 arch/arm/mach-mx5/board-mx51_efikamx.c      |    1 +
 arch/arm/mach-mx5/board-mx51_efikasb.c      |    1 +
 arch/arm/mach-mx5/board-mx53_ard.c          |    1 +
 arch/arm/mach-mx5/board-mx53_evk.c          |    1 +
 arch/arm/mach-mx5/board-mx53_loco.c         |    1 +
 arch/arm/mach-mx5/board-mx53_smd.c          |    1 +
 41 files changed, 42 insertions(+), 0 deletions(-)
arch/arm/Kconfig +1 -0
index 5ebc5d9..975b5dd 100644
@@ -397,6 +397,7 @@ config ARCH_MXC
 	select CLKSRC_MMIO
 	select GENERIC_IRQ_CHIP
 	select HAVE_SCHED_CLOCK
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for Freescale MXC/iMX-based family of processors
arch/arm/mach-imx/mach-apf9328.c +1 -0
index a404c89..e5154f5 100644
@@ -136,6 +136,7 @@ MACHINE_START(APF9328, "Armadeus APF9328")
 	.map_io       = mx1_map_io,
 	.init_early   = imx1_init_early,
 	.init_irq     = mx1_init_irq,
+	.handle_irq   = mx1_handle_irq,
 	.timer        = &apf9328_timer,
 	.init_machine = apf9328_init,
 MACHINE_END
arch/arm/mach-imx/mach-armadillo5x0.c +1 -0
index ede2710..88c77f5 100644
@@ -562,6 +562,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &armadillo5x0_timer,
 	.init_machine = armadillo5x0_init,
 MACHINE_END
arch/arm/mach-imx/mach-bug.c +1 -0
index f494705..c44b236 100644
@@ -62,6 +62,7 @@ MACHINE_START(BUG, "BugLabs BUGBase")
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &bug_timer,
 	.init_machine = bug_board_init,
 MACHINE_END
arch/arm/mach-imx/mach-cpuimx27.c +1 -0
index 87887ac..21d3d81 100644
@@ -315,6 +315,7 @@ MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
 	.map_io = mx27_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.timer = &eukrea_cpuimx27_timer,
 	.init_machine = eukrea_cpuimx27_init,
 MACHINE_END
arch/arm/mach-imx/mach-cpuimx35.c +1 -0
index f39a478b..251830b 100644
@@ -198,6 +198,7 @@ MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
 	.map_io = mx35_map_io,
 	.init_early = imx35_init_early,
 	.init_irq = mx35_init_irq,
+	.handle_irq = mx35_handle_irq,
 	.timer = &eukrea_cpuimx35_timer,
 	.init_machine = eukrea_cpuimx35_init,
 MACHINE_END
arch/arm/mach-imx/mach-eukrea_cpuimx25.c +1 -0
index da36da5..c192f2a 100644
@@ -167,6 +167,7 @@ MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
 	.map_io = mx25_map_io,
 	.init_early = imx25_init_early,
 	.init_irq = mx25_init_irq,
+	.handle_irq = mx25_handle_irq,
 	.timer = &eukrea_cpuimx25_timer,
 	.init_machine = eukrea_cpuimx25_init,
 MACHINE_END
arch/arm/mach-imx/mach-imx27_visstrim_m10.c +1 -0
index 6778f81..8edbdde 100644
@@ -279,6 +279,7 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
 	.map_io = mx27_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.timer = &visstrim_m10_timer,
 	.init_machine = visstrim_m10_board_init,
 MACHINE_END
arch/arm/mach-imx/mach-imx27ipcam.c +1 -0
index 272f793..9a8cc1d 100644
@@ -75,6 +75,7 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
 	.map_io = mx27_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.timer = &mx27ipcam_timer,
 	.init_machine = mx27ipcam_init,
 MACHINE_END
arch/arm/mach-imx/mach-imx27lite.c +1 -0
index d81a769..4d78b0e 100644
@@ -81,6 +81,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
 	.map_io = mx27_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.timer = &mx27lite_timer,
 	.init_machine = mx27lite_init,
 MACHINE_END
arch/arm/mach-imx/mach-kzm_arm11_01.c +1 -0
index e472a1d..5bce476 100644
@@ -275,6 +275,7 @@ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
 	.map_io = kzm_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &kzm_timer,
 	.init_machine = kzm_board_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx1ads.c +2 -0
index 5cd8bee..dbfe645 100644
@@ -149,6 +149,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
 	.map_io = mx1_map_io,
 	.init_early = imx1_init_early,
 	.init_irq = mx1_init_irq,
+	.handle_irq = mx1_handle_irq,
 	.timer = &mx1ads_timer,
 	.init_machine = mx1ads_init,
 MACHINE_END

@@ -158,6 +159,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
 	.map_io = mx1_map_io,
 	.init_early = imx1_init_early,
 	.init_irq = mx1_init_irq,
+	.handle_irq = mx1_handle_irq,
 	.timer = &mx1ads_timer,
 	.init_machine = mx1ads_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx21ads.c +1 -0
index d389ecf..9955c2a 100644
@@ -309,6 +309,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
 	.map_io = mx21ads_map_io,
 	.init_early = imx21_init_early,
 	.init_irq = mx21_init_irq,
+	.handle_irq = mx21_handle_irq,
 	.timer = &mx21ads_timer,
 	.init_machine = mx21ads_board_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx25_3ds.c +1 -0
index 7f66a91..1d06af1 100644
@@ -257,6 +257,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
 	.map_io = mx25_map_io,
 	.init_early = imx25_init_early,
 	.init_irq = mx25_init_irq,
+	.handle_irq = mx25_handle_irq,
 	.timer = &mx25pdk_timer,
 	.init_machine = mx25pdk_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx27_3ds.c +1 -0
index 6fa6934..01e4994 100644
@@ -425,6 +425,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
 	.map_io = mx27_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.timer = &mx27pdk_timer,
 	.init_machine = mx27pdk_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx27ads.c +1 -0
index fc26ed7..f85fb61 100644
@@ -349,6 +349,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
 	.map_io = mx27ads_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.timer = &mx27ads_timer,
 	.init_machine = mx27ads_board_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx31_3ds.c +1 -0
index c20be75..644a787 100644
@@ -768,6 +768,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &mx31_3ds_timer,
 	.init_machine = mx31_3ds_init,
 	.reserve = mx31_3ds_reserve,
arch/arm/mach-imx/mach-mx31ads.c +1 -0
index 29ca890..463cdcf 100644
@@ -539,6 +539,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
 	.map_io = mx31ads_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31ads_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &mx31ads_timer,
 	.init_machine = mx31ads_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx31lilly.c +1 -0
index 126913a..659de08cd 100644
@@ -299,6 +299,7 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &mx31lilly_timer,
 	.init_machine = mx31lilly_board_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx31lite.c +1 -0
index 4b47fd9..225fa56 100644
@@ -284,6 +284,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
 	.map_io = mx31lite_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &mx31lite_timer,
 	.init_machine = mx31lite_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx31moboard.c +1 -0
index b358383..91aed2b 100644
@@ -572,6 +572,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &mx31moboard_timer,
 	.init_machine = mx31moboard_init,
 MACHINE_END
arch/arm/mach-imx/mach-mx35_3ds.c +1 -0
index b3b9bd8..912b1bc 100644
@@ -221,6 +221,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
 	.map_io = mx35_map_io,
 	.init_early = imx35_init_early,
 	.init_irq = mx35_init_irq,
+	.handle_irq = mx35_handle_irq,
 	.timer = &mx35pdk_timer,
 	.init_machine = mx35_3ds_init,
 MACHINE_END
arch/arm/mach-imx/mach-mxt_td60.c +1 -0
index c85876f..40f573f 100644
@@ -271,6 +271,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
 	.map_io = mx27_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.timer = &mxt_td60_timer,
 	.init_machine = mxt_td60_board_init,
 MACHINE_END
arch/arm/mach-imx/mach-pca100.c +1 -0
index 71083aa..945d2e2 100644
@@ -439,6 +439,7 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
 	.map_io = mx27_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.init_machine = pca100_init,
 	.timer = &pca100_timer,
 MACHINE_END
arch/arm/mach-imx/mach-pcm037.c +1 -0
index f45b7cd..05b2077 100644
@@ -693,6 +693,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &pcm037_timer,
 	.init_machine = pcm037_init,
 MACHINE_END
arch/arm/mach-imx/mach-pcm038.c +1 -0
index 2d6a64b..5da3c4f 100644
@@ -353,6 +353,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
 	.map_io = mx27_map_io,
 	.init_early = imx27_init_early,
 	.init_irq = mx27_init_irq,
+	.handle_irq = mx27_handle_irq,
 	.timer = &pcm038_timer,
 	.init_machine = pcm038_init,
 MACHINE_END
arch/arm/mach-imx/mach-pcm043.c +1 -0
index 660ec3e..ad28006 100644
@@ -422,6 +422,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
 	.map_io = mx35_map_io,
 	.init_early = imx35_init_early,
 	.init_irq = mx35_init_irq,
+	.handle_irq = mx35_handle_irq,
 	.timer = &pcm043_timer,
 	.init_machine = pcm043_init,
 MACHINE_END
arch/arm/mach-imx/mach-qong.c +1 -0
index 3626f48..9afcdb6 100644
@@ -266,6 +266,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
 	.map_io = mx31_map_io,
 	.init_early = imx31_init_early,
 	.init_irq = mx31_init_irq,
+	.handle_irq = mx31_handle_irq,
 	.timer = &qong_timer,
 	.init_machine = qong_init,
 MACHINE_END
arch/arm/mach-imx/mach-scb9328.c +1 -0
index db2d604..f6d3b73 100644
@@ -141,6 +141,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
 	.map_io = mx1_map_io,
 	.init_early = imx1_init_early,
 	.init_irq = mx1_init_irq,
+	.handle_irq = mx1_handle_irq,
 	.timer = &scb9328_timer,
 	.init_machine = scb9328_init,
 MACHINE_END
arch/arm/mach-imx/mach-vpr200.c +1 -0
index 7d8e012..4c577a5 100644
@@ -319,6 +319,7 @@ MACHINE_START(VPR200, "VPR200")
 	.map_io = mx35_map_io,
 	.init_early = imx35_init_early,
 	.init_irq = mx35_init_irq,
+	.handle_irq = mx35_handle_irq,
 	.timer = &vpr200_timer,
 	.init_machine = vpr200_board_init,
 MACHINE_END
arch/arm/mach-mx5/board-cpuimx51.c +1 -0
index 68934ea..e6d919e 100644
@@ -297,6 +297,7 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
 	.map_io = mx51_map_io,
 	.init_early = imx51_init_early,
 	.init_irq = mx51_init_irq,
+	.handle_irq = mx51_handle_irq,
 	.timer = &mxc_timer,
 	.init_machine = eukrea_cpuimx51_init,
 MACHINE_END
arch/arm/mach-mx5/board-cpuimx51sd.c +1 -0
index ff096d5..32e07d6 100644
@@ -335,6 +335,7 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
 	.map_io = mx51_map_io,
 	.init_early = imx51_init_early,
 	.init_irq = mx51_init_irq,
+	.handle_irq = mx51_handle_irq,
 	.timer = &mxc_timer,
 	.init_machine = eukrea_cpuimx51sd_init,
 MACHINE_END
arch/arm/mach-mx5/board-mx50_rdp.c +1 -0
index 7de25c6..bef945e 100644
@@ -219,6 +219,7 @@ MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
 	.map_io = mx50_map_io,
 	.init_early = imx50_init_early,
 	.init_irq = mx50_init_irq,
+	.handle_irq = mx50_handle_irq,
 	.timer = &mx50_rdp_timer,
 	.init_machine = mx50_rdp_board_init,
 MACHINE_END
arch/arm/mach-mx5/board-mx51_3ds.c +1 -0
index 07a3815..cf9537e 100644
@@ -173,6 +173,7 @@ MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
 	.map_io = mx51_map_io,
 	.init_early = imx51_init_early,
 	.init_irq = mx51_init_irq,
+	.handle_irq = mx51_handle_irq,
 	.timer = &mx51_3ds_timer,
 	.init_machine = mx51_3ds_init,
 MACHINE_END
arch/arm/mach-mx5/board-mx51_babbage.c +1 -0
index 11b0ff6..16db947 100644
@@ -420,6 +420,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
 	.map_io = mx51_map_io,
 	.init_early = imx51_init_early,
 	.init_irq = mx51_init_irq,
+	.handle_irq = mx51_handle_irq,
 	.timer = &mx51_babbage_timer,
 	.init_machine = mx51_babbage_init,
 MACHINE_END
arch/arm/mach-mx5/board-mx51_efikamx.c +1 -0
index 551daf8..c8415cc 100644
@@ -284,6 +284,7 @@ MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
 	.map_io = mx51_map_io,
 	.init_early = imx51_init_early,
 	.init_irq = mx51_init_irq,
+	.handle_irq = mx51_handle_irq,
 	.timer = &mx51_efikamx_timer,
 	.init_machine = mx51_efikamx_init,
 MACHINE_END
arch/arm/mach-mx5/board-mx51_efikasb.c +1 -0
index 8a9bca2..e720f32 100644
@@ -270,6 +270,7 @@ MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
 	.map_io = mx51_map_io,
 	.init_early = imx51_init_early,
 	.init_irq = mx51_init_irq,
+	.handle_irq = mx51_handle_irq,
 	.init_machine =  efikasb_board_init,
 	.timer = &mx51_efikasb_timer,
 MACHINE_END
arch/arm/mach-mx5/board-mx53_ard.c +1 -0
index 76a67c4..9d8aa8c 100644
@@ -249,6 +249,7 @@ MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
 	.map_io = mx53_map_io,
 	.init_early = imx53_init_early,
 	.init_irq = mx53_init_irq,
+	.handle_irq = mx53_handle_irq,
 	.timer = &mx53_ard_timer,
 	.init_machine = mx53_ard_board_init,
 MACHINE_END
arch/arm/mach-mx5/board-mx53_evk.c +1 -0
index 1b417b0..c74a608 100644
@@ -167,6 +167,7 @@ MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
 	.map_io = mx53_map_io,
 	.init_early = imx53_init_early,
 	.init_irq = mx53_init_irq,
+	.handle_irq = mx53_handle_irq,
 	.timer = &mx53_evk_timer,
 	.init_machine = mx53_evk_board_init,
 MACHINE_END
arch/arm/mach-mx5/board-mx53_loco.c +1 -0
index 4e1d51d..e43493d 100644
@@ -288,6 +288,7 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
 	.map_io = mx53_map_io,
 	.init_early = imx53_init_early,
 	.init_irq = mx53_init_irq,
+	.handle_irq = mx53_handle_irq,
 	.timer = &mx53_loco_timer,
 	.init_machine = mx53_loco_board_init,
 MACHINE_END
arch/arm/mach-mx5/board-mx53_smd.c +1 -0
index bc02894..25f686a 100644
@@ -140,6 +140,7 @@ MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
 	.map_io = mx53_map_io,
 	.init_early = imx53_init_early,
 	.init_irq = mx53_init_irq,
+	.handle_irq = mx53_handle_irq,
 	.timer = &mx53_smd_timer,
 	.init_machine = mx53_smd_board_init,
 MACHINE_END
Signature · 1 line
1.7.6.3
author maintainer
#5 lore raw

PATCH 4/4 ARM i.MX entry-macro.S: remove now unused code

In reply to Sascha Hauer
Signed-off-by Sascha Hauer <[email protected]>
---
 arch/arm/plat-mxc/include/mach/entry-macro.S |   58 +-------------------------
 1 files changed, 1 insertions(+), 57 deletions(-)
arch/arm/plat-mxc/include/mach/entry-macro.S +1 -57
index 066d464..842fbcb 100644
@@ -9,72 +9,16 @@
  * published by the Free Software Foundation.
  */
 
-#include <mach/hardware.h>
+/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */
 
-#define AVIC_NIMASK	0x04
-
-	@ this macro disables fast irq (not implemented)
 	.macro	disable_fiq
 	.endm
 
 	.macro  get_irqnr_preamble, base, tmp
-#ifndef CONFIG_MXC_TZIC
-	ldr	\base, =avic_base
-	ldr	\base, [\base]
-#ifdef CONFIG_MXC_IRQ_PRIOR
-	ldr	r4, [\base, #AVIC_NIMASK]
-#endif
-#elif defined CONFIG_MXC_TZIC
-	ldr	\base, =tzic_base
-	ldr	\base, [\base]
-#endif /* CONFIG_MXC_TZIC */
 	.endm
 
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
 
-	@ this macro checks which interrupt occurred
-	@ and returns its number in irqnr
-	@ and returns if an interrupt occurred in irqstat
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-#ifndef CONFIG_MXC_TZIC
-	@ Load offset & priority of the highest priority
-	@ interrupt pending from AVIC_NIVECSR
-	ldr	\irqstat, [\base, #0x40]
-	@ Shift to get the decoded IRQ number, using ASR so
-	@ 'no interrupt pending' becomes 0xffffffff
-	mov	\irqnr, \irqstat, asr #16
-	@ set zero flag if IRQ + 1 == 0
-	adds	\tmp, \irqnr, #1
-#ifdef CONFIG_MXC_IRQ_PRIOR
-	bicne	\tmp, \irqstat, #0xFFFFFFE0
-	strne	\tmp, [\base, #AVIC_NIMASK]
-	streq	r4, [\base, #AVIC_NIMASK]
-#endif
-#elif defined CONFIG_MXC_TZIC
-	@ Load offset & priority of the highest priority
-	@ interrupt pending.
-	@ 0x080 is INTSEC0 register
-	@ 0xD80 is HIPND0 register
-	mov     \irqnr, #0
-1000:	add	\irqstat, \base, \irqnr, lsr #3
-	ldr	\tmp, [\irqstat, #0xd80]
-	ldr	\irqstat, [\irqstat, #0x080]
-	ands	\tmp, \tmp, \irqstat
-	bne	1001f
-	add	\irqnr, \irqnr, #32
-	cmp     \irqnr, #128
-	blo     1000b
-	b       2001f
-1001:	mov     \irqstat, #1
-1002:	tst     \tmp, \irqstat
-	bne     2002f
-	movs    \tmp, \tmp, lsr #1
-	addne   \irqnr, \irqnr, #1
-	bne     1002b
-2001:
-	mov  \irqnr, #0
-2002:
-	movs \irqnr, \irqnr
-#endif
 	.endm
Signature · 1 line
1.7.6.3
#6 lore raw

PATCH 1/1 ARM i.MX gic: add handle_irq function

In reply to Sascha Hauer

This is a plain translation of assembly gic irq handler to C function for CONFIG_MULTI_IRQ_HANDLER support on imx family.

As the speed of gic_handle_irq() is much more important than code clean, the patch chooses to plug the ifdef in the function to compile out the corresponding codes.

Signed-off-by Shawn Guo <[email protected]>

---
Right, ideally the arch/arm/plat-mxc/gic.c should be merged into arch/arm/common/gic.c. But before rmk asks me to do that, I would let it stay in imx platform.

 arch/arm/plat-mxc/Makefile                   |    2 +-
 arch/arm/plat-mxc/gic.c                      |   47 ++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h      |    2 +
 arch/arm/plat-mxc/include/mach/entry-macro.S |    6 +++
 4 files changed, 56 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/plat-mxc/gic.c
arch/arm/plat-mxc/Makefile +1 -1
index d53c35f..b9f0f5f 100644
@@ -5,7 +5,7 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
 
-# MX51 uses the TZIC interrupt controller, older platforms use AVIC
+obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
arch/arm/plat-mxc/gic.c new file +47 -0

47 lines not on this page · raw message

arch/arm/plat-mxc/include/mach/common.h +2 -0
index 2e8802b..49cad2a 100644
@@ -75,6 +75,7 @@ extern int mx53_display_revision(void);
 
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
+void gic_handle_irq(struct pt_regs *);
 
 #define mx1_handle_irq avic_handle_irq
 #define mx21_handle_irq avic_handle_irq

@@ -85,5 +86,6 @@ void tzic_handle_irq(struct pt_regs *);
 #define mx50_handle_irq tzic_handle_irq
 #define mx51_handle_irq tzic_handle_irq
 #define mx53_handle_irq tzic_handle_irq
+#define imx6q_handle_irq gic_handle_irq
 
 #endif
arch/arm/plat-mxc/include/mach/entry-macro.S +6 -0
index 842fbcb..9fe0dfc 100644
@@ -22,3 +22,9 @@
 
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	.endm
+
+	.macro test_for_ipi, irqnr, irqstat, base, tmp
+	.endm
+
+	.macro test_for_ltirq, irqnr, irqstat, base, tmp
+	.endm
Signature · 1 line
1.7.4.1
author maintainer
#7 lore raw

PATCH 1/1 ARM i.MX gic: add handle_irq function

Quoted 76 lines · Shawn Guo

This is a plain translation of assembly gic irq handler to C function for CONFIG_MULTI_IRQ_HANDLER support on imx family.

As the speed of gic_handle_irq() is much more important than code clean, the patch chooses to plug the ifdef in the function to compile out the corresponding codes.

Signed-off-by Shawn Guo <[email protected]>

---
Right, ideally the arch/arm/plat-mxc/gic.c should be merged into arch/arm/common/gic.c. But before rmk asks me to do that, I would let it stay in imx platform.

 arch/arm/plat-mxc/Makefile                   |    2 +-
 arch/arm/plat-mxc/gic.c                      |   47 ++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h      |    2 +
 arch/arm/plat-mxc/include/mach/entry-macro.S |    6 +++
 4 files changed, 56 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/plat-mxc/gic.c
arch/arm/plat-mxc/Makefile +1 -1
index d53c35f..b9f0f5f 100644
@@ -5,7 +5,7 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
 
-# MX51 uses the TZIC interrupt controller, older platforms use AVIC
+obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
arch/arm/plat-mxc/gic.c new file +37 -0
new file mode 100644
index 0000000..487d12c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
+#ifdef CONFIG_SMP
+#include <asm/smp.h>
+#endif
+
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+		irqnr = irqstat & 0x3ff;
+		if (irqnr == 1023)
+			break;
+
+		if (irqnr > 29 && irqnr < 1021)
+			handle_IRQ(irqnr, regs);
+#ifdef CONFIG_SMP
+		else if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			do_IPI(irqnr, regs);
+		}

arch/arm/plat-mxc/gic.c line 47

Quoted 10 lines
arch/arm/plat-mxc/gic.c new file +10 -0
+#endif
+#ifdef CONFIG_LOCAL_TIMERS
+		else if (irqnr == 29) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			do_local_timer(regs);
+		}
+#endif
+	} while (1);
+}

Shouldn't this code go to arch/arm/common/gic.c instead? The corresponding assembly code is generic so I see no reason to make this i.MX specific.

Sascha

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
#8 lore raw

PATCH 1/1 ARM i.MX gic: add handle_irq function

Quoted 83 lines · Sascha Hauer
Quoted 82 lines · Shawn Guo

This is a plain translation of assembly gic irq handler to C function for CONFIG_MULTI_IRQ_HANDLER support on imx family.

As the speed of gic_handle_irq() is much more important than code clean, the patch chooses to plug the ifdef in the function to compile out the corresponding codes.

Signed-off-by Shawn Guo <[email protected]>

---
Right, ideally the arch/arm/plat-mxc/gic.c should be merged into arch/arm/common/gic.c. But before rmk asks me to do that, I would let it stay in imx platform.

 arch/arm/plat-mxc/Makefile                   |    2 +-
 arch/arm/plat-mxc/gic.c                      |   47 ++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h      |    2 +
 arch/arm/plat-mxc/include/mach/entry-macro.S |    6 +++
 4 files changed, 56 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/plat-mxc/gic.c
arch/arm/plat-mxc/Makefile +1 -1
index d53c35f..b9f0f5f 100644
@@ -5,7 +5,7 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
 
-# MX51 uses the TZIC interrupt controller, older platforms use AVIC
+obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
arch/arm/plat-mxc/gic.c new file +43 -0
new file mode 100644
index 0000000..487d12c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
+#ifdef CONFIG_SMP
+#include <asm/smp.h>
+#endif
+
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+		irqnr = irqstat & 0x3ff;
+		if (irqnr == 1023)
+			break;
+
+		if (irqnr > 29 && irqnr < 1021)
+			handle_IRQ(irqnr, regs);
+#ifdef CONFIG_SMP
+		else if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			do_IPI(irqnr, regs);
+		}
+#endif
+#ifdef CONFIG_LOCAL_TIMERS
+		else if (irqnr == 29) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			do_local_timer(regs);
Quoted 9 lines

arch/arm/plat-mxc/gic.c line 47

Quoted 4 lines
arch/arm/plat-mxc/gic.c new file +4 -0
+		}
+#endif
+	} while (1);
+}

Shouldn't this code go to arch/arm/common/gic.c instead? The corresponding assembly code is generic so I see no reason to make this i.MX specific.

Yes. I put some notes below '---' about this. Basically, this patch is just a way around to have imx6q catch up with your global move on i.mx CONFIG_MULTI_IRQ_HANDLER support. In the long term, this GIC support should definitely need to be handled by arch/arm/common/gic.c.

Actually, Marc Zyngier has just started posting CONFIG_MULTI_IRQ_HANDLER for GIC. But it depends on his own PPI series, which I'm unsure if it will gets merged in the coming window. I really want to get imx6q merged in v3.2 window, so I would not have Marc's common GIC support as a dependency. We can switch to it once it gets merged.

Signature · 2 lines
Regards,
Shawn
#9 lore raw

PATCH 1/1 ARM i.MX gic: add handle_irq function

In reply to Shawn Guo

arch/arm/plat-mxc/gic.c line 43

Quoted 12 lines · Shawn Guo
arch/arm/plat-mxc/gic.c new file +12 -0
+#ifdef CONFIG_SMP
+		else if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			do_IPI(irqnr, regs);
+		}
+#endif
+#ifdef CONFIG_LOCAL_TIMERS
+		else if (irqnr == 29) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			do_local_timer(regs);

Neither of these two functions are designed to be called from C code. Notice that they are marked __exception or __exception_irq_entry, and thus they expect to have a pt_regs structure directly above themselves.

#10 lore raw

PATCH 1/1 ARM i.MX gic: add handle_irq function

Quoted 18 lines · Russell King - ARM Linux

arch/arm/plat-mxc/gic.c line 43

Quoted 12 lines · Shawn Guo
arch/arm/plat-mxc/gic.c new file +12 -0
+#ifdef CONFIG_SMP
+		else if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			do_IPI(irqnr, regs);
+		}
+#endif
+#ifdef CONFIG_LOCAL_TIMERS
+		else if (irqnr == 29) {
+			writel_relaxed(irqstat, gic_cpu_base_addr +
+						GIC_CPU_EOI);
+			do_local_timer(regs);

Neither of these two functions are designed to be called from C code. Notice that they are marked __exception or __exception_irq_entry, and thus they expect to have a pt_regs structure directly above themselves.

Thanks for the points. Since the testing did not tell any problem, I guess we can use it as a temporary solution before we have a sophisticated implementation available in GIC common code?

Signature · 2 lines
Regards,
Shawn
#11 lore raw

PATCH 1/1 i.MX: use CONFIG_MULTI_IRQ_HANDLER

In reply to Sascha Hauer
Quoted 5 lines · Sascha Hauer

The following series switches the i.MX architecture to use CONFIG_MULTI_IRQ_HANDLER. This allows us to compile a kernel with i.MX3 and i.MX5 support in a later series. Also, it will help with the i.MX6 support which has a different irq controller.

Hi Sascha,

I just sent a patch to get GIC support with CONFIG_MULTI_IRQ_HANDLER based on your series. If the patch looks good to people, you may want to fold it into the series?

Signature · 2 lines
Regards,
Shawn