Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
Subsystems (10)
v2 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
In order to support multiple primary interrupt controllers in the same image, it is necessary to use the MULTI_IRQ_HANDLER config option.
This patch series makes a first step in that direction by:
- having the GIC code to provides a global handler,
- make GIC users to provide this handler from their machine descriptor.
A side effect of this is that it forces OMAP2/3 platforms to be converted too in order to preserve the MULTI_OMAP feature. This leads to a certain simplification of the interrupt handling for the OMAP2/3/4 platforms.
The primary IRQ handlers have been written in C, and the performance degradation is hardly noticeable. Should some tests reveal a major increase in latency, it is always possible to restore the ASM version.
This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-20110926 plus my PPI series.
PATCH v2 1/16 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive
Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code requires the arch_irq_handler_default macro to be defined as a fallback.
It turns out nobody is using that particular feature as both PXA and shmobile have all their machine descriptors populated with the interrupt handler, leaving unused code (or empty macros) in their entry-macro.S file just to be able to compile entry-armv.S.
Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default, which allows to remove one test from the hot path. Also cleanup both PXA and shmobile entry-macro.S.
--- arch/arm/kernel/entry-armv.S | 7 ++-- arch/arm/mach-pxa/include/mach/entry-macro.S | 36 --------------------- arch/arm/mach-shmobile/include/mach/entry-macro.S | 9 ----- 3 files changed, 3 insertions(+), 49 deletions(-)
arch/arm/kernel/entry-armv.S +3 -4
@@ -36,12 +36,11 @@ #ifdef CONFIG_MULTI_IRQ_HANDLER ldr r1, =handle_arch_irq mov r0, sp - ldr r1, [r1] adr lr, BSYM(9997f) - teq r1, #0 - movne pc, r1 -#endif + ldr pc, [r1] +#else arch_irq_handler_default +#endif 9997: .endm
arch/arm/mach-pxa/include/mach/entry-macro.S +0 -36
@@ -7,45 +7,9 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <mach/hardware.h> -#include <mach/irqs.h> .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mrc p15, 0, \tmp, c0, c0, 0 @ CPUID - mov \tmp, \tmp, lsr #13 - and \tmp, \tmp, #0x7 @ Core G - cmp \tmp, #1 - bhi 1002f - - @ Core Generation 1 (PXA25x) - mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 - add \base, \base, #0x00d00000 - ldr \irqstat, [\base, #0] @ ICIP - ldr \irqnr, [\base, #4] @ ICMR - - ands \irqnr, \irqstat, \irqnr - beq 1001f - rsb \irqstat, \irqnr, #0 - and \irqstat, \irqstat, \irqnr - clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0)) - b 1001f -1002: - @ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx) - mrc p6, 0, \irqstat, c5, c0, 0 @ ICHP - tst \irqstat, #0x80000000 - beq 1001f - bic \irqstat, \irqstat, #0x80000000 - mov \irqnr, \irqstat, lsr #16 - add \irqnr, \irqnr, #(PXA_IRQ(0)) -1001: - .endm
arch/arm/mach-shmobile/include/mach/entry-macro.S +0 -9
@@ -18,14 +18,5 @@ .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - .endm - - .macro test_for_ipi, irqnr, irqstat, base, tmp - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm
Signature · 1 line
1.7.0.4
Tony Lindgren
maintainerPATCH v2 1/16 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive
Quoted 9 lines · Marc Zyngier
Even when
CONFIG_MULTI_IRQ_HANDLERis selected, the core code requires thearch_irq_handler_defaultmacro to be defined as a fallback.It turns out nobody is using that particular feature as both PXA and shmobile have all their machine descriptors populated with the interrupt handler, leaving unused code (or empty macros) in their
entry-macro.Sfile just to be able to compileentry-armv.S.
Quoted 7 lines
Make
CONFIG_MULTI_IRQ_HANDLERexclusive wrtarch_irq_handler_default, which allows to remove one test from the hot path. Also cleanup both PXA and shmobileentry-macro.S.Cc Eric Miao <[email protected]>Cc Paul Mundt <[email protected]>Signed-off-by Marc Zyngier <[email protected]>
PATCH v2 2/16 ARM: smp: Add an IPI handler callable from C code
In reply to Marc ZyngierIn order to be able to handle IPI directly from C code instead of assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().
--- arch/arm/include/asm/smp.h | 5 +++++ arch/arm/kernel/smp.c | 5 +++++ 2 files changed, 10 insertions(+), 0 deletions(-)
arch/arm/include/asm/smp.h +5 -0
@@ -33,6 +33,11 @@ extern void show_ipi_list(struct seq_file *, int); asmlinkage void do_IPI(int ipinr, struct pt_regs *regs);/* +* Called from C code, this handles an IPI. +*/ +void handle_IPI (int ipinr,struct pt_regs *regs); + +/* * Setup the set of possible CPUs (via set_cpu_possible) */ extern void smp_init_cpus (void );
arch/arm/kernel/smp.c +5 -0
@@ -603,6 +603,11 @@ static void ipi_cpu_stop(unsigned int cpu)*/ asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) { +handle_IPI (ipinr, regs); +} + +void handle_IPI (int ipinr,struct pt_regs *regs) +{unsigned int cpu =smp_processor_id ();struct pt_regs *old_regs =set_irq_regs (regs);
Signature · 1 line
1.7.0.4
Tony Lindgren
maintainerPATCH v2 2/16 ARM: smp: Add an IPI handler callable from C code
Quoted 4 lines · Marc Zyngier
In order to be able to handle IPI directly from C code instead of assembly code, introduce
handle_IPI(), which is modeled afterhandle_IRQ().Signed-off-by Marc Zyngier <[email protected]>
PATCH v2 3/16 ARM: GIC: Add global gic_handle_irq() function
In reply to Marc ZyngierProvide the GIC code with a low level handler that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handler is written in C, the compiled code doesn't feel much slower than its assembly counterpart (at least with my gcc 4.4.1).
--- arch/arm/common/gic.c | 23 +++++++++++++++++++++++ arch/arm/include/asm/hardware/gic.h | 1 + 2 files changed, 24 insertions(+), 0 deletions(-)
arch/arm/common/gic.c +23 -0
@@ -209,6 +209,29 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)#define gic_set_wake NULL#endif +asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) +{ +u32 irqstat, irqnr; + +do { + irqstat =readl_relaxed (gic_cpu_base_addr +GIC_CPU_INTACK ); + irqnr = irqstat & ~0x1c00 ; + +if (likely (irqnr >15 && irqnr <1021 )) { +handle_IRQ (irqnr, regs); +continue ; + } +if (irqnr <16 ) { +writel_relaxed (irqstat, gic_cpu_base_addr +GIC_CPU_EOI ); +#ifdef CONFIG_SMP +handle_IPI (irqnr, regs); +#endif +continue ; + } +break ; + }while (1 ); +} +static void gic_handle_cascade_irq (unsigned int irq,struct irq_desc *desc) {struct gic_chip_data *chip_data =irq_get_handler_data (irq);
arch/arm/include/asm/hardware/gic.h +1 -0
@@ -38,6 +38,7 @@ extern struct irq_chip gic_arch_extn;void gic_init (unsigned int ,unsigned int ,void __iomem *,void __iomem *);void gic_secondary_init (unsigned int ); +void gic_handle_irq (struct pt_regs *regs);void gic_cascade_irq (unsigned int gic_nr,unsigned int irq);void gic_raise_softirq (const struct cpumask *mask,unsigned int irq);
Signature · 1 line
1.7.0.4
Tony Lindgren
maintainerPATCH v2 3/16 ARM: GIC: Add global gic_handle_irq() function
Quoted 6 lines · Marc Zyngier
Provide the GIC code with a low level handler that can be used by platforms using
CONFIG_MULTI_IRQ_HANDLER. Though the handler is written in C, the compiled code doesn't feel much slower than its assembly counterpart (at least with my gcc 4.4.1).Signed-off-by Marc Zyngier <[email protected]>
PATCH v2 4/16 ARM: RealView: convert to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the RealView platforms to be using the gic_handle_irq function as their primary interrupt handler.
--- arch/arm/Kconfig | 1 + arch/arm/mach-realview/include/mach/entry-macro.S | 2 -- arch/arm/mach-realview/realview_eb.c | 1 + arch/arm/mach-realview/realview_pb1176.c | 1 + arch/arm/mach-realview/realview_pb11mp.c | 1 + arch/arm/mach-realview/realview_pba8.c | 1 + arch/arm/mach-realview/realview_pbx.c | 1 + 7 files changed, 6 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
@@ -262,6 +262,7 @@ config ARCH_REALVIEW select PLAT_VERSATILE_CLCD select ARM_TIMER_SP804 select GPIO_PL061 if GPIOLIB + select MULTI_IRQ_HANDLER help This enables support for ARM Ltd RealView boards.
arch/arm/mach-realview/include/mach/entry-macro.S +0 -2
@@ -7,8 +7,6 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <mach/hardware.h> -#include <asm/hardware/entry-macro-gic.S> .macro disable_fiq .endm
arch/arm/mach-realview/realview_eb.c +1 -0
@@ -470,6 +470,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB") .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_eb_timer, + .handle_irq = gic_handle_irq, .init_machine = realview_eb_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M,
arch/arm/mach-realview/realview_pb1176.c +1 -0
@@ -364,6 +364,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pb1176_timer, + .handle_irq = gic_handle_irq, .init_machine = realview_pb1176_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M,
arch/arm/mach-realview/realview_pb11mp.c +1 -0
@@ -367,6 +367,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pb11mp_timer, + .handle_irq = gic_handle_irq, .init_machine = realview_pb11mp_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M,
arch/arm/mach-realview/realview_pba8.c +1 -0
@@ -317,6 +317,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pba8_timer, + .handle_irq = gic_handle_irq, .init_machine = realview_pba8_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M,
arch/arm/mach-realview/realview_pbx.c +1 -0
@@ -400,6 +400,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") .init_early = realview_init_early, .init_irq = gic_init_irq, .timer = &realview_pbx_timer, + .handle_irq = gic_handle_irq, .init_machine = realview_pbx_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M,
Signature · 1 line
1.7.0.4
PATCH v2 5/16 ARM: VExpress: convert to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the VExpress platform to be using the gic_handle_irq function as its primary interrupt handler.
--- arch/arm/Kconfig | 1 + arch/arm/mach-vexpress/include/mach/entry-macro.S | 2 -- arch/arm/mach-vexpress/v2m.c | 2 ++ 3 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
@@ -295,6 +295,7 @@ config ARCH_VEXPRESS select ICST select PLAT_VERSATILE select PLAT_VERSATILE_CLCD + select MULTI_IRQ_HANDLER help This enables support for the ARM Ltd Versatile Express boards.
arch/arm/mach-vexpress/include/mach/entry-macro.S +0 -2
@@ -1,5 +1,3 @@ -#include <asm/hardware/entry-macro-gic.S> - .macro disable_fiq .endm
arch/arm/mach-vexpress/v2m.c +2 -0
@@ -24,6 +24,7 @@#include <asm/hardware/arm_timer.h> #include <asm/hardware/timer-sp.h> #include <asm/hardware/sp810.h> +#include <asm/hardware/gic.h> #include <mach/ct-ca9x4.h> #include <mach/motherboard.h>
@@ -457,5 +458,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express") .init_early = v2m_init_early, .init_irq = v2m_init_irq, .timer = &v2m_timer, + .handle_irq = gic_handle_irq, .init_machine = v2m_init,MACHINE_END
Signature · 1 line
1.7.0.4
PATCH v2 6/16 ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the SMP msm platforms to be using the gic_handle_irq function as their primary interrupt handler.
--- arch/arm/mach-msm/Kconfig | 2 + arch/arm/mach-msm/board-msm8960.c | 2 + arch/arm/mach-msm/board-msm8x60.c | 4 ++ arch/arm/mach-msm/include/mach/entry-macro-qgic.S | 17 --------- arch/arm/mach-msm/include/mach/entry-macro-vic.S | 37 --------------------- arch/arm/mach-msm/include/mach/entry-macro.S | 27 +++++++++++++-- 6 files changed, 31 insertions(+), 58 deletions(-) delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-qgic.S delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-vic.S
arch/arm/mach-msm/Kconfig +2 -0
@@ -50,6 +50,7 @@ config ARCH_MSM8X60 select GPIO_MSM_V2 select MSM_GPIOMUX select MSM_SCM if SMP + select MULTI_IRQ_HANDLER config ARCH_MSM8960 bool "MSM8960"
@@ -60,6 +61,7 @@ config ARCH_MSM8960 select MSM_V2_TLMM select MSM_GPIOMUX select MSM_SCM if SMP + select MULTI_IRQ_HANDLER endchoice
arch/arm/mach-msm/board-msm8960.c +2 -0
@@ -101,6 +101,7 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") .map_io = msm8960_map_io, .init_irq = msm8960_init_irq, .timer = &msm_timer, + .handle_irq = gic_handle_irq, .init_machine = msm8960_sim_init,MACHINE_END
@@ -111,6 +112,7 @@ MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") .map_io = msm8960_map_io, .init_irq = msm8960_init_irq, .timer = &msm_timer, + .handle_irq = gic_handle_irq, .init_machine = msm8960_rumi3_init,MACHINE_END
arch/arm/mach-msm/board-msm8x60.c +4 -0
@@ -111,6 +111,7 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") .reserve = msm8x60_reserve, .map_io = msm8x60_map_io, .init_irq = msm8x60_init_irq, + .handle_irq = gic_handle_irq, .init_machine = msm8x60_init, .timer = &msm_timer,MACHINE_END
@@ -121,6 +122,7 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") .reserve = msm8x60_reserve, .map_io = msm8x60_map_io, .init_irq = msm8x60_init_irq, + .handle_irq = gic_handle_irq, .init_machine = msm8x60_init, .timer = &msm_timer,MACHINE_END
@@ -131,6 +133,7 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR") .reserve = msm8x60_reserve, .map_io = msm8x60_map_io, .init_irq = msm8x60_init_irq, + .handle_irq = gic_handle_irq, .init_machine = msm8x60_init, .timer = &msm_timer,MACHINE_END
@@ -141,6 +144,7 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA") .reserve = msm8x60_reserve, .map_io = msm8x60_map_io, .init_irq = msm8x60_init_irq, + .handle_irq = gic_handle_irq, .init_machine = msm8x60_init, .timer = &msm_timer,MACHINE_END
arch/arm/mach-msm/include/mach/entry-macro-qgic.S deleted +0 -17
@@ -1,17 +0,0 @@ -/* - * Low-level IRQ helper macros - * - * Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <asm/hardware/entry-macro-gic.S> - - .macro disable_fiq - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm
arch/arm/mach-msm/include/mach/entry-macro-vic.S deleted +0 -37
@@ -1,37 +0,0 @@ -/* - * Copyright (C) 2007 Google, Inc. - * Author: Brian Swetland <[email protected]> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <mach/msm_iomap.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - @ enable imprecise aborts - cpsie a - mov \base, #MSM_VIC_BASE - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - @ 0xD0 has irq# or old irq# if the irq has been handled - @ 0xD4 has irq# or -1 if none pending *but* if you just - @ read 0xD4 you never get the first irq for some reason - ldr \irqnr, [\base, #0xD0] - ldr \irqnr, [\base, #0xD4] - cmp \irqnr, #0xffffffff - .endm
arch/arm/mach-msm/include/mach/entry-macro.S +23 -4
@@ -16,8 +16,27 @@ * */ -#if defined(CONFIG_ARM_GIC) -#include <mach/entry-macro-qgic.S> -#else -#include <mach/entry-macro-vic.S> + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + +#if !defined(CONFIG_ARM_GIC) +#include <mach/msm_iomap.h> + + .macro get_irqnr_preamble, base, tmp + @ enable imprecise aborts + cpsie a + mov \base, #MSM_VIC_BASE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ 0xD0 has irq# or old irq# if the irq has been handled + @ 0xD4 has irq# or -1 if none pending *but* if you just + @ read 0xD4 you never get the first irq for some reason + ldr \irqnr, [\base, #0xD0] + ldr \irqnr, [\base, #0xD4] + cmp \irqnr, #0xffffffff + .endm #endif
Signature · 1 line
1.7.0.4
PATCH v2 7/16 ARM: GIC: Add global gic_handle_irq_offset() function
In reply to Marc ZyngierSimilar to gic_handle_irq(), gic_handle_irq_offset() is provided for those platform who insist on having their GIC base interrupt at something different from zero. At the moment, Exynos4 is the only one...
--- arch/arm/common/gic.c | 24 ++++++++++++++++++++++++ arch/arm/include/asm/hardware/gic.h | 1 + 2 files changed, 25 insertions(+), 0 deletions(-)
arch/arm/common/gic.c +24 -0
@@ -232,6 +232,30 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) }while (1 ); } +asmlinkage void __exception_irq_entry gic_handle_irq_offset(struct pt_regs *regs) +{ +u32 irqstat, irqnr; +u32 offset = gic_data[0 ].irq_offset; + +do { + irqstat =readl_relaxed (gic_cpu_base_addr +GIC_CPU_INTACK ); + irqnr = irqstat & ~0x1c00 ; + +if (likely (irqnr >15 && irqnr <1021 )) { +handle_IRQ (irqnr + offset, regs); +continue ; + } +if (irqnr <16 ) { +writel_relaxed (irqstat, gic_cpu_base_addr +GIC_CPU_EOI ); +#ifdef CONFIG_SMP +handle_IPI (irqnr, regs); +#endif +continue ; + } +break ; + }while (1 ); +} +static void gic_handle_cascade_irq (unsigned int irq,struct irq_desc *desc) {struct gic_chip_data *chip_data =irq_get_handler_data (irq);
arch/arm/include/asm/hardware/gic.h +1 -0
@@ -39,6 +39,7 @@ extern struct irq_chip gic_arch_extn;void gic_init (unsigned int ,unsigned int ,void __iomem *,void __iomem *);void gic_secondary_init (unsigned int );void gic_handle_irq (struct pt_regs *regs); +void gic_handle_irq_offset (struct pt_regs *regs);void gic_cascade_irq (unsigned int gic_nr,unsigned int irq);void gic_raise_softirq (const struct cpumask *mask,unsigned int irq);
Signature · 1 line
1.7.0.4
PATCH v2 7/16 ARM: GIC: Add global gic_handle_irq_offset() function
Quoted 20 lines · Marc Zyngier
Similar to
gic_handle_irq(),gic_handle_irq_offset()is provided for those platform who insist on having their GIC base interrupt at something different from zero. At the moment, Exynos4 is the only one...Signed-off-by Marc Zyngier <[email protected]>--- arch/arm/common/gic.c | 24 ++++++++++++++++++++++++ arch/arm/include/asm/hardware/gic.h | 1 + 2 files changed, 25 insertions(+), 0 deletions(-)arch/arm/common/gic.c +1
-0@@ -232,6 +232,30 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) }while (1 ); } +asmlinkage void __exception_irq_entry gic_handle_irq_offset(struct pt_regs *regs)
arch/arm/common/gic.c asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) · line 245
Quoted 10 lines
arch/arm/common/gic.c +10
-0+{ +u32 irqstat, irqnr; +u32 offset = gic_data[0 ].irq_offset; + + do { + irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK); + irqnr = irqstat & ~0x1c00; + + if (likely(irqnr > 15 && irqnr < 1021)) { + handle_IRQ(irqnr + offset, regs);
Can't this be combined with gic_handle_irq. irq_offset will be 0 in that case. Really, irq_domain should be used here.
Rob
Quoted 28 lines
arch/arm/common/gic.c +13
-0+continue ; + } +if (irqnr <16 ) { +writel_relaxed (irqstat, gic_cpu_base_addr +GIC_CPU_EOI ); +#ifdef CONFIG_SMP +handle_IPI (irqnr, regs); +#endif +continue ; + } +break ; + }while (1 ); +} +static void gic_handle_cascade_irq (unsigned int irq,struct irq_desc *desc) {struct gic_chip_data *chip_data =irq_get_handler_data (irq);arch/arm/include/asm/hardware/gic.h +1
-0@@ -39,6 +39,7 @@ extern struct irq_chip gic_arch_extn;void gic_init (unsigned int ,unsigned int ,void __iomem *,void __iomem *);void gic_secondary_init (unsigned int );void gic_handle_irq (struct pt_regs *regs); +void gic_handle_irq_offset (struct pt_regs *regs);void gic_cascade_irq (unsigned int gic_nr,unsigned int irq);void gic_raise_softirq (const struct cpumask *mask,unsigned int irq);
PATCH v2 7/16 ARM: GIC: Add global gic_handle_irq_offset() function
Quoted 20 lines · Rob Herring
Quoted 19 lines · Marc Zyngier
Similar to
gic_handle_irq(),gic_handle_irq_offset()is provided for those platform who insist on having their GIC base interrupt at something different from zero. At the moment, Exynos4 is the only one...Signed-off-by Marc Zyngier <[email protected]>--- arch/arm/common/gic.c | 24 ++++++++++++++++++++++++ arch/arm/include/asm/hardware/gic.h | 1 + 2 files changed, 25 insertions(+), 0 deletions(-)arch/arm/common/gic.c +0
-0@@ -232,6 +232,30 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) }while (1 ); }
Quoted 14 lines
arch/arm/common/gic.c asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) · line 245
Quoted 11 lines
arch/arm/common/gic.c +11
-0+asmlinkage void __exception_irq_entry gic_handle_irq_offset(struct pt_regs *regs) +{ +u32 irqstat, irqnr; +u32 offset = gic_data[0 ].irq_offset; + + do { + irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK); + irqnr = irqstat & ~0x1c00; + + if (likely(irqnr > 15 && irqnr < 1021)) { + handle_IRQ(irqnr + offset, regs);Can't this be combined with
gic_handle_irq.irq_offsetwill be 0 in that case. Really,irq_domainshould be used here.
I completely agree on the irq_domain thing. The reason I introduced two functions is to keep things as similar as possible to the old implementation, and also to save a memory reference + addition on the hot path of all the other platforms.
If we all agree that keeping that piece of code as generic as possible is the way forward, then I'll happily drop that patch and let Exynos4 use the same handler.
Cheers,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
PATCH v2 8/16 ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the Exynos4 platforms to be using the gic_handle_irq_offset() function as their primary interrupt handler.
--- arch/arm/Kconfig | 1 + arch/arm/mach-exynos4/include/mach/entry-macro.S | 62 ---------------------- arch/arm/mach-exynos4/mach-armlex4210.c | 2 + arch/arm/mach-exynos4/mach-nuri.c | 2 + arch/arm/mach-exynos4/mach-origen.c | 2 + arch/arm/mach-exynos4/mach-smdk4212.c | 2 + arch/arm/mach-exynos4/mach-smdkv310.c | 2 + arch/arm/mach-exynos4/mach-universal_c210.c | 2 + 8 files changed, 13 insertions(+), 62 deletions(-)
arch/arm/Kconfig +1 -0
@@ -787,6 +787,7 @@ config ARCH_EXYNOS4 select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG + select MULTI_IRQ_HANDLER help Samsung EXYNOS4 series based systems
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -62
71 lines not on this page · raw message
arch/arm/mach-exynos4/mach-armlex4210.c +2 -0
@@ -15,6 +15,7 @@#include <linux/serial_core.h> #include <linux/smsc911x.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h>
@@ -213,6 +214,7 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210") .soc = &exynos4_soc_desc, .init_irq = exynos4_init_irq, .map_io = armlex4210_map_io, + .handle_irq = gic_handle_irq_offset, .init_machine = armlex4210_machine_init, .timer = &exynos4_timer,MACHINE_END
arch/arm/mach-exynos4/mach-nuri.c +2 -0
@@ -28,6 +28,7 @@#include <video/platform_lcd.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h>
@@ -1192,6 +1193,7 @@ MACHINE_START(NURI, "NURI") .soc = &exynos4_soc_desc, .init_irq = exynos4_init_irq, .map_io = nuri_map_io, + .handle_irq = gic_handle_irq_offset, .init_machine = nuri_machine_init, .timer = &exynos4_timer, .reserve = &nuri_reserve,
arch/arm/mach-exynos4/mach-origen.c +2 -0
@@ -17,6 +17,7 @@#include <linux/pwm_backlight.h> #include <linux/gpio_keys.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h>
@@ -215,6 +216,7 @@ MACHINE_START(ORIGEN, "ORIGEN") .soc = &exynos4_soc_desc, .init_irq = exynos4_init_irq, .map_io = origen_map_io, + .handle_irq = gic_handle_irq_offset, .init_machine = origen_machine_init, .timer = &exynos4_timer,MACHINE_END
arch/arm/mach-exynos4/mach-smdk4212.c +2 -0
@@ -20,6 +20,7 @@#include <linux/regulator/machine.h> #include <linux/serial_core.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h>
@@ -290,6 +291,7 @@ MACHINE_START(SMDK4212, "SMDK4212") .soc = &exynos4_soc_desc, .init_irq = exynos4_init_irq, .map_io = smdk4212_map_io, + .handle_irq = gic_handle_irq_offset, .init_machine = smdk4212_machine_init, .timer = &exynos4_timer,MACHINE_END
arch/arm/mach-exynos4/mach-smdkv310.c +2 -0
@@ -20,6 +20,7 @@#include <linux/input.h> #include <linux/pwm_backlight.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h>
@@ -351,6 +352,7 @@ MACHINE_START(SMDKC210, "SMDKC210") .soc = &exynos4_soc_desc, .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, + .handle_irq = gic_handle_irq_offset, .init_machine = smdkv310_machine_init, .timer = &exynos4_timer,MACHINE_END
arch/arm/mach-exynos4/mach-universal_c210.c +2 -0
@@ -23,6 +23,7 @@#include <linux/i2c/mcs.h> #include <linux/i2c/atmel_mxt_ts.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h>
@@ -876,6 +877,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") .soc = &exynos4_soc_desc, .init_irq = exynos4_init_irq, .map_io = universal_map_io, + .handle_irq = gic_handle_irq_offset, .init_machine = universal_machine_init, .timer = &exynos4_timer, .reserve = &universal_reserve,
Signature · 1 line
1.7.0.4
PATCH v2 9/16 ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the tegra2 platforms to be using the gic_handle_irq function as their primary interrupt handler.
Tested on harmony.
--- arch/arm/mach-tegra/Kconfig | 1 + arch/arm/mach-tegra/board-dt.c | 2 ++ arch/arm/mach-tegra/board-harmony.c | 2 ++ arch/arm/mach-tegra/board-paz00.c | 2 ++ arch/arm/mach-tegra/board-seaboard.c | 4 ++++ arch/arm/mach-tegra/board-trimslice.c | 2 ++ arch/arm/mach-tegra/include/mach/entry-macro.S | 22 ++-------------------- 7 files changed, 15 insertions(+), 20 deletions(-)
arch/arm/mach-tegra/Kconfig +1 -0
@@ -13,6 +13,7 @@ config ARCH_TEGRA_2x_SOC select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ULPI if USB_SUPPORT select USB_ULPI_VIEWPORT if USB_SUPPORT + select MULTI_IRQ_HANDLER help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
arch/arm/mach-tegra/board-dt.c +2 -0
@@ -32,6 +32,7 @@#include <linux/i2c.h> #include <linux/i2c-tegra.h> +#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h>
@@ -115,6 +116,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)") .soc = &tegra_soc_desc, .init_early = tegra_init_early, .init_irq = tegra_init_irq, + .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_dt_init, .dt_compat = tegra_dt_board_compat,
arch/arm/mach-tegra/board-harmony.c +2 -0
@@ -31,6 +31,7 @@#include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> +#include <asm/hardware/gic.h> #include <asm/setup.h> #include <mach/tegra_wm8903_pdata.h>
@@ -189,6 +190,7 @@ MACHINE_START(HARMONY, "harmony") .map_io = tegra_map_common_io, .init_early = tegra_init_early, .init_irq = tegra_init_irq, + .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_harmony_init,MACHINE_END
arch/arm/mach-tegra/board-paz00.c +2 -0
@@ -28,6 +28,7 @@#include <linux/i2c.h> #include <linux/rfkill-gpio.h> +#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h>
@@ -192,6 +193,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ") .map_io = tegra_map_common_io, .init_early = tegra_init_early, .init_irq = tegra_init_irq, + .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_paz00_init,MACHINE_END
arch/arm/mach-tegra/board-seaboard.c +4 -0
@@ -34,6 +34,7 @@#include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <asm/hardware/gic.h> #include "board.h" #include "board-seaboard.h"
@@ -286,6 +287,7 @@ MACHINE_START(SEABOARD, "seaboard") .map_io = tegra_map_common_io, .init_early = tegra_init_early, .init_irq = tegra_init_irq, + .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_seaboard_init,MACHINE_END
@@ -296,6 +298,7 @@ MACHINE_START(KAEN, "kaen") .map_io = tegra_map_common_io, .init_early = tegra_init_early, .init_irq = tegra_init_irq, + .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_kaen_init,MACHINE_END
@@ -306,6 +309,7 @@ MACHINE_START(WARIO, "wario") .map_io = tegra_map_common_io, .init_early = tegra_init_early, .init_irq = tegra_init_irq, + .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_wario_init,MACHINE_END
arch/arm/mach-tegra/board-trimslice.c +2 -0
@@ -26,6 +26,7 @@#include <linux/i2c.h> #include <linux/gpio.h> +#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/setup.h>
@@ -179,6 +180,7 @@ MACHINE_START(TRIMSLICE, "trimslice") .map_io = tegra_map_common_io, .init_early = tegra_init_early, .init_irq = tegra_init_irq, + .handle_irq = gic_handle_irq, .timer = &tegra_timer, .init_machine = tegra_trimslice_init,MACHINE_END
arch/arm/mach-tegra/include/mach/entry-macro.S +2 -20
@@ -12,30 +12,15 @@ * GNU General Public License for more details. * */ -#include <mach/iomap.h> -#include <mach/io.h> - -#if defined(CONFIG_ARM_GIC) -#define HAVE_GET_IRQNR_PREAMBLE -#include <asm/hardware/entry-macro-gic.S> - - /* Uses the GIC interrupt controller built into the cpu */ -#define ICTRL_BASE (IO_CPU_VIRT + 0x100) .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - movw \base, #(ICTRL_BASE & 0x0000ffff) - movt \base, #((ICTRL_BASE & 0xffff0000) >> 16) + .macro arch_ret_to_user, tmp1, tmp2 .endm - .macro arch_ret_to_user, tmp1, tmp2 - .endm -#else +#if !defined(CONFIG_ARM_GIC) /* legacy interrupt controller for AP16 */ - .macro disable_fiq - .endm .macro get_irqnr_preamble, base, tmp @ enable imprecise aborts
@@ -46,9 +31,6 @@ orr \base, #0x0000f000 .endm - .macro arch_ret_to_user, tmp1, tmp2 - .endm - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS cmp \irqnr, #0x80
Signature · 1 line
1.7.0.4
PATCH v2 10/16 ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the ux500 platforms to be using the gic_handle_irq function as their primary interrupt handler.
--- arch/arm/mach-ux500/Kconfig | 1 + arch/arm/mach-ux500/board-mop500.c | 4 ++++ arch/arm/mach-ux500/board-u5500.c | 2 ++ arch/arm/mach-ux500/include/mach/entry-macro.S | 2 -- 4 files changed, 7 insertions(+), 2 deletions(-)
arch/arm/mach-ux500/Kconfig +1 -0
@@ -7,6 +7,7 @@ config UX500_SOC_COMMON select HAS_MTU select ARM_ERRATA_753970 select ARM_ERRATA_754322 + select MULTI_IRQ_HANDLER menu "Ux500 SoC"
arch/arm/mach-ux500/board-mop500.c +4 -0
@@ -33,6 +33,7 @@#include <linux/leds.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <asm/hardware/gic.h> #include <plat/i2c.h> #include <plat/ste_dma40.h>
@@ -696,6 +697,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform") .init_irq = ux500_init_irq,/* we re-use nomadik timer here */ .timer = &ux500_timer, + .handle_irq = gic_handle_irq, .init_machine = mop500_init_machine,MACHINE_END
@@ -705,6 +707,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") .map_io = u8500_map_io, .init_irq = ux500_init_irq, .timer = &ux500_timer, + .handle_irq = gic_handle_irq, .init_machine = hrefv60_init_machine,MACHINE_END
@@ -715,5 +718,6 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") .init_irq = ux500_init_irq,/* we re-use nomadik timer here */ .timer = &ux500_timer, + .handle_irq = gic_handle_irq, .init_machine = snowball_init_machine,MACHINE_END
arch/arm/mach-ux500/board-u5500.c +2 -0
@@ -11,6 +11,7 @@#include <linux/irq.h> #include <linux/i2c.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach-types.h>
@@ -123,5 +124,6 @@ MACHINE_START(U5500, "ST-Ericsson U5500 Platform") .map_io = u5500_map_io, .init_irq = ux500_init_irq, .timer = &ux500_timer, + .handle_irq = gic_handle_irq, .init_machine = u5500_init_machine,MACHINE_END
arch/arm/mach-ux500/include/mach/entry-macro.S +0 -2
@@ -10,8 +10,6 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <mach/hardware.h> -#include <asm/hardware/entry-macro-gic.S> .macro disable_fiq .endm
Signature · 1 line
1.7.0.4
PATCH v2 10/16 ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER
Quoted 5 lines · Marc Zyngier
Convert the ux500 platforms to be using the
gic_handle_irqfunction as their primary interrupt handler.Cc Linus Walleij <[email protected]>Signed-off-by Marc Zyngier <[email protected]>
Seems straight-forward provided the first patch is working good so:
Thanks,
Linus Walleij
PATCH v2 10/16 ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER
Quoted 11 lines · Linus Walleij
Quoted 5 lines · Marc Zyngier
Convert the ux500 platforms to be using the
gic_handle_irqfunction as their primary interrupt handler.Cc Linus Walleij <[email protected]>Signed-off-by Marc Zyngier <[email protected]>Seems straight-forward provided the first patch is working good so:
Acked-by Linus Walleij <[email protected]>
Thanks Linus!
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
PATCH v2 11/16 ARM: shmobile: convert smp platforms to gic_handle_irq()
In reply to Marc ZyngierConvert the SMP shmobile platforms to use gic_handle_irq() instead of the assembly macro.
--- arch/arm/mach-shmobile/Makefile | 1 - arch/arm/mach-shmobile/board-ag5evm.c | 2 +- arch/arm/mach-shmobile/entry-gic.S | 18 ------------------ arch/arm/mach-shmobile/include/mach/common.h | 1 - 4 files changed, 1 insertions(+), 21 deletions(-) delete mode 100644 arch/arm/mach-shmobile/entry-gic.S
arch/arm/mach-shmobile/Makefile +0 -1
@@ -28,7 +28,6 @@ pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o obj-$(CONFIG_ARCH_SH7367) += entry-intc.o obj-$(CONFIG_ARCH_SH7377) += entry-intc.o obj-$(CONFIG_ARCH_SH7372) += entry-intc.o -obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o # PM objects obj-$(CONFIG_SUSPEND) += suspend.o
arch/arm/mach-shmobile/board-ag5evm.c +1 -1
@@ -602,7 +602,7 @@ struct sys_timer ag5evm_timer = {MACHINE_START (AG5EVM ,"ag5evm" ) .map_io = ag5evm_map_io, .init_irq = ag5evm_init_irq, - .handle_irq = shmobile_handle_irq_gic, + .handle_irq = gic_handle_irq, .init_machine = ag5evm_init, .timer = &ag5evm_timer,MACHINE_END
arch/arm/mach-shmobile/entry-gic.S deleted +0 -18
@@ -1,18 +0,0 @@ -/* - * ARM Interrupt demux handler using GIC - * - * Copyright (C) 2010 Magnus Damm - * Copyright (C) 2011 Paul Mundt - * Copyright (C) 2010 - 2011 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <asm/assembler.h> -#include <asm/entry-macro-multi.S> -#include <asm/hardware/gic.h> -#include <asm/hardware/entry-macro-gic.S> - - arch_irq_handler shmobile_handle_irq_gic
arch/arm/mach-shmobile/include/mach/common.h +0 -1
@@ -7,7 +7,6 @@ extern void shmobile_secondary_vector(void);struct clk ;extern int clk_init (void );extern void shmobile_handle_irq_intc (struct pt_regs *); -extern void shmobile_handle_irq_gic (struct pt_regs *);extern struct platform_suspend_ops shmobile_suspend_ops;struct cpuidle_device ;extern void (*shmobile_cpuidle_modes[])(void );
Signature · 1 line
1.7.0.4
PATCH v2 12/16 ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the cns3xxx platform to be using the gic_handle_irq function as its primary interrupt handler.
--- arch/arm/Kconfig | 1 + arch/arm/mach-cns3xxx/cns3420vb.c | 2 ++ arch/arm/mach-cns3xxx/include/mach/entry-macro.S | 2 -- 3 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
@@ -334,6 +334,7 @@ config ARCH_CNS3XXX select ARM_GIC select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI + select MULTI_IRQ_HANDLER help Support for Cavium Networks CNS3XXX platform.
arch/arm/mach-cns3xxx/cns3420vb.c +2 -0
@@ -26,6 +26,7 @@#include <linux/mtd/partitions.h> #include <asm/setup.h> #include <asm/mach-types.h> +#include <asm/hardware/gic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h>
@@ -201,5 +202,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .map_io = cns3420_map_io, .init_irq = cns3xxx_init_irq, .timer = &cns3xxx_timer, + .handle_irq = gic_handle_irq, .init_machine = cns3420_init,MACHINE_END
arch/arm/mach-cns3xxx/include/mach/entry-macro.S +0 -2
@@ -8,8 +8,6 @@ * published by the Free Software Foundation. */ -#include <asm/hardware/entry-macro-gic.S> - .macro disable_fiq .endm
Signature · 1 line
1.7.0.4
PATCH v2 13/16 ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the zynq platform to be using the gic_handle_irq function as its primary interrupt handler.
--- arch/arm/Kconfig | 1 + arch/arm/mach-zynq/common.c | 1 + arch/arm/mach-zynq/include/mach/entry-macro.S | 3 --- 3 files changed, 2 insertions(+), 3 deletions(-)
arch/arm/Kconfig +1 -0
@@ -911,6 +911,7 @@ config ARCH_ZYNQ select ARM_AMBA select ICST select USE_OF + select MULTI_IRQ_HANDLER help Support for Xilinx Zynq ARM Cortex A9 Platform endchoice
arch/arm/mach-zynq/common.c +1 -0
@@ -112,6 +112,7 @@ static const char *xilinx_dt_match[] = {MACHINE_START (XILINX_EP107 ,"Xilinx Zynq Platform" ) .map_io = xilinx_map_io, .init_irq = xilinx_irq_init, + .handle_irq = gic_handle_irq, .init_machine = xilinx_init_machine, .timer = &xttcpss_sys_timer, .dt_compat = xilinx_dt_match,
arch/arm/mach-zynq/include/mach/entry-macro.S +0 -3
@@ -20,9 +20,6 @@ * GNU General Public License for more details. */ -#include <mach/hardware.h> -#include <asm/hardware/entry-macro-gic.S> - .macro disable_fiq .endm
Signature · 1 line
1.7.0.4
PATCH v2 14/16 ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions
In reply to Marc ZyngierProvide the OMAP2/3 IRQ code with low level handlers that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handlers are written in C, the compiled code looks very similar to its assembly counterpart (at least with my gcc 4.4.1).
--- arch/arm/mach-omap2/irq.c | 49 ++++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/irqs.h | 2 + 2 files changed, 51 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/irq.c +49 -0
@@ -35,6 +35,11 @@/* Number of IRQ state bits in each MIR register */ #define IRQ_BITS_PER_REG 32 +#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) +#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) +#define INTCPS_SIR_IRQ_OFFSET 0x0040/* omap2/3 active interrupt offset */ +#define ACTIVEIRQ_MASK 0x7f/* omap2/3 active interrupt bits */ +/* * OMAP2 has a number of different interrupt controllers, each interrupt * controller is identified as its own "bank". Register definitions are
@@ -191,6 +196,44 @@ void __init ti816x_init_irq(void)omap_init_irq (OMAP34XX_IC_BASE ,128 ); } +static inline void omap_intc_handle_irq (void __iomem *base_addr,struct pt_regs *regs) +{ +u32 irqnr; + +do { + irqnr =readl_relaxed (base_addr +0x98 ); +if (irqnr) + goto out; + + irqnr =readl_relaxed (base_addr +0xb8 ); +if (irqnr) + goto out; + + irqnr =readl_relaxed (base_addr +0xd8 ); +#ifdef CONFIG_SOC_OMAPTI816X +if (irqnr) + goto out; + irqnr =readl_relaxed (base_addr +0xf8 ); +#endif + +out: +if (!irqnr) +break ; + + irqnr =readl_relaxed (base_addr +INTCPS_SIR_IRQ_OFFSET ); + irqnr &=ACTIVEIRQ_MASK ; + +if (irqnr) +handle_IRQ (irqnr, regs); + }while (irqnr); +} + +asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs) +{ +void __iomem *base_addr =OMAP2_IRQ_BASE ; +omap_intc_handle_irq (base_addr, regs); +} +#ifdef CONFIG_ARCH_OMAP3 static struct omap3_intc_regs intc_context[ARRAY_SIZE (irq_banks)];
@@ -263,4 +306,10 @@ void omap3_intc_resume_idle(void)/* Re-enable autoidle */ intc_bank_write_reg (1 , &irq_banks[0 ],INTC_SYSCONFIG ); } + +asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) +{ +void __iomem *base_addr =OMAP3_IRQ_BASE ; +omap_intc_handle_irq (base_addr, regs); +}#endif /* CONFIG_ARCH_OMAP3 */
arch/arm/plat-omap/include/plat/irqs.h +2 -0
@@ -448,6 +448,8 @@ void omap_intc_restore_context(void);void omap3_intc_suspend (void );void omap3_intc_prepare_idle (void );void omap3_intc_resume_idle (void ); +void omap2_intc_handle_irq (struct pt_regs *regs); +void omap3_intc_handle_irq (struct pt_regs *regs);#endif #include <mach/hardware.h>
Signature · 1 line
1.7.0.4
Tony Lindgren
maintainerPATCH v2 14/16 ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions
Quoted 7 lines · Marc Zyngier
Provide the OMAP2/3 IRQ code with low level handlers that can be used by platforms using
CONFIG_MULTI_IRQ_HANDLER. Though the handlers are written in C, the compiled code looks very similar to its assembly counterpart (at least with my gcc 4.4.1).Cc Tony Lindgren <[email protected]>Signed-off-by Marc Zyngier <[email protected]>
Nice, thanks for doing this!
PATCH v2 15/16 ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierConvert the omap2plus platforms to be using CONFIG_MULTI_IRQ_HANDLER. Each machine is modified to provide either omap2_intc_handle_irq(), omap3_intc_handle_irq() or gic_handle_irq().
This allows for a major cleanup, removing the MULTI_OMAP setup from the interrupt path.
Tested on both Panda and IGEPv2 (single kernel image)
--- arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/board-2430sdp.c | 1 + arch/arm/mach-omap2/board-3430sdp.c | 1 + arch/arm/mach-omap2/board-3630sdp.c | 1 + arch/arm/mach-omap2/board-4430sdp.c | 2 + arch/arm/mach-omap2/board-am3517crane.c | 1 + arch/arm/mach-omap2/board-am3517evm.c | 1 + arch/arm/mach-omap2/board-apollon.c | 1 + arch/arm/mach-omap2/board-cm-t35.c | 2 + arch/arm/mach-omap2/board-cm-t3517.c | 1 + arch/arm/mach-omap2/board-devkit8000.c | 1 + arch/arm/mach-omap2/board-generic.c | 1 + arch/arm/mach-omap2/board-h4.c | 1 + arch/arm/mach-omap2/board-igep0020.c | 2 + arch/arm/mach-omap2/board-ldp.c | 1 + arch/arm/mach-omap2/board-n8x0.c | 3 + arch/arm/mach-omap2/board-omap3beagle.c | 1 + arch/arm/mach-omap2/board-omap3evm.c | 1 + arch/arm/mach-omap2/board-omap3logic.c | 2 + arch/arm/mach-omap2/board-omap3pandora.c | 1 + arch/arm/mach-omap2/board-omap3stalker.c | 1 + arch/arm/mach-omap2/board-omap3touchbook.c | 1 + arch/arm/mach-omap2/board-omap4panda.c | 2 + arch/arm/mach-omap2/board-overo.c | 1 + arch/arm/mach-omap2/board-rm680.c | 1 + arch/arm/mach-omap2/board-rx51.c | 1 + arch/arm/mach-omap2/board-zoom.c | 2 + arch/arm/mach-omap2/include/mach/entry-macro.S | 137 ------------------------ arch/arm/plat-omap/Kconfig | 1 + 29 files changed, 36 insertions(+), 137 deletions(-)
arch/arm/mach-omap2/Kconfig +1 -0
@@ -25,6 +25,7 @@ config ARCH_OMAP2 depends on ARCH_OMAP2PLUS default y select CPU_V6 + select MULTI_IRQ_HANDLER config ARCH_OMAP3 bool "TI OMAP3"
arch/arm/mach-omap2/board-2430sdp.c +1 -0
@@ -256,6 +256,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") .map_io = omap_2430sdp_map_io, .init_early = omap2430_init_early, .init_irq = omap2_init_irq, + .handle_irq = omap2_intc_handle_irq, .init_machine = omap_2430sdp_init, .timer = &omap2_timer,MACHINE_END
arch/arm/mach-omap2/board-3430sdp.c +1 -0
@@ -728,6 +728,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap_3430sdp_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-3630sdp.c +1 -0
@@ -215,6 +215,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") .map_io = omap3_map_io, .init_early = omap3630_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap_sdp_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-4430sdp.c +2 -0
@@ -28,6 +28,7 @@#include <mach/hardware.h> #include <mach/omap4-common.h> +#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h>
@@ -991,6 +992,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") .map_io = omap_4430sdp_map_io, .init_early = omap4430_init_early, .init_irq = gic_init_irq, + .handle_irq = gic_handle_irq, .init_machine = omap_4430sdp_init, .timer = &omap4_timer,MACHINE_END
arch/arm/mach-omap2/board-am3517crane.c +1 -0
@@ -98,6 +98,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") .map_io = omap3_map_io, .init_early = am35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = am3517_crane_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-am3517evm.c +1 -0
@@ -491,6 +491,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .map_io = omap3_map_io, .init_early = am35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = am3517_evm_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-apollon.c +1 -0
@@ -350,6 +350,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") .map_io = omap_apollon_map_io, .init_early = omap2420_init_early, .init_irq = omap2_init_irq, + .handle_irq = omap2_intc_handle_irq, .init_machine = omap_apollon_init, .timer = &omap2_timer,MACHINE_END
arch/arm/mach-omap2/board-cm-t35.c +2 -0
@@ -634,6 +634,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t35_init, .timer = &omap3_timer,MACHINE_END
@@ -644,6 +645,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730") .map_io = omap3_map_io, .init_early = omap3630_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t3730_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-cm-t3517.c +1 -0
@@ -299,6 +299,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517") .map_io = omap3_map_io, .init_early = am35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = cm_t3517_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-devkit8000.c +1 -0
@@ -666,6 +666,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = devkit8000_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = devkit8000_init, .timer = &omap3_secure_timer,MACHINE_END
arch/arm/mach-omap2/board-generic.c +1 -0
@@ -70,6 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") .map_io = omap_generic_map_io, .init_early = omap_generic_init_early, .init_irq = omap2_init_irq, + .handle_irq = omap2_intc_handle_irq, .init_machine = omap_generic_init, .timer = &omap2_timer,MACHINE_END
arch/arm/mach-omap2/board-h4.c +1 -0
@@ -381,6 +381,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board") .map_io = omap_h4_map_io, .init_early = omap2420_init_early, .init_irq = omap_h4_init_irq, + .handle_irq = omap2_intc_handle_irq, .init_machine = omap_h4_init, .timer = &omap2_timer,MACHINE_END
arch/arm/mach-omap2/board-igep0020.c +2 -0
@@ -672,6 +672,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = igep_init, .timer = &omap3_timer,MACHINE_END
@@ -682,6 +683,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = igep_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-ldp.c +1 -0
@@ -332,6 +332,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board") .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap_ldp_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-n8x0.c +3 -0
@@ -695,6 +695,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800") .map_io = n8x0_map_io, .init_early = omap2420_init_early, .init_irq = omap2_init_irq, + .handle_irq = omap2_intc_handle_irq, .init_machine = n8x0_init_machine, .timer = &omap2_timer,MACHINE_END
@@ -705,6 +706,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810") .map_io = n8x0_map_io, .init_early = omap2420_init_early, .init_irq = omap2_init_irq, + .handle_irq = omap2_intc_handle_irq, .init_machine = n8x0_init_machine, .timer = &omap2_timer,MACHINE_END
@@ -715,6 +717,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") .map_io = n8x0_map_io, .init_early = omap2420_init_early, .init_irq = omap2_init_irq, + .handle_irq = omap2_intc_handle_irq, .init_machine = n8x0_init_machine, .timer = &omap2_timer,MACHINE_END
arch/arm/mach-omap2/board-omap3beagle.c +1 -0
@@ -569,6 +569,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") .map_io = omap3_map_io, .init_early = omap3_beagle_init_early, .init_irq = omap3_beagle_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_beagle_init, .timer = &omap3_secure_timer,MACHINE_END
arch/arm/mach-omap2/board-omap3evm.c +1 -0
@@ -681,6 +681,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_evm_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-omap3logic.c +2 -0
@@ -208,6 +208,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap3logic_init, .timer = &omap3_timer,MACHINE_END
@@ -217,6 +218,7 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap3logic_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-omap3pandora.c +1 -0
@@ -606,6 +606,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap3pandora_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-omap3stalker.c +1 -0
@@ -459,6 +459,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_stalker_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_stalker_init, .timer = &omap3_secure_timer,MACHINE_END
arch/arm/mach-omap2/board-omap3touchbook.c +1 -0
@@ -404,6 +404,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_touchbook_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_touchbook_init, .timer = &omap3_secure_timer,MACHINE_END
arch/arm/mach-omap2/board-omap4panda.c +2 -0
@@ -31,6 +31,7 @@#include <mach/hardware.h> #include <mach/omap4-common.h> +#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h>
@@ -584,6 +585,7 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") .map_io = omap4_panda_map_io, .init_early = omap4430_init_early, .init_irq = gic_init_irq, + .handle_irq = gic_handle_irq, .init_machine = omap4_panda_init, .timer = &omap4_timer,MACHINE_END
arch/arm/mach-omap2/board-overo.c +1 -0
@@ -562,6 +562,7 @@ MACHINE_START(OVERO, "Gumstix Overo") .map_io = omap3_map_io, .init_early = omap35xx_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = overo_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-rm680.c +1 -0
@@ -155,6 +155,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") .map_io = rm680_map_io, .init_early = omap3630_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = rm680_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-rx51.c +1 -0
@@ -158,6 +158,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") .map_io = rx51_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = rx51_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/board-zoom.c +2 -0
@@ -135,6 +135,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap_zoom_init, .timer = &omap3_timer,MACHINE_END
@@ -145,6 +146,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .map_io = omap3_map_io, .init_early = omap3630_init_early, .init_irq = omap3_init_irq, + .handle_irq = omap3_intc_handle_irq, .init_machine = omap_zoom_init, .timer = &omap3_timer,MACHINE_END
arch/arm/mach-omap2/include/mach/entry-macro.S +0 -137
146 lines not on this page · raw message
arch/arm/plat-omap/Kconfig +1 -0
@@ -22,6 +22,7 @@ config ARCH_OMAP2PLUS select CLKDEV_LOOKUP select GENERIC_IRQ_CHIP select OMAP_DM_TIMER + select MULTI_IRQ_HANDLER help "Systems based on OMAP2, OMAP3 or OMAP4"
Signature · 1 line
1.7.0.4
Tony Lindgren
maintainerPATCH v2 15/16 ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER
Quoted 8 lines · Marc Zyngier
Convert the omap2plus platforms to be using
CONFIG_MULTI_IRQ_HANDLER. Each machine is modified to provide eitheromap2_intc_handle_irq(),omap3_intc_handle_irq()orgic_handle_irq().This allows for a major cleanup, removing the
MULTI_OMAPsetup from the interrupt path.Tested on both Panda and IGEPv2 (single kernel image)
...
arch/arm/mach-omap2/Kconfig config ARCH_OMAP2 · line 31
Quoted 10 lines
arch/arm/mach-omap2/Kconfig +1
-0@@ -25,6 +25,7 @@ config ARCH_OMAP2 depends on ARCH_OMAP2PLUS default y select CPU_V6 + select MULTI_IRQ_HANDLER config ARCH_OMAP3 bool "TI OMAP3"
This one selects it only for ARCH_OMAP2, not for ARCH_OMAP2PLUS.
This might require minor merging with the cleanup I've posted, but that should be trivial.
Other than that:
PATCH v2 16/16 ARM: GIC: Make MULTI_IRQ_HANDLER mandatory
In reply to Marc ZyngierNow that MULTI_IRQ_HANDLER is selected by all the in-tree GIC users, make it mandatory and remove the unused macros.
--- arch/arm/Kconfig | 3 - arch/arm/common/Kconfig | 1 + arch/arm/common/gic.c | 2 +- arch/arm/include/asm/hardware/entry-macro-gic.S | 60 ----------------------- arch/arm/include/asm/hardware/gic.h | 1 - arch/arm/mach-msm/Kconfig | 2 - arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-tegra/Kconfig | 1 - arch/arm/mach-ux500/Kconfig | 1 - arch/arm/plat-omap/Kconfig | 1 - 10 files changed, 3 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/Kconfig +0 -3
@@ -334,7 +334,6 @@ config ARCH_CNS3XXX select ARM_GIC select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI - select MULTI_IRQ_HANDLER help Support for Cavium Networks CNS3XXX platform.
@@ -788,7 +787,6 @@ config ARCH_EXYNOS4 select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG - select MULTI_IRQ_HANDLER help Samsung EXYNOS4 series based systems
@@ -911,7 +909,6 @@ config ARCH_ZYNQ select ARM_AMBA select ICST select USE_OF - select MULTI_IRQ_HANDLER help Support for Xilinx Zynq ARM Cortex A9 Platform endchoice
arch/arm/common/Kconfig +1 -0
@@ -1,5 +1,6 @@ config ARM_GIC select IRQ_PERCPU_DEVID + select MULTI_IRQ_HANDLER bool config ARM_VIC
arch/arm/common/gic.c +1 -1
@@ -39,7 +39,7 @@static DEFINE_RAW_SPINLOCK (irq_controller_lock);/* Address of GIC 0 CPU interface */ -void __iomem *gic_cpu_base_addr__read_mostly ; +static void __iomem *gic_cpu_base_addr__read_mostly ;/* * Supported arch specific GIC irq extension.
arch/arm/include/asm/hardware/entry-macro-gic.S deleted +0 -60
60 lines not on this page · raw message
arch/arm/include/asm/hardware/gic.h +0 -1
@@ -33,7 +33,6 @@#define GIC_DIST_SOFTINT 0xf00#ifndef __ASSEMBLY__ -extern void __iomem *gic_cpu_base_addr;extern struct irq_chip gic_arch_extn;void gic_init (unsigned int ,unsigned int ,void __iomem *,void __iomem *);
arch/arm/mach-msm/Kconfig +0 -2
@@ -50,7 +50,6 @@ config ARCH_MSM8X60 select GPIO_MSM_V2 select MSM_GPIOMUX select MSM_SCM if SMP - select MULTI_IRQ_HANDLER config ARCH_MSM8960 bool "MSM8960"
@@ -61,7 +60,6 @@ config ARCH_MSM8960 select MSM_V2_TLMM select MSM_GPIOMUX select MSM_SCM if SMP - select MULTI_IRQ_HANDLER endchoice
arch/arm/mach-omap2/Kconfig +1 -0
@@ -36,6 +36,7 @@ config ARCH_OMAP3 select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 select ARCH_HAS_OPP select PM_OPP if PM + select MULTI_IRQ_HANDLER config ARCH_OMAP4 bool "TI OMAP4"
arch/arm/mach-tegra/Kconfig +0 -1
@@ -13,7 +13,6 @@ config ARCH_TEGRA_2x_SOC select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ULPI if USB_SUPPORT select USB_ULPI_VIEWPORT if USB_SUPPORT - select MULTI_IRQ_HANDLER help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
arch/arm/mach-ux500/Kconfig +0 -1
@@ -7,7 +7,6 @@ config UX500_SOC_COMMON select HAS_MTU select ARM_ERRATA_753970 select ARM_ERRATA_754322 - select MULTI_IRQ_HANDLER menu "Ux500 SoC"
arch/arm/plat-omap/Kconfig +0 -1
@@ -22,7 +22,6 @@ config ARCH_OMAP2PLUS select CLKDEV_LOOKUP select GENERIC_IRQ_CHIP select OMAP_DM_TIMER - select MULTI_IRQ_HANDLER help "Systems based on OMAP2, OMAP3 or OMAP4"
Signature · 1 line
1.7.0.4
PATCH v2 16/16 ARM: GIC: Make MULTI_IRQ_HANDLER mandatory
Quoted 39 lines · Marc Zyngier
Now that
MULTI_IRQ_HANDLERis selected by all the in-tree GIC users, make it mandatory and remove the unused macros.Signed-off-by Marc Zyngier <[email protected]>--- arch/arm/Kconfig | 3 - arch/arm/common/Kconfig | 1 + arch/arm/common/gic.c | 2 +- arch/arm/include/asm/hardware/entry-macro-gic.S | 60 ----------------------- arch/arm/include/asm/hardware/gic.h | 1 - arch/arm/mach-msm/Kconfig | 2 - arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-tegra/Kconfig | 1 - arch/arm/mach-ux500/Kconfig | 1 - arch/arm/plat-omap/Kconfig | 1 - 10 files changed, 3 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.Sarch/arm/Kconfig +0
-2@@ -334,7 +334,6 @@ config ARCH_CNS3XXX select ARM_GIC select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI - select MULTI_IRQ_HANDLER help Support for Cavium Networks CNS3XXX platform.@@ -788,7 +787,6 @@ config ARCH_EXYNOS4 select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG - select MULTI_IRQ_HANDLER help Samsung EXYNOS4 series based systems
arch/arm/Kconfig config ARCH_ZYNQ · line 914
Quoted 7 lines
arch/arm/Kconfig +0
-1@@ -911,7 +909,6 @@ config ARCH_ZYNQ select ARM_AMBA select ICST select USE_OF - select MULTI_IRQ_HANDLER help Support for Xilinx Zynq ARM Cortex A9 Platform endchoice
Hi Marc,
I'm unsure about your base. But I have the following platforms in arch/arm/Kconfig selecting MULTI_IRQ_HANDLER at the end of your series, which should also be removed from?
ARCH_REALVIEW
ARCH_VEXPRESS
ARCH_PXA
ARCH_SHMOBILE
Signature · 2 lines
Regards, Shawn
PATCH v2 16/16 ARM: GIC: Make MULTI_IRQ_HANDLER mandatory
Hi Shawn,
Quoted 50 lines · Shawn Guo
Quoted 39 lines · Marc Zyngier
Now that
MULTI_IRQ_HANDLERis selected by all the in-tree GIC users, make it mandatory and remove the unused macros.Signed-off-by Marc Zyngier <[email protected]>--- arch/arm/Kconfig | 3 - arch/arm/common/Kconfig | 1 + arch/arm/common/gic.c | 2 +- arch/arm/include/asm/hardware/entry-macro-gic.S | 60 ----------------------- arch/arm/include/asm/hardware/gic.h | 1 - arch/arm/mach-msm/Kconfig | 2 - arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-tegra/Kconfig | 1 - arch/arm/mach-ux500/Kconfig | 1 - arch/arm/plat-omap/Kconfig | 1 - 10 files changed, 3 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.Sarch/arm/Kconfig +0
-2@@ -334,7 +334,6 @@ config ARCH_CNS3XXX select ARM_GIC select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI - select MULTI_IRQ_HANDLER help Support for Cavium Networks CNS3XXX platform.@@ -788,7 +787,6 @@ config ARCH_EXYNOS4 select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG - select MULTI_IRQ_HANDLER help Samsung EXYNOS4 series based systemsarch/arm/Kconfig config ARCH_ZYNQ · line 914
Quoted 7 lines
arch/arm/Kconfig +0
-1@@ -911,7 +909,6 @@ config ARCH_ZYNQ select ARM_AMBA select ICST select USE_OF - select MULTI_IRQ_HANDLER help Support for Xilinx Zynq ARM Cortex A9 Platform endchoiceHi Marc,
Quoted 6 lines
I'm unsure about your base. But I have the following platforms in
arch/arm/KconfigselectingMULTI_IRQ_HANDLERat the end of your series, which should also be removed from?
ARCH_REALVIEW
ARCH_VEXPRESS
These two can be indeed removed, as they are GIC users and GIC now selects MULTI_IRQ_HANDLER directly. I'll fix the patch.
Quoted 1 line
ARCH_PXA
PXA doesn't use the GIC, so it has to select MULTI_IRQ_HANDLER directly as it used to before my patch.
Quoted 1 line
ARCH_SHMOBILE
This one is caught in the middle. Only SMP shmobile platforms use the GIC, but they all need MULTI_IRQ_HANDLER anyway, so keeping the option selected doesn't hurt.
Cheers,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
PATCH v2 16/16 ARM: GIC: Make MULTI_IRQ_HANDLER mandatory
Quoted 60 lines · Marc Zyngier
Hi Shawn,
Quoted 50 lines · Shawn Guo
Quoted 39 lines · Marc Zyngier
Now that
MULTI_IRQ_HANDLERis selected by all the in-tree GIC users, make it mandatory and remove the unused macros.Signed-off-by Marc Zyngier <[email protected]>--- arch/arm/Kconfig | 3 - arch/arm/common/Kconfig | 1 + arch/arm/common/gic.c | 2 +- arch/arm/include/asm/hardware/entry-macro-gic.S | 60 ----------------------- arch/arm/include/asm/hardware/gic.h | 1 - arch/arm/mach-msm/Kconfig | 2 - arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-tegra/Kconfig | 1 - arch/arm/mach-ux500/Kconfig | 1 - arch/arm/plat-omap/Kconfig | 1 - 10 files changed, 3 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.Sarch/arm/Kconfig +0
-2@@ -334,7 +334,6 @@ config ARCH_CNS3XXX select ARM_GIC select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI - select MULTI_IRQ_HANDLER help Support for Cavium Networks CNS3XXX platform.@@ -788,7 +787,6 @@ config ARCH_EXYNOS4 select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG - select MULTI_IRQ_HANDLER help Samsung EXYNOS4 series based systemsarch/arm/Kconfig config ARCH_ZYNQ · line 914
Quoted 7 lines
arch/arm/Kconfig +0
-1@@ -911,7 +909,6 @@ config ARCH_ZYNQ select ARM_AMBA select ICST select USE_OF - select MULTI_IRQ_HANDLER help Support for Xilinx Zynq ARM Cortex A9 Platform endchoiceHi Marc,
Quoted 6 lines
I'm unsure about your base. But I have the following platforms in
arch/arm/KconfigselectingMULTI_IRQ_HANDLERat the end of your series, which should also be removed from?
ARCH_REALVIEW
ARCH_VEXPRESS
Quoted 8 lines
These two can be indeed removed, as they are GIC users and GIC now selects
MULTI_IRQ_HANDLERdirectly. I'll fix the patch.Quoted 1 line
ARCH_PXAPXA doesn't use the GIC, so it has to select
MULTI_IRQ_HANDLERdirectly as it used to before my patch.
Ah, yes. I missed that the MULTI_IRQ_HANDLER was selected by ARM_GIC in arch/arm/common/Kconfig.
Regards,
Shawn
Quoted 12 lines
Quoted 1 line
ARCH_SHMOBILEThis one is caught in the middle. Only SMP shmobile platforms use the GIC, but they all need
MULTI_IRQ_HANDLERanyway, so keeping the option selected doesn't hurt.Cheers,
M.Signature · 1 line
Jazz is not dead. It just smells funny...
Tony Lindgren
maintainerPATCH v2 16/16 ARM: GIC: Make MULTI_IRQ_HANDLER mandatory
In reply to Marc ZyngierQuoted 4 lines · Marc Zyngier
Now that
MULTI_IRQ_HANDLERis selected by all the in-tree GIC users, make it mandatory and remove the unused macros.Signed-off-by Marc Zyngier <[email protected]>
v2 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierQuoted 2 lines · Marc Zyngier
This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-20110926 plus my PPI series.
Tested on an msm8660.
Signature · 2 lines
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
v2 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
Quoted 9 lines · David Brown
Quoted 2 lines · Marc Zyngier
This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-20110926 plus my PPI series.
Tested on an msm8660.
Tested-by David Brown <[email protected]>Acked-by David Brown <[email protected]>
Tested as well on msm8250.
David
Signature · 2 lines
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
v2 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
Quoted 6 lines · David Brown
Quoted 5 lines · David Brown
Quoted 2 lines · Marc Zyngier
This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-20110926 plus my PPI series.
Quoted 6 lines
Quoted 4 lines
Tested on an msm8660.
Tested-by David Brown <[email protected]>Acked-by David Brown <[email protected]>Tested as well on msm8250.
Awesome. Thanks a lot for testing all of this David.
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
v2 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierQuoted 35 lines · Marc Zyngier
In order to support multiple primary interrupt controllers in the same image, it is necessary to use the
MULTI_IRQ_HANDLERconfig option.This patch series makes a first step in that direction by:
- having the GIC code to provides a global handler,
- make GIC users to provide this handler from their machine descriptor.A side effect of this is that it forces OMAP2/3 platforms to be converted too in order to preserve the
MULTI_OMAPfeature. This leads to a certain simplification of the interrupt handling for the OMAP2/3/4 platforms.The primary IRQ handlers have been written in C, and the performance degradation is hardly noticeable. Should some tests reveal a major increase in latency, it is always possible to restore the ASM version.
This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-20110926 plus my PPI series.
From v1:
- Add forgotten patch to make global handler andMULTI_IRQ_HANDLERmutually exclusive.
- Introducehandle_IPI(), which is similar todo_IP()and callable from C code.Marc Zyngier (16):
ARM: Make global handler andCONFIG_MULTI_IRQ_HANDLERmutually
exclusive
ARM: smp: Add an IPI handler callable from C code
ARM: GIC: Add globalgic_handle_irq()function
ARM: RealView: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: VExpress: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: msm: convert SMP platforms toCONFIG_MULTI_IRQ_HANDLER
ARM: GIC: Add globalgic_handle_irq_offset()function
ARM: exynos4: convert toCONFIG_MULTI_IRQ_HANDLER
Quoted 9 lines
ARM: tegra2: convert to
CONFIG_MULTI_IRQ_HANDLER
ARM: ux500: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: shmobile: convert smp platforms togic_handle_irq()
ARM: cns3xxx: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: zynq: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions
ARM: omap2plus: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: GIC: MakeMULTI_IRQ_HANDLERmandatory
On imx6q:
Signature · 2 lines
Regards, Shawn
v2 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
Quoted 45 lines · Shawn Guo
Quoted 35 lines · Marc Zyngier
In order to support multiple primary interrupt controllers in the same image, it is necessary to use the
MULTI_IRQ_HANDLERconfig option.This patch series makes a first step in that direction by:
- having the GIC code to provides a global handler,
- make GIC users to provide this handler from their machine descriptor.A side effect of this is that it forces OMAP2/3 platforms to be converted too in order to preserve the
MULTI_OMAPfeature. This leads to a certain simplification of the interrupt handling for the OMAP2/3/4 platforms.The primary IRQ handlers have been written in C, and the performance degradation is hardly noticeable. Should some tests reveal a major increase in latency, it is always possible to restore the ASM version.
This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-20110926 plus my PPI series.
From v1:
- Add forgotten patch to make global handler andMULTI_IRQ_HANDLERmutually exclusive.
- Introducehandle_IPI(), which is similar todo_IP()and callable from C code.Marc Zyngier (16):
ARM: Make global handler andCONFIG_MULTI_IRQ_HANDLERmutually
exclusive
ARM: smp: Add an IPI handler callable from C code
ARM: GIC: Add globalgic_handle_irq()function
ARM: RealView: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: VExpress: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: msm: convert SMP platforms toCONFIG_MULTI_IRQ_HANDLER
ARM: GIC: Add globalgic_handle_irq_offset()function
ARM: exynos4: convert toCONFIG_MULTI_IRQ_HANDLERQuoted 9 lines
ARM: tegra2: convert to
CONFIG_MULTI_IRQ_HANDLER
ARM: ux500: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: shmobile: convert smp platforms togic_handle_irq()
ARM: cns3xxx: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: zynq: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions
ARM: omap2plus: convert toCONFIG_MULTI_IRQ_HANDLER
ARM: GIC: MakeMULTI_IRQ_HANDLERmandatory
Quoted 4 lines
On imx6q:
Tested-by Shawn Guo <[email protected]>
Thanks for testing.
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Tony Lindgren
maintainerv2 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
In reply to Marc ZyngierHi Marc,
Quoted 11 lines · Marc Zyngier
In order to support multiple primary interrupt controllers in the same image, it is necessary to use the
MULTI_IRQ_HANDLERconfig option.This patch series makes a first step in that direction by:
- having the GIC code to provides a global handler,
- make GIC users to provide this handler from their machine descriptor.A side effect of this is that it forces OMAP2/3 platforms to be converted too in order to preserve the
MULTI_OMAPfeature. This leads to a certain simplification of the interrupt handling for the OMAP2/3/4 platforms.
That's nice :)
Quoted 6 lines
The primary IRQ handlers have been written in C, and the performance degradation is hardly noticeable. Should some tests reveal a major increase in latency, it is always possible to restore the ASM version.
This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-20110926 plus my PPI series.
I gave this series a quick try, it works except with all the patches applied omap2plus_defconfig will failt to boot on omap4. It seems that the issue is somewhere in the GIC related patches, the last one just enables the MULTI_IRQ..
Care to give it a try on your Panda and see if omap2plus_defconfig works for you with this series?
Looks like disabling CONFIG_SMP made it omap4 boot again.
Regards,
Tony
Tony Lindgren
maintainerv2 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER
Quoted 11 lines · Tony Lindgren
Quoted 3 lines · Marc Zyngier
This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2 and Harmony. Patches against next-20110926 plus my PPI series.
I gave this series a quick try, it works except with all the patches applied
omap2plus_defconfigwill failt to boot on omap4. It seems that the issue is somewhere in the GIC related patches, the last one just enables theMULTI_IRQ..
Quoted 4 lines
Care to give it a try on your Panda and see if
omap2plus_defconfigworks for you with this series?Looks like disabling
CONFIG_SMPmade it omap4 boot again.
Nevermind, looks like I was missing the PPI series.. No wonder I had to do some rebasing to get the patches to apply..
Booting just fine now, will ack some patches separately. Gave the PPI + MULTI_IRQ series a quick boot test on n800, 2430sdp, n900, zoom3 and blaze. So that pretty much covers omap2, 3 & 4.
Regards,
Tony