add initial imx6q support

This patch series adds the initial support for imx6q, which is a Cortex-A9 Quad Core based SoC.

We chose to add imx6q support into mach-imx other than mach-mx5 or a new mach-mx6, because we intend to merge mach-mx5 into mach-imx, so that we have only mach-imx for imx family.

It's based on linux-next-20110926 with some prerequisite patches not showing up on linux-next applied.

Changes since v3:
* Fold the gic_handle_irq (local to imx) support patch in the series. It can be replaced by Marc Zyngier's global gic_handle_irq support with a little rework if his PPI and MULTI_IRQ_HANDLER series gets merged.

Changes since v2:
* Refine the L2 register save/restore implementation per Lorenzo's suggestion
* Rebase to Rob's latest GIC OF bindings series
* Rebase to Sascha's MULTI_IRQ_HANDLER support series

Changes since v1:
* Use the existing IMX_IO_P2V for static mapping
* Fix the MXC_INTERNAL_IRQS breakage introduced by GIC definition
* Retrieve clock frequency for fixed clocks from device tree
* Drop early_initcall from imx_src_init() and call it from imx6q platform initialization
* Use readl_relaxed/writel_relaxed rather than __raw_readl/__raw_writel as suggested by Arnd
* Kill unnecessary imx_local_timer_pre_suspend/resume functions
* Kill Kconfig symbol MACH_IMX6Q
* Rebase to rmk's "Add L2 cache cleaning to generic CPU suspend" series so that we can retain L2 cache with necessary L2 register save/restore across suspend/resume cycle
* Rebase to Rob's new "GIC OF bindings" series

Thanks.

Shawn Guo (7):
arm/imx6q: add device tree source
arm/imx6q: add core definitions and low-level debug uart arm/imx: add gic_handle_irq function arm/imx6q: add core drivers clock, gpc, mmdc and src arm/imx6q: add smp and cpu hotplug support arm/imx6q: add device tree machine support arm/imx6q: add suspend/resume support

 Documentation/devicetree/bindings/arm/fsl.txt |    6 +
 arch/arm/Kconfig                              |    2 +-
 arch/arm/Kconfig.debug                        |    7 +
 arch/arm/Makefile                             |    1 +
 arch/arm/boot/dts/imx6q-sabreauto.dts         |   82 +
 arch/arm/boot/dts/imx6q.dtsi                  |  555 +++++++
 arch/arm/mach-imx/Kconfig                     |   28 +
 arch/arm/mach-imx/Makefile                    |   11 +
 arch/arm/mach-imx/Makefile.boot               |    4 +
 arch/arm/mach-imx/clock-imx6q.c               | 2012 +++++++++++++++++++++++++
 arch/arm/mach-imx/gpc.c                       |  113 ++
 arch/arm/mach-imx/head-v7.S                   |  103 ++
 arch/arm/mach-imx/hotplug.c                   |   44 +
 arch/arm/mach-imx/lluart.c                    |   32 +
 arch/arm/mach-imx/localtimer.c                |   35 +
 arch/arm/mach-imx/mach-imx6q.c                |   84 +
 arch/arm/mach-imx/mmdc.c                      |   72 +
 arch/arm/mach-imx/platsmp.c                   |   85 ++
 arch/arm/mach-imx/pm-imx6q.c                  |   90 ++
 arch/arm/mach-imx/src.c                       |   49 +
 arch/arm/mm/Kconfig                           |    2 +-
 arch/arm/plat-mxc/Kconfig                     |    7 +
 arch/arm/plat-mxc/Makefile                    |    2 +-
 arch/arm/plat-mxc/gic.c                       |   47 +
 arch/arm/plat-mxc/include/mach/common.h       |   29 +
 arch/arm/plat-mxc/include/mach/debug-macro.S  |    2 +
 arch/arm/plat-mxc/include/mach/entry-macro.S  |    6 +
 arch/arm/plat-mxc/include/mach/hardware.h     |    6 +
 arch/arm/plat-mxc/include/mach/irqs.h         |   10 +-
 arch/arm/plat-mxc/include/mach/memory.h       |    1 +
 arch/arm/plat-mxc/include/mach/mx6q.h         |   33 +
 31 files changed, 3555 insertions(+), 5 deletions(-)

It adds device tree source and documentation for imx6q platform.

---
 Documentation/devicetree/bindings/arm/fsl.txt |    6 +
 arch/arm/boot/dts/imx6q-sabreauto.dts         |   82 ++++
 arch/arm/boot/dts/imx6q.dtsi                  |  555 +++++++++++++++++++++++++
 3 files changed, 643 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/fsl.txt
 create mode 100644 arch/arm/boot/dts/imx6q-sabreauto.dts
 create mode 100644 arch/arm/boot/dts/imx6q.dtsi

new file mode 100644
index 0000000..345bfc0
@@ -0,0 +1,6 @@
+Freescale i.MX Platforms Device Tree Bindings
+-----------------------------------------------
+
+i.MX6 Quad SABRE Automotive Board
+Required root node properties:
+    - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";

1.7.4.1

It adds the core definitions and low-level debug uart support for imx6q.

---
 arch/arm/Kconfig                             |    2 +-
 arch/arm/Kconfig.debug                       |    7 +++++
 arch/arm/Makefile                            |    1 +
 arch/arm/mach-imx/Kconfig                    |   14 +++++++++++
 arch/arm/mach-imx/Makefile                   |    2 +
 arch/arm/mach-imx/Makefile.boot              |    4 +++
 arch/arm/mach-imx/lluart.c                   |   32 +++++++++++++++++++++++++
 arch/arm/plat-mxc/Kconfig                    |    7 +++++
 arch/arm/plat-mxc/include/mach/debug-macro.S |    2 +
 arch/arm/plat-mxc/include/mach/hardware.h    |    6 ++++
 arch/arm/plat-mxc/include/mach/irqs.h        |   10 ++++++-
 arch/arm/plat-mxc/include/mach/memory.h      |    1 +
 arch/arm/plat-mxc/include/mach/mx6q.h        |   33 ++++++++++++++++++++++++++
 13 files changed, 118 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-imx/lluart.c
 create mode 100644 arch/arm/plat-mxc/include/mach/mx6q.h

index 5cafa03..58d9343 100644
@@ -1363,7 +1363,7 @@ config SMP
 	depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
 		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
 		 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
-		 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
+		 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || SOC_IMX6Q
 	select USE_GENERIC_SMP_HELPERS
 	select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
 	help

index add32ff..ba206e0 100644
@@ -155,6 +155,13 @@ choice
 		  Say Y here if you want kernel low-level debugging support
 		  on i.MX50 or i.MX53.
 
+	config DEBUG_IMX6Q_UART
+		bool "i.MX6Q Debug UART"
+		depends on SOC_IMX6Q
+		help
+		  Say Y here if you want kernel low-level debugging support
+		  on i.MX6Q.
+
 	config DEBUG_S3C_UART0
 		depends on PLAT_SAMSUNG
 		bool "Use S3C UART 0 for low-level debug"

index 30b9201..fc36c1b 100644
@@ -160,6 +160,7 @@ machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
 machine-$(CONFIG_ARCH_MX3)		:= imx
 machine-$(CONFIG_ARCH_MX5)		:= mx5
+machine-$(CONFIG_ARCH_MX6)		:= imx
 machine-$(CONFIG_ARCH_MXS)		:= mxs
 machine-$(CONFIG_ARCH_NETX)		:= netx
 machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik

index 46cf2c5..4586edf 100644
@@ -592,3 +592,17 @@ config MACH_VPR200
 	  configurations for the board and its peripherals.
 
 endif
+
+if ARCH_MX6
+comment "i.MX6 family:"
+
+config SOC_IMX6Q
+	bool "i.MX6 Quad support"
+	select ARM_GIC
+	select CPU_V7
+	select USE_OF
+
+	help
+	  This enables support for Freescale i.MX6 Quad processor.
+
+endif

index d22096a..d291bc5 100644
@@ -61,3 +61,5 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
+
+obj-$(CONFIG_DEBUG_LL) += lluart.o

index dbe6120..22d8588 100644
@@ -17,3 +17,7 @@ initrd_phys-$(CONFIG_MACH_MX27)	:= 0xA0800000
 zreladdr-$(CONFIG_ARCH_MX3)	+= 0x80008000
 params_phys-$(CONFIG_ARCH_MX3)	:= 0x80000100
 initrd_phys-$(CONFIG_ARCH_MX3)	:= 0x80800000
+
+zreladdr-$(CONFIG_SOC_IMX6Q)	+= 0x10008000
+params_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10000100
+initrd_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10800000

new file mode 100644
index 0000000..d4ab6f2
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <asm/page.h>
+#include <asm/sizes.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+
+static struct map_desc imx_lluart_desc = {
+#ifdef CONFIG_DEBUG_IMX6Q_UART
+	.virtual	= MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
+	.pfn		= __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
+	.length		= MX6Q_UART4_SIZE,
+	.type		= MT_DEVICE,
+#endif
+};
+
+void __init imx_lluart_map_io(void)
+{
+	if (imx_lluart_desc.virtual)
+		iotable_init(&imx_lluart_desc, 1);
+}

index 502e45f..e2e3e5a 100644
@@ -29,6 +29,13 @@ config ARCH_MX5
 	  This enables support for machines using Freescale's i.MX50 and i.MX51
 	  processors.
 
+config ARCH_MX6
+	bool "i.MX6"
+	select AUTO_ZRELADDR
+	select ARM_PATCH_PHYS_VIRT
+	help
+	  This enables support for systems based on the Freescale i.MX6 family
+
 endchoice
 
 source "arch/arm/mach-imx/Kconfig"

index 07cfdbe..f2ce2cb 100644
@@ -24,6 +24,8 @@
 #define UART_PADDR	MX51_UART1_BASE_ADDR
 #elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
 #define UART_PADDR	MX53_UART1_BASE_ADDR
+#elif defined (CONFIG_DEBUG_IMX6Q_UART)
+#define UART_PADDR	MX6Q_UART4_BASE_ADDR
 #endif
 
 #define UART_VADDR	IMX_IO_ADDRESS(UART_PADDR)

index eba3118..a599f01 100644
@@ -91,6 +91,11 @@
  *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000
  *	AIPS1	0x53f00000+0x100000	->	0xf5700000+0x100000
  *	AIPS2	0x63f00000+0x100000	->	0xf5300000+0x100000
+ * mx6q:
+ *	SCU	0x00a00000+0x001000	->	0xf4000000+0x001000
+ *	CCM	0x020c4000+0x004000	->	0xf42c4000+0x004000
+ *	ANATOP	0x020c8000+0x001000	->	0xf42c8000+0x001000
+ *	UART4	0x021f0000+0x004000	->	0xf42f0000+0x004000
  */
 #define IMX_IO_P2V(x)	(						\
 			0xf4000000 +					\

@@ -102,6 +107,7 @@
 
 #include <mach/mxc.h>
 
+#include <mach/mx6q.h>
 #include <mach/mx50.h>
 #include <mach/mx51.h>
 #include <mach/mx53.h>

index 00e812b..fd9efb0 100644
@@ -14,9 +14,15 @@
 #include <asm-generic/gpio.h>
 
 /*
- * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
+ * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
+ * have 128 IRQs, and those with AVIC have 64.
+ *
+ * To support single image, the biggest number should be defined on
+ * top of the list.
  */
-#ifdef CONFIG_MXC_TZIC
+#if defined CONFIG_ARM_GIC
+#define MXC_INTERNAL_IRQS	160
+#elif defined CONFIG_MXC_TZIC
 #define MXC_INTERNAL_IRQS	128
 #else
 #define MXC_INTERNAL_IRQS	64

index ae3541d..80e5bf2 100644
@@ -19,6 +19,7 @@
 #define MX50_PHYS_OFFSET	UL(0x70000000)
 #define MX51_PHYS_OFFSET	UL(0x90000000)
 #define MX53_PHYS_OFFSET	UL(0x70000000)
+#define MX6Q_PHYS_OFFSET	UL(0x10000000)
 
 #if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
 # if defined CONFIG_ARCH_MX3

new file mode 100644
index 0000000..254a561
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_MX6Q_H__
+#define __MACH_MX6Q_H__
+
+#define MX6Q_IO_P2V(x)			IMX_IO_P2V(x)
+#define MX6Q_IO_ADDRESS(x)		IOMEM(MX6Q_IO_P2V(x))
+
+/*
+ * The following are the blocks that need to be statically mapped.
+ * For other blocks, the base address really should be retrieved from
+ * device tree.
+ */
+#define MX6Q_SCU_BASE_ADDR		0x00a00000
+#define MX6Q_SCU_SIZE			0x1000
+#define MX6Q_CCM_BASE_ADDR		0x020c4000
+#define MX6Q_CCM_SIZE			0x4000
+#define MX6Q_ANATOP_BASE_ADDR		0x020c8000
+#define MX6Q_ANATOP_SIZE		0x1000
+#define MX6Q_UART4_BASE_ADDR		0x021f0000
+#define MX6Q_UART4_SIZE			0x4000
+
+#endif	/* __MACH_MX6Q_H__ */

1.7.4.1

Right. This is going to be 'select AUTO_ZRELADDR if !ZBOOT_ROM'.

Regards,
Shawn

This is a plain translation of assembly gic irq handler to C function for CONFIG_MULTI_IRQ_HANDLER support on imx family.

---
 arch/arm/plat-mxc/Makefile                   |    2 +-
 arch/arm/plat-mxc/gic.c                      |   47 ++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h      |    2 +
 arch/arm/plat-mxc/include/mach/entry-macro.S |    6 +++
 4 files changed, 56 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/plat-mxc/gic.c

index d53c35f..b9f0f5f 100644
@@ -5,7 +5,7 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
 
-# MX51 uses the TZIC interrupt controller, older platforms use AVIC
+obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
 

index 9f15a79..988fa9a 100644
@@ -75,6 +75,7 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
+void gic_handle_irq(struct pt_regs *);
 
 #define imx1_handle_irq avic_handle_irq
 #define imx21_handle_irq avic_handle_irq

@@ -85,5 +86,6 @@ void tzic_handle_irq(struct pt_regs *);
 #define imx50_handle_irq tzic_handle_irq
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
+#define imx6q_handle_irq gic_handle_irq
 
 #endif

index 842fbcb..9fe0dfc 100644
@@ -22,3 +22,9 @@
 
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	.endm
+
+	.macro test_for_ipi, irqnr, irqstat, base, tmp
+	.endm
+
+	.macro test_for_ltirq, irqnr, irqstat, base, tmp
+	.endm

1.7.4.1

Can you please share your position on Marc's PPI and GIC MULTI_IRQ_HANDLER series? Are you possibly going to merge them in the coming merge window? If you are, I would directly move my imx6q onto those series and save the local gic_handle_irq(). Otherwise, I may have to add a wrapper for do_IPI() and do_local_timer() to work around the pt_regs issue you pointed out here.

Regards,
Shawn

My personal opinion of Marc's PPI patches hasn't changed: I think integrating them into genirq just makes the whole thing a lot more complicated (and error-prone) than it otherwise needs to be.

For example, it is completely invalid to call any of the existing genirq APIs for a PPI interrupt, because there is no sane way to ensure that the intended CPU is targetted - unless we're operating from a thread which is bound specifically to a single CPU.

However, Marc has been working with Thomas to produce something more generic (and not ARM specific) and I don't have an opinion on that. This addresses the issues (like the one I mention above) but I've not been following it any further than that.

I'm also wondering the consequence of not doing so, because we are seeing icip_handle_irq() and ichp_handle_irq() (arch/arm/mach-pxa/irq.c) are doing the same thing, and we are not running into any problem with above code.

Regards,
Shawn

Sorry. Please ignore the above.

Regards,
Shawn

It adds a number of core drivers support for imx6q, including clock, General Power Controller (gpc), Multi Mode DDR Controller(mmdc) and System Reset Controller (src).

---
 arch/arm/mach-imx/Kconfig       |   13 +
 arch/arm/mach-imx/Makefile      |    4 +
 arch/arm/mach-imx/clock-imx6q.c | 2012 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/gpc.c         |  113 +++
 arch/arm/mach-imx/mmdc.c        |   72 ++
 arch/arm/mach-imx/src.c         |   49 +
 6 files changed, 2263 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-imx/clock-imx6q.c
 create mode 100644 arch/arm/mach-imx/gpc.c
 create mode 100644 arch/arm/mach-imx/mmdc.c
 create mode 100644 arch/arm/mach-imx/src.c

index 4586edf..7555410 100644
@@ -1,5 +1,15 @@
 config IMX_HAVE_DMA_V1
 	bool
+
+config HAVE_IMX_GPC
+	bool
+
+config HAVE_IMX_MMDC
+	bool
+
+config HAVE_IMX_SRC
+	bool
+
 #
 # ARCH_MX31 and ARCH_MX35 are left for compatibility
 # Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.

@@ -600,6 +610,9 @@ config SOC_IMX6Q
 	bool "i.MX6 Quad support"
 	select ARM_GIC
 	select CPU_V7
+	select HAVE_IMX_GPC
+	select HAVE_IMX_MMDC
+	select HAVE_IMX_SRC
 	select USE_OF
 
 	help

index d291bc5..c71e3c5 100644
@@ -63,3 +63,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
 obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
 
 obj-$(CONFIG_DEBUG_LL) += lluart.o
+obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
+obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
+obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o

1.7.4.1

It adds smp and cpu hotplug support for imx6q.

---
 arch/arm/mach-imx/Kconfig               |    1 +
 arch/arm/mach-imx/Makefile              |    5 ++
 arch/arm/mach-imx/head-v7.S             |   71 ++++++++++++++++++++++++++
 arch/arm/mach-imx/hotplug.c             |   44 ++++++++++++++++
 arch/arm/mach-imx/localtimer.c          |   35 +++++++++++++
 arch/arm/mach-imx/platsmp.c             |   85 +++++++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h |    5 ++
 7 files changed, 246 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-imx/head-v7.S
 create mode 100644 arch/arm/mach-imx/hotplug.c
 create mode 100644 arch/arm/mach-imx/localtimer.c
 create mode 100644 arch/arm/mach-imx/platsmp.c

index 7555410..d52fe3d 100644
@@ -610,6 +610,7 @@ config SOC_IMX6Q
 	bool "i.MX6 Quad support"
 	select ARM_GIC
 	select CPU_V7
+	select HAVE_ARM_SCU
 	select HAVE_IMX_GPC
 	select HAVE_IMX_MMDC
 	select HAVE_IMX_SRC

index c71e3c5..67aba68 100644
@@ -66,4 +66,9 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+obj-$(CONFIG_CPU_V7) += head-v7.o
+AFLAGS_head-v7.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SMP) += platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o

new file mode 100644
index 0000000..3a16351
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/clockchips.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <asm/smp_twd.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
+	if (!twd_base) {
+		twd_base = of_iomap(np, 0);
+		WARN_ON(!twd_base);
+	}
+	evt->irq = irq_of_parse_and_map(np, 0);
+	twd_timer_setup(evt);
+
+	return 0;
+}

index 988fa9a..855c214 100644
@@ -88,4 +88,9 @@ void gic_handle_irq(struct pt_regs *);
 #define imx53_handle_irq tzic_handle_irq
 #define imx6q_handle_irq gic_handle_irq
 
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+#ifdef CONFIG_SMP
+extern void v7_secondary_startup(void);
+#endif
 #endif

1.7.4.1

It adds generic device tree based machine support for imx6q.

---
 arch/arm/mach-imx/Makefile              |    2 +-
 arch/arm/mach-imx/mach-imx6q.c          |   84 +++++++++++++++++++++++++++++++
 arch/arm/mm/Kconfig                     |    2 +-
 arch/arm/plat-mxc/include/mach/common.h |   13 +++++
 4 files changed, 99 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-imx/mach-imx6q.c

index 67aba68..31c8602 100644
@@ -71,4 +71,4 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o

index 2df5504..6dc9967 100644
@@ -835,7 +835,7 @@ config CACHE_L2X0
 		   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
 		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
 		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX
+		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_MX6
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC

index 855c214..571e91d 100644
@@ -64,6 +64,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
 			unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
 			unsigned long ckih1, unsigned long ckih2);
+extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
 	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);

@@ -90,7 +91,19 @@ void gic_handle_irq(struct pt_regs *);
 
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+#ifdef CONFIG_DEBUG_LL
+extern void imx_lluart_map_io(void);
+#else
+static inline void imx_lluart_map_io(void) {}
+#endif
 #ifdef CONFIG_SMP
 extern void v7_secondary_startup(void);
+extern void imx_scu_map_io(void);
+#else
+static inline void imx_scu_map_io(void) {}
 #endif
+extern void imx_enable_cpu(int cpu, bool enable);
+extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+extern void imx_src_init(void);
+extern void imx_gpc_init(void);
 #endif

1.7.4.1

Hi Shawn,

[...]

[...]

Not really. In case of DT, gpio core will dynamically assign gpio range from the end of total number (MXC_GPIO_IRQ_START + ARCH_NR_GPIOS for imx case) for each gpio bank that gets probed. Supposing we have gpio0 ~ gpio6 sorted in dts, we will have the following gpio ranges assigned by gpio core.

gpio0: MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - 32
gpio1: MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - 32 * 2
...
gpio6: MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - 32 * 7

Regards,
Shawn

It adds suspend/resume support for imx6q.

---
 arch/arm/mach-imx/Makefile              |    2 +-
 arch/arm/mach-imx/head-v7.S             |   32 +++++++++++
 arch/arm/mach-imx/pm-imx6q.c            |   90 +++++++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h |    9 +++
 4 files changed, 132 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-imx/pm-imx6q.c

index 31c8602..e6c36b4 100644
@@ -71,4 +71,4 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o

index ede908b..1f6316c 100644
@@ -69,3 +69,35 @@ ENTRY(v7_secondary_startup)
 	b	secondary_startup
 ENDPROC(v7_secondary_startup)
 #endif
+
+ENTRY(pl310_get_save_ptr)
+	ldr	r0, =pl310_pbase
+	mov	pc, lr
+ENDPROC(pl310_get_save_ptr)
+
+/*
+ * The following code is located into the .data section.  This is to
+ * allow pl310_pbase and pl310_aux_ctrl to be accessed with a relative
+ * load as we are running on physical address here.
+ */
+	.data
+	.align
+
+	.macro	pl310_resume
+	adr	r2, pl310_pbase
+	ldmia	r2, {r0, r1}
+	str	r1, [r0, #L2X0_AUX_CTRL]	@ restore aux_ctrl
+	mov	r1, #0x1
+	str	r1, [r0, #L2X0_CTRL]		@ re-enable L2
+	.endm
+
+ENTRY(v7_cpu_resume)
+	bl	v7_invalidate_l1
+	pl310_resume
+	b	cpu_resume
+ENDPROC(v7_cpu_resume)
+
+pl310_pbase:
+	.long	0
+pl310_aux_ctrl:
+	.long	0

index 571e91d..318b995 100644
@@ -13,6 +13,7 @@
 
 struct platform_device;
 struct clk;
+enum mxc_cpu_pwr_mode;
 
 extern void mx1_map_io(void);
 extern void mx21_map_io(void);

@@ -96,14 +97,22 @@ extern void imx_lluart_map_io(void);
 #else
 static inline void imx_lluart_map_io(void) {}
 #endif
+extern void v7_cpu_resume(void);
+extern u32 *pl310_get_save_ptr(void);
 #ifdef CONFIG_SMP
 extern void v7_secondary_startup(void);
 extern void imx_scu_map_io(void);
+extern void imx_smp_prepare(void);
 #else
 static inline void imx_scu_map_io(void) {}
+static inline void imx_smp_prepare(void) {}
 #endif
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern void imx_src_init(void);
 extern void imx_gpc_init(void);
+extern void imx_gpc_pre_suspend(void);
+extern void imx_gpc_post_resume(void);
+extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
+extern void imx6q_pm_init(void);
 #endif

1.7.4.1

How should we best proceed on this series? Sascha, do you want to take the next version into your tree once Shawn has addressed the remaining comments, or should I just take the patches with your Ack?

Shawn, what are the current dependencies? I will have to pull in the other branches that this depends on into the next/soc tree and then wait for those to get merged first before I send this to Linus.

Arnd

Thanks for asking, Arnd.

The latest version (v5) of this series that I will send shortly has the dependencies on the following branches.

* rmk's for-next branch with the following additional patches wait for rmk to apply:
- ARM: l2x0: add empty l2x0_of_init (Rob Herring)
- ARM: cache-l2x0: add resume entry for l2 in secure mode (Barry Song)
- ARM: localtimer: add header linux/errno.h explicitly (Shawn Guo)
- ARM: smp: Add an IPI handler callable from C code (Marc Zyngier)
- ARM: smp: Add a localtimer handler callable from C code (Shawn Guo)

* Rob Herring's "GIC OF bindings" series, currently on

    git://git.jdl.com/software/linux-3.0.git gic-v2

tglx has picked up the two that are irq core related. And I'm not sure about the branch that Rob will push others to.

* Branches that will be merged into arm-soc
- Sascha's imx-cleanup
- Sascha's imx-features
- [GIT PULL] DEBUG_LL platform updates for 3.2 (Will Deacon)

Regards,
Shawn