Rework of the TI81xx PRCM support

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new file mode 100644
index 0000000..d48e5fc
@@ -0,0 +1,32 @@
+/*
+ * TI81XX PRCM register access functions
+ *
+ * Copyright (C) 2010-2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#include "prcm81xx.h"
+
+static u32 ti81xx_prcm_inst_read(u16 inst, u16 offs)
+{
+	return __raw_readl(prm_base + inst + offs);
+}
+
+static void ti81xx_prcm_inst_write(u32 v, u16 inst, u16 offs)
+{
+	__raw_writel(v, prm_base + inst + offs);
+}
+
+

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index 8febd84..b3d51f2 100644
@@ -218,6 +218,7 @@ extern void omap44xx_powerdomains_init(void);
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
 extern struct pwrdm_ops omap4_pwrdm_operations;
+extern struct pwrdm_ops ti81xx_pwrdm_operations;
 
 /* Common Internal functions used across OMAP rev's */
 extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);

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new file mode 100644
index 0000000..8eda6b0
@@ -0,0 +1,23 @@
+/*
+ * OMAP81xx PRCM register bits
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *
+ * Paul Walmsley (paul at pwsan.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_REGBITS_81XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_REGBITS_81XX_H
+
+/*
+ * Used by PM_ACTIVE_PWRSTST, PM_HDVICP_PWRSTST, PM_ISP_PWRSTST,
+ * PM_DSS_PWRSTST, PM_SGX_PWRSTST
+ */
+#define TI81XX_MEM_STATEST_SHIFT				4
+#define TI81XX_MEM_STATEST_MASK					(0x3 << 4)
+
+#endif

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index fd0a174..e0c20b9 100644
@@ -188,6 +188,20 @@
 #define TI81XX_CM_ALWON_SR_1_CLKCTRL_OFFSET		0x020C
 #define TI81XX_CM_ALWON_SR_1_CLKCTRL			TI81XX_CM_REGADDR(TI81XX_CM_ALWON_INST, 0x020C)
 
+/*
+ * Register offset aliases (for clearer code,@least in theory)
+ */
+#define TI81XX_PM_PWRSTCTRL_OFFSET			TI81XX_PRM_ACTIVE_PM_PWRSTCTRL_OFFSET
+#define TI81XX_PM_PWRSTST_OFFSET			TI81XX_PRM_ACTIVE_PM_PWRSTST_OFFSET
+
 /* Function prototypes */
 
+extern void ti81xx_prcm_pwrdm_set_powerstate(u16 offs, u8 pwrst);
+extern u8 ti81xx_prcm_pwrdm_read_powerstate(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_powerstatest(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_logicstatest(u16 offs);
+extern u8 ti81xx_prcm_pwrdm_read_mem_statest(u16 offs);
+extern void ti81xx_prcm_pwrdm_set_lowpowerstatechange(u16 offs);
+extern int ti81xx_prcm_pwrdm_wait_transition(u16 offs);
+
 #endif

index d59feec..bad2edb 100644
@@ -350,6 +350,7 @@ void __init omap2_init_common_infrastructure(void)
 		omap2430_hwmod_init();
 	} else if (cpu_is_omap34xx()) {
 		omap3xxx_powerdomains_init();
+		ti81xx_powerdomains_init();
 		omap3xxx_clockdomains_init();
 		omap3xxx_hwmod_init();
 	} else if (cpu_is_omap44xx()) {

index b3d51f2..b9e7ab2 100644
@@ -214,6 +214,7 @@ extern void omap242x_powerdomains_init(void);
 extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
+extern void ti81xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;

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index f7b5860..9c7c5e9 100644
@@ -202,6 +202,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
 extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_ops ti81xx_clkdm_operations;
 
 extern struct clkdm_dep gfx_24xx_wkdeps[];
 extern struct clkdm_dep dsp_24xx_wkdeps[];

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index e0c20b9..19a7b40 100644
@@ -203,5 +203,10 @@ extern u8 ti81xx_prcm_pwrdm_read_logicstatest(u16 offs);
 extern u8 ti81xx_prcm_pwrdm_read_mem_statest(u16 offs);
 extern void ti81xx_prcm_pwrdm_set_lowpowerstatechange(u16 offs);
 extern int ti81xx_prcm_pwrdm_wait_transition(u16 offs);
+extern void ti81xx_prcm_clkdm_enable_hwsup(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_disable_hwsup(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_force_sleep(s16 inst, u16 offs);
+extern void ti81xx_prcm_clkdm_force_wakeup(s16 inst, u16 offs);
+extern bool ti81xx_prcm_is_clkdm_in_hwsup(s16 inst, u16 offs);
 
 #endif

index 9c7c5e9..3f1b310 100644
@@ -196,6 +196,8 @@ extern void __init omap242x_clockdomains_init(void);
 extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
+extern void __init ti81xx_clockdomains_init(void);
+
 extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
 

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index bad2edb..2d26820 100644
@@ -352,6 +352,7 @@ void __init omap2_init_common_infrastructure(void)
 		omap3xxx_powerdomains_init();
 		ti81xx_powerdomains_init();
 		omap3xxx_clockdomains_init();
+		ti81xx_clockdomains_init();
 		omap3xxx_hwmod_init();
 	} else if (cpu_is_omap44xx()) {
 		omap44xx_powerdomains_init();