TVP514x V4L int device driver support

1/2

---
 include/configs/am3517_evm.h |  293 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/am3517_evm.h
new file mode 100644
index 0000000..d7eef73
@@ -0,0 +1,293 @@
+/*
+ * am3517_evm.h - Configuration settings for the TI's AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <[email protected]>
+ *
+ * Derived from evm code
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ			/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+/*
+ * DDR size interfaced
+ */
+#define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+#undef CONFIG_CMD_NET
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT		"AM3517_EVM # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */

1.6.2.4
---
 include/configs/am3517_evm.h |  293 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/am3517_evm.h
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Es sind ?berhaupt nur die Dummk?pfe, die sich den Befehlen der  M?ch-
tigen  widersetzen.  Um  sie  zu ruinieren ist es genug, ihre Befehle
treu zu erf?llen.                  - Peter Hacks: "Die sch?ne Helena"
---
 include/configs/am3517_evm.h |  293
 1 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/am3517_evm.h
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif

---
 include/configs/am3517_evm.h |  293
 1 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/am3517_evm.h
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif

---
 include/configs/am3517_evm.h |  293
 1 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/am3517_evm.h
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif

+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The IQ of the group is the lowest IQ of a member of the group divided
by the number of people in the group.
---
 include/asm-arm/arch-omap3/mux.h |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)
index 0c01c73..9f06fbb 100644
@@ -403,6 +403,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
+#define CONTROL_PADCONF_CCDC_HD         0x01E8
+#define CONTROL_PADCONF_CCDC_VD         0x01EA
+#define CONTROL_PADCONF_CCDC_WEN        0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0      0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1      0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2      0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3      0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4      0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5      0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6      0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7      0x01FC
+#define CONTROL_PADCONF_RMII_MDIO_DATA  0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK   0x0200
+#define CONTROL_PADCONF_RMII_RXD0       0x0202
+#define CONTROL_PADCONF_RMII_RXD1       0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV     0x0206
+#define CONTROL_PADCONF_RMII_RXER       0x0208
+#define CONTROL_PADCONF_RMII_TXD0       0x020A
+#define CONTROL_PADCONF_RMII_TXD1       0x020C
+#define CONTROL_PADCONF_RMII_TXEN       0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK  0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS     0x0212
+#define CONTROL_PADCONF_HECC1_TXD       0x0214
+#define CONTROL_PADCONF_HECC1_RXD       0x0216
+#define CONTROL_PADCONF_SYS_BOOT7       0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N      0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N      0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N      0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N      0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0     0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1     0x0224
+#define CONTROL_PADCONF_SYS_BOOT8       0x0226
 
 #define MUX_VAL(OFFSET,VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));

---
 include/asm-arm/arch-omap3/mux.h |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)
index 0c01c73..9f06fbb 100644

@@ -403,6 +403,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
+#define CONTROL_PADCONF_CCDC_HD         0x01E8
+#define CONTROL_PADCONF_CCDC_VD         0x01EA
+#define CONTROL_PADCONF_CCDC_WEN        0x01EC

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
f u cn rd ths, u cn gt a gd jb n cmptr prgrmmng.
---
 include/asm-arm/arch-omap3/mux.h |   35
 1 files changed, 35 insertions(+), 0 deletions(-)
@@ -403,6 +403,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
+#define CONTROL_PADCONF_CCDC_HD         0x01E8
+#define CONTROL_PADCONF_CCDC_VD         0x01EA
+#define CONTROL_PADCONF_CCDC_WEN        0x01EC

---
 include/asm-arm/arch-omap3/mux.h |   35
 1 files changed, 35 insertions(+), 0 deletions(-)
@@ -403,6 +403,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
+#define CONTROL_PADCONF_CCDC_HD         0x01E8
+#define CONTROL_PADCONF_CCDC_VD         0x01EA
+#define CONTROL_PADCONF_CCDC_WEN        0x01EC

+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
+#define CONTROL_PADCONF_CCDC_HD         0x01E8
+#define CONTROL_PADCONF_CCDC_VD         0x01EA
+#define CONTROL_PADCONF_CCDC_WEN        0x01EC

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The so-called "desktop metaphor" of today's workstations  is  instead
an  "airplane-seat"  metaphor.  Anyone who has shuffled a lap full of
papers while seated between two portly passengers will recognize  the
difference -- one can see only a very few things at once.
                                                   - Fred Brooks, Jr.
---
 cpu/arm_cortexa8/omap3/board.c         |   11 ++-
 cpu/arm_cortexa8/omap3/mem.c           |  110 ++++++++++++++++++++++++++------
 cpu/arm_cortexa8/omap3/sys_info.c      |   12 +++-
 include/asm-arm/arch-omap3/cpu.h       |   26 ++++++++
 include/asm-arm/arch-omap3/mem.h       |   58 ++++++++++++++++-
 include/asm-arm/arch-omap3/sys_proto.h |    4 +
 include/configs/am3517_evm.h           |    6 ++
 include/configs/devkit8000.h           |    4 +
 include/configs/omap3_beagle.h         |    4 +
 include/configs/omap3_evm.h            |    4 +
 include/configs/omap3_overo.h          |    4 +
 include/configs/omap3_pandora.h        |    4 +
 include/configs/omap3_sdp3430.h        |    4 +
 include/configs/omap3_zoom1.h          |    4 +
 include/configs/omap3_zoom2.h          |    4 +
 15 files changed, 233 insertions(+), 26 deletions(-)
index dd2c940..ce60f99 100644
@@ -227,7 +227,11 @@ void s_init(void)
 	per_clocks_enable();
 
 	if (!in_sdram)
+#if defined(CONFIG_SDRC)
 		sdrc_init();
+#elif defined(CONFIG_EMIF4)
+		emif4_init();
+#endif
 }
 
 /******************************************************************************

@@ -276,19 +280,20 @@ int dram_init(void)
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int size0 = 0, size1 = 0;
 
+	size0 = get_sdr_cs_size(CS0);
 	/*
 	 * If a second bank of DDR is attached to CS1 this is
 	 * where it can be started.  Early init code will init
 	 * memory on CS0.
 	 */
 	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+#if defined(CONFIG_SDRC)
 		do_sdrc_init(CS1, NOT_EARLY);
 		make_cs1_contiguous();
+#endif
+		size1 = get_sdr_cs_size(CS1);
 	}
 
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = size0;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);

index 08fb32e..f396898 100644
@@ -109,8 +109,10 @@ u32 get_cpu_rev(void)
  ****************************************************/
 u32 is_mem_sdr(void)
 {
+#if defined(CONFIG_SDRC)
 	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
 		return 1;
+#endif
 	return 0;
 }
 

@@ -121,10 +123,16 @@ u32 get_sdr_cs_size(u32 cs)
 {
 	u32 size;
 
+#if defined(CONFIG_EMIF4)
+	/* TODO: Calculate the size based on EMIF4 configuration */
+	size = CONFIG_SYS_CS0_SIZE;
+#elif defined(CONFIG_SDRC)
 	/* get ram size field */
 	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
 	size &= 0x3FF;		/* remove unwanted bits */
 	size <<= 21;		/* multiply by 2 MiB to find size in MB */
+#endif
+
 	return size;
 }
 

@@ -133,13 +141,15 @@ u32 get_sdr_cs_size(u32 cs)
  ************************************************************************/
 u32 get_sdr_cs_offset(u32 cs)
 {
-	u32 offset;
+	u32 offset = 0;
 
 	if (!cs)
 		return 0;
 
+#if defined(CONFIG_SDRC)
 	offset = readl(&sdrc_base->cs_cfg);
 	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+#endif
 
 	return offset;
 }

index e51c4f3..f9aacb4 100644
@@ -214,6 +214,32 @@ struct sdrc {
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
+/* EMIF4 */
+#ifndef __ASSEMBLY__
+typedef struct emif4 {
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
+#endif /* __ASSEMBLY__ */
+
 #define DLLPHASE_90		(0x1 << 1)
 #define LOADDLL			(0x1 << 2)
 #define ENADLL			(0x1 << 3)

index 34bd515..cfbc84b 100644
@@ -31,8 +31,12 @@ void prcm_init(void);
 void per_clocks_enable(void);
 
 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#elif defined(CONFIG_EMIF4)
+void emif4_init(void);
+#endif
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);

index d7eef73..74e52c1 100644
@@ -62,6 +62,12 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
+
+/*
+ * Support for EMIF4
+ */
+#define CONFIG_EMIF4			1
+
 /*
  * DDR size interfaced
  */

index 1011770..8041416 100644
@@ -66,6 +66,10 @@
 
 /* Hardware drivers */
 
+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1
 

index 024b9b8..7fb3434 100644
@@ -97,6 +97,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1
 
+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1
 

index 36cb5e0..68e0569 100644
@@ -101,6 +101,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1
 
+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1
 

index 0f812a7..7ae4f0c 100644
@@ -89,6 +89,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1
 
+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1
 

index 0cafeb8..45c38bf 100644
@@ -92,6 +92,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1
 
+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1
 

index d91c8ff..a8deab5 100644
@@ -137,6 +137,10 @@
 #define CONFIG_SYS_I2C_BUS_SELECT	1
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Infineon DDR */
 #define CONFIG_OMAP3_INFINEON_DDR	1
 

index 2aef973..17cb3fb 100644
@@ -98,6 +98,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1
 
+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1
 

index 5b03fb6..cf09832 100644
@@ -98,6 +98,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1
 
+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1
 

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
You are an excellent tactician, Captain. You let your second in  com-
mand attack while you sit and watch for weakness.
	-- Khan Noonian Singh, "Space Seed", stardate 3141.9
 MAINTAINERS                            |    4 +
 Makefile                               |    3 +
 board/ti/am3517evm/Makefile            |   47 ++++
 board/ti/am3517evm/am3517evm.c         |   76 ++++++
 board/ti/am3517evm/am3517evm.h         |  400 ++++++++++++++++++++++++++++++++
 board/ti/am3517evm/config.mk           |   29 +++
 cpu/arm_cortexa8/omap3/Makefile        |    6 +
 cpu/arm_cortexa8/omap3/board.c         |   34 +---
 cpu/arm_cortexa8/omap3/emif4.c         |  160 +++++++++++++
 cpu/arm_cortexa8/omap3/mem.c           |   90 -------
 cpu/arm_cortexa8/omap3/sdrc.c          |  186 +++++++++++++++
 cpu/arm_cortexa8/omap3/sys_info.c      |   42 +----
 include/asm-arm/arch-omap3/cpu.h       |   26 ++
 include/asm-arm/arch-omap3/emif4.h     |   77 ++++++
 include/asm-arm/arch-omap3/mem.h       |   24 ++
 include/asm-arm/arch-omap3/mux.h       |   35 +++
 include/asm-arm/arch-omap3/sys_proto.h |    7 +-
 include/configs/am3517_evm.h           |  293 +++++++++++++++++++++++
 include/configs/omap3_beagle.h         |    2 +
 include/configs/omap3_evm.h            |    2 +
 include/configs/omap3_overo.h          |    2 +
 include/configs/omap3_pandora.h        |    2 +
 include/configs/omap3_sdp3430.h        |    2 +
 include/configs/omap3_zoom1.h          |    2 +
 include/configs/omap3_zoom2.h          |    2 +
 25 files changed, 1387 insertions(+), 166 deletions(-)
 create mode 100644 board/ti/am3517evm/Makefile
 create mode 100644 board/ti/am3517evm/am3517evm.c
 create mode 100644 board/ti/am3517evm/am3517evm.h
 create mode 100644 board/ti/am3517evm/config.mk
 create mode 100644 cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 cpu/arm_cortexa8/omap3/sdrc.c
 create mode 100644 include/asm-arm/arch-omap3/emif4.h
 create mode 100644 include/configs/am3517_evm.h
 MAINTAINERS                            |    4 +
 Makefile                               |    3 +
 board/ti/am3517evm/Makefile            |   47 ++++
 board/ti/am3517evm/am3517evm.c         |   76 ++++++
 board/ti/am3517evm/am3517evm.h         |  400
++++++++++++++++++++++++++++++++
 board/ti/am3517evm/config.mk           |   29 +++
 cpu/arm_cortexa8/omap3/Makefile        |    6 +
 cpu/arm_cortexa8/omap3/board.c         |   34 +---
 cpu/arm_cortexa8/omap3/emif4.c         |  160 +++++++++++++
 cpu/arm_cortexa8/omap3/mem.c           |   90 -------
 cpu/arm_cortexa8/omap3/sdrc.c          |  186 +++++++++++++++
 cpu/arm_cortexa8/omap3/sys_info.c      |   42 +----
 include/asm-arm/arch-omap3/cpu.h       |   26 ++
 include/asm-arm/arch-omap3/emif4.h     |   77 ++++++
 include/asm-arm/arch-omap3/mem.h       |   24 ++
 include/asm-arm/arch-omap3/mux.h       |   35 +++
 include/asm-arm/arch-omap3/sys_proto.h |    7 +-
 include/configs/am3517_evm.h           |  293
+++++++++++++++++++++++
 include/configs/omap3_beagle.h         |    2 +
 include/configs/omap3_evm.h            |    2 +
 include/configs/omap3_overo.h          |    2 +
 include/configs/omap3_pandora.h        |    2 +
 include/configs/omap3_sdp3430.h        |    2 +
 include/configs/omap3_zoom1.h          |    2 +
 include/configs/omap3_zoom2.h          |    2 +
 25 files changed, 1387 insertions(+), 166 deletions(-)
 create mode 100644 board/ti/am3517evm/Makefile
 create mode 100644 board/ti/am3517evm/am3517evm.c
 create mode 100644 board/ti/am3517evm/am3517evm.h
 create mode 100644 board/ti/am3517evm/config.mk
 create mode 100644 cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 cpu/arm_cortexa8/omap3/sdrc.c
 create mode 100644 include/asm-arm/arch-omap3/emif4.h
 create mode 100644 include/configs/am3517_evm.h
---
 cpu/arm_cortexa8/omap3/Makefile        |    3 +
 cpu/arm_cortexa8/omap3/board.c         |   34 +------
 cpu/arm_cortexa8/omap3/mem.c           |   90 ---------------
 cpu/arm_cortexa8/omap3/sdrc.c          |  186 ++++++++++++++++++++++++++++++++
 cpu/arm_cortexa8/omap3/sys_info.c      |   42 +-------
 include/asm-arm/arch-omap3/mem.h       |   14 +++
 include/asm-arm/arch-omap3/sys_proto.h |    4 +-
 include/configs/omap3_beagle.h         |    2 +
 include/configs/omap3_evm.h            |    2 +
 include/configs/omap3_overo.h          |    2 +
 include/configs/omap3_pandora.h        |    2 +
 include/configs/omap3_sdp3430.h        |    2 +
 include/configs/omap3_zoom1.h          |    2 +
 include/configs/omap3_zoom2.h          |    2 +
 14 files changed, 221 insertions(+), 166 deletions(-)
 create mode 100644 cpu/arm_cortexa8/omap3/sdrc.c
index 136b163..8cc7802 100644
@@ -33,6 +33,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= gpio.o
 COBJS	+= mem.o
+ifdef	CONFIG_SDRC
+COBJS	+= sdrc.o
+endif
 COBJS	+= syslib.o
 COBJS	+= sys_info.o
 COBJS	+= timer.o

index 2aa69b3..0bad682 100644
@@ -40,8 +40,6 @@
 
 extern omap3_sysinfo sysinfo;
 
-extern u32 is_mem_sdr(void);
-
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works

@@ -227,7 +225,7 @@ void s_init(void)
 	per_clocks_enable();
 
 	if (!in_sdram)
-		sdrc_init();
+		mem_init();
 }
 
 /******************************************************************************

@@ -268,36 +266,6 @@ void watchdog_init(void)
 }
 
 /******************************************************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- *****************************************************************************/
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-	}
-
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-
-/******************************************************************************
  * Dummy function to handle errors for EABI incompatibility
  *****************************************************************************/
 void abort(void)

index 9439758..0f3733f 100644
@@ -270,4 +270,18 @@ enum {
 #define PISMO1_ONEN_BASE	ONENAND_MAP
 #define DBG_MPDB_BASE		DEBUG_BASE
 
+#ifndef __ASSEMBLY__
+/*
+ * Function prototypes
+ */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* endif _MEM_H_ */

index 34bd515..34e4e0d 100644
@@ -31,8 +31,10 @@ void prcm_init(void);
 void per_clocks_enable(void);
 
 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#endif
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);

@@ -46,8 +48,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);

index a8abb0e..eeeb324 100644
@@ -37,6 +37,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 52cb202..72b2f72 100644
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_EVM	1	/* working with EVM */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index c72fb9d..d36b8f7 100644
@@ -29,6 +29,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_OVERO	1	/* working with overo */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index f22fab5..f323d76 100644
@@ -32,6 +32,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 4d01933..ce20c9f 100644
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index cdf95c0..22aca38 100644
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 7a8beb8..49bf72f 100644
@@ -39,6 +39,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

---
 cpu/arm_cortexa8/omap3/Makefile        |    3 +
 cpu/arm_cortexa8/omap3/board.c         |   34 +------
 			u32 size)
 {

new file mode 100644
index 0000000..9a46155

@@ -0,0 +1,186 @@
+/*
+ * Functions related to SDRC.
+ *
+ * This file has been created after exctracting and consolidating
+ * the SDRC related content from mem.c and board.c.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *

+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+

+
+	if (!mem_ok(cs))
+		writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/**

+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);

+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+		do_sdrc_init(CS1, NOT_EARLY);
+		make_cs1_contiguous();
+
+		size1 = get_sdr_cs_size(CS1);

---
 cpu/arm_cortexa8/omap3/Makefile        |    3 +
 cpu/arm_cortexa8/omap3/board.c         |   34 +------
 			u32 size)
 {

@@ -0,0 +1,186 @@
+/*
+ * Functions related to SDRC.
+ *
+ * This file has been created after exctracting and consolidating
+ * the SDRC related content from mem.c and board.c.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated -

+ *

+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public

+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+

+
+	if (!mem_ok(cs))
+		writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/**

+int dram_init(void)
+{

+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype ==

+		do_sdrc_init(CS1, NOT_EARLY);
+		make_cs1_contiguous();
+
+		size1 = get_sdr_cs_size(CS1);

 Makefile                                    |    3 +
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    6 +
 arch/arm/cpu/arm_cortexa8/omap3/board.c     |   34 +---
 arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168 +++++++++++
 arch/arm/cpu/arm_cortexa8/omap3/mem.c       |   90 ------
 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c      |  202 +++++++++++++
 arch/arm/cpu/arm_cortexa8/omap3/sys_info.c  |   41 ---
 arch/arm/include/asm/arch-omap3/cpu.h       |   27 ++
 arch/arm/include/asm/arch-omap3/emif4.h     |   79 ++++++
 arch/arm/include/asm/arch-omap3/mem.h       |   13 +
 arch/arm/include/asm/arch-omap3/mux.h       |   36 +++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    7 +-
 board/logicpd/am3517evm/Makefile            |   47 +++
 board/logicpd/am3517evm/am3517evm.c         |   76 +++++
 board/logicpd/am3517evm/am3517evm.h         |  405 +++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk           |   30 ++
 include/configs/am3517_evm.h                |  297 ++++++++++++++++++++
 include/configs/devkit8000.h                |    2 +
 include/configs/omap3_beagle.h              |    2 +
 include/configs/omap3_evm.h                 |    2 +
 include/configs/omap3_overo.h               |    2 +
 include/configs/omap3_pandora.h             |    2 +
 include/configs/omap3_sdp3430.h             |    2 +
 include/configs/omap3_zoom1.h               |    2 +
 include/configs/omap3_zoom2.h               |    2 +
 25 files changed, 1411 insertions(+), 166 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
 create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
 Makefile                                    |    3 +
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    6 +
 arch/arm/cpu/arm_cortexa8/omap3/board.c     |   34 +---
 arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168 +++++++++++
 arch/arm/cpu/arm_cortexa8/omap3/mem.c       |   90 ------
 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c      |  202 +++++++++++++
 arch/arm/cpu/arm_cortexa8/omap3/sys_info.c  |   41 ---
 arch/arm/include/asm/arch-omap3/cpu.h       |   27 ++
 arch/arm/include/asm/arch-omap3/emif4.h     |   79 ++++++
 arch/arm/include/asm/arch-omap3/mem.h       |   13 +
 arch/arm/include/asm/arch-omap3/mux.h       |   36 +++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    7 +-
 board/logicpd/am3517evm/Makefile            |   47 +++
 board/logicpd/am3517evm/am3517evm.c         |   76 +++++
 board/logicpd/am3517evm/am3517evm.h         |  405
+++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk           |   30 ++
 include/configs/am3517_evm.h                |  297 ++++++++++++++++++++
 include/configs/devkit8000.h                |    2 +
 include/configs/omap3_beagle.h              |    2 +
 include/configs/omap3_evm.h                 |    2 +
 include/configs/omap3_overo.h               |    2 +
 include/configs/omap3_pandora.h             |    2 +
 include/configs/omap3_sdp3430.h             |    2 +
 include/configs/omap3_zoom1.h               |    2 +
 include/configs/omap3_zoom2.h               |    2 +
 25 files changed, 1411 insertions(+), 166 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
 create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
---
 include/configs/omap3_evm.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)
index 0d99f7d..1d31731 100644
@@ -151,7 +151,8 @@
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#undef CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 

@@ -306,7 +307,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 

index 0d99f7d..1d31731 100644
@@ -151,7 +151,8 @@
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#undef CONFIG_CMD_ONENAND	/* ONENAND support		*/

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
What is tolerance? -- it is the consequence of humanity. We  are  all
formed  of frailty and error; let us pardon reciprocally each other's
folly -- that is the first law of nature.                  - Voltaire
index 0d99f7d..1d31731 100644
@@ -151,7 +151,8 @@
 

 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#undef CONFIG_CMD_ONENAND	/* ONENAND support		*/

-#define CONFIG_CMD_ONENAND     /* ONENAND support              */
+/*#define CONFIG_CMD_ONENAND*/ /* ONENAND support              */
+#define CONFIG_CMD_NAND        /* NAND support                 */

index 0d99f7d..1d31731 100644
@@ -151,7 +151,8 @@
 

-#define CONFIG_CMD_ONENAND /* ONENAND support ? ? ? ? ? ? ?*/
+#undef CONFIG_CMD_ONENAND ?/* ONENAND support ? ? ? ? ? ? ?*/

-#define CONFIG_CMD_ONENAND ? ? /* ONENAND support ? ? ? ? ? ? ?*/
+/*#define CONFIG_CMD_ONENAND*/ /* ONENAND support ? ? ? ? ? ? ?*/
+#define CONFIG_CMD_NAND ? ? ? ?/* NAND support ? ? ? ? ? ? ? ? */

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Motto of the Electrical Engineer: Working computer hardware is a  lot
like an erect penis: it stays up as long as you don't fuck with it.
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Always leave room to add an explanation if it doesn't work out.
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Honest error is to be pitied, not ridiculed.
                                       -- Philip Earl of Chesterfield
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Why can you only have two doors on a chicken coop? If it had four  it
would be a chicken sedan.
---
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    3 +
 arch/arm/cpu/arm_cortexa8/omap3/board.c     |   35 +-----
 arch/arm/cpu/arm_cortexa8/omap3/mem.c       |   90 ------------
 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c      |  202 +++++++++++++++++++++++++++
 arch/arm/cpu/arm_cortexa8/omap3/sys_info.c  |   41 ------
 arch/arm/include/asm/arch-omap3/cpu.h       |    3 +
 arch/arm/include/asm/arch-omap3/mem.h       |   13 ++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    4 +-
 include/configs/devkit8000.h                |    2 +
 include/configs/omap3_beagle.h              |    2 +
 include/configs/omap3_evm.h                 |    2 +
 include/configs/omap3_overo.h               |    2 +
 include/configs/omap3_pandora.h             |    2 +
 include/configs/omap3_sdp3430.h             |    2 +
 include/configs/omap3_zoom1.h               |    2 +
 include/configs/omap3_zoom2.h               |    2 +
 16 files changed, 240 insertions(+), 167 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
index 136b163..8cc7802 100644
@@ -33,6 +33,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= gpio.o
 COBJS	+= mem.o
+ifdef	CONFIG_SDRC
+COBJS	+= sdrc.o
+endif
 COBJS	+= syslib.o
 COBJS	+= sys_info.o
 COBJS	+= timer.o

index 69a08fd..d2500ca 100644
@@ -40,8 +40,6 @@
 
 extern omap3_sysinfo sysinfo;
 
-extern u32 is_mem_sdr(void);
-
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works

@@ -233,7 +231,7 @@ void s_init(void)
 	per_clocks_enable();
 
 	if (!in_sdram)
-		sdrc_init();
+		mem_init();
 }
 
 /******************************************************************************

@@ -274,37 +272,6 @@ void watchdog_init(void)
 }
 
 /******************************************************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- *****************************************************************************/
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-
-		size1 = get_sdr_cs_size(CS1);
-	}
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-
-/******************************************************************************
  * Dummy function to handle errors for EABI incompatibility
  *****************************************************************************/
 void abort(void)

index aa8de32..a49af10 100644
@@ -183,6 +183,7 @@ struct sms {
 /* SDRC */
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+#if defined(CONFIG_SDRC)
 struct sdrc_cs {
 	u32 mcfg;		/* 0x80 || 0xB0 */
 	u32 mr;			/* 0x84 || 0xB4 */

@@ -215,6 +216,8 @@ struct sdrc {
 	u8 res4[0xC];
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
+
+#endif	/* CONFIG_SDRC */
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 

index 9439758..a78cf9f 100644
@@ -270,4 +270,17 @@ enum {
 #define PISMO1_ONEN_BASE	ONENAND_MAP
 #define DBG_MPDB_BASE		DEBUG_BASE
 
+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif	/* __ASSEMBLY__ */
+
 #endif /* endif _MEM_H_ */

index 34bd515..34e4e0d 100644
@@ -31,8 +31,10 @@ void prcm_init(void);
 void per_clocks_enable(void);
 
 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#endif
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);

@@ -46,8 +48,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);

index 7d1332f..1798bc6 100644
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_DEVKIT8000	1	/* working with DevKit8000 */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 08d79ac..7584063 100644
@@ -37,6 +37,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 1d31731..8c17388 100644
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_EVM	1	/* working with EVM */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index a43500b..5ca9f3a 100644
@@ -29,6 +29,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_OVERO	1	/* working with overo */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 945c053..7c62685 100644
@@ -32,6 +32,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index b4919db..f751592 100644
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index ae7ebf9..30515b0 100644
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index c88c732..2861608 100644
@@ -39,6 +39,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */
 
+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 136b163..8cc7802 100644

@@ -33,6 +33,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= gpio.o
 COBJS	+= mem.o
+ifdef	CONFIG_SDRC
+COBJS	+= sdrc.o
+endif

index aa8de32..a49af10 100644
@@ -183,6 +183,7 @@ struct sms {
 /* SDRC */
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+#if defined(CONFIG_SDRC)
 struct sdrc_cs {
 	u32 mcfg;		/* 0x80 || 0xB0 */
 	u32 mr;			/* 0x84 || 0xB4 */

@@ -215,6 +216,8 @@ struct sdrc {
 	u8 res4[0xC];
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
+
+#endif	/* CONFIG_SDRC */

index 34bd515..34e4e0d 100644
@@ -31,8 +31,10 @@ void prcm_init(void);
 void per_clocks_enable(void);
 
 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#endif

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
People seldom know what they want until you give them what  they  ask
for.
@@ -33,6 +33,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= gpio.o
 COBJS	+= mem.o
+ifdef	CONFIG_SDRC
+COBJS	+= sdrc.o
+endif

@@ -183,6 +183,7 @@ struct sms {
 /* SDRC */
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+#if defined(CONFIG_SDRC)
 struct sdrc_cs {
 	u32 mcfg;		/* 0x80 || 0xB0 */
 	u32 mr;			/* 0x84 || 0xB4 */

@@ -215,6 +216,8 @@ struct sdrc {
 	u8 res4[0xC];
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
+
+#endif	/* CONFIG_SDRC */

@@ -31,8 +31,10 @@ void prcm_init(void);
 void per_clocks_enable(void);
 

 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#endif

@@ -183,6 +183,7 @@ struct sms {
 /* SDRC */
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+#if defined(CONFIG_SDRC)
 struct sdrc_cs {
 	u32 mcfg;		/* 0x80 || 0xB0 */
 	u32 mr;			/* 0x84 || 0xB4 */

@@ -215,6 +216,8 @@ struct sdrc {
 	u8 res4[0xC];
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
+
+#endif	/* CONFIG_SDRC */

@@ -31,8 +31,10 @@ void prcm_init(void);
 void per_clocks_enable(void);
 

 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#endif

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Ahead warp factor 1"                                  - Captain Kirk
---
 Makefile                              |    3 +
 arch/arm/include/asm/arch-omap3/mux.h |   36 +++
 board/logicpd/am3517evm/Makefile      |   47 ++++
 board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h   |  405 +++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk     |   30 +++
 include/configs/am3517_evm.h          |  297 ++++++++++++++++++++++++
 7 files changed, 894 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
index 34f10ce..487ae73 100644
@@ -3169,6 +3169,9 @@ omap3_zoom1_config :	unconfig
 omap3_zoom2_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
 
+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 smdkc100_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
 

index 0c01c73..8ea47b6 100644
@@ -283,6 +283,7 @@
 /*Control and debug */
 #define CONTROL_PADCONF_SYS_32K		0x0A04
 #define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
 #define CONTROL_PADCONF_SYS_NIRQ	0x01E0
 #define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
 #define CONTROL_PADCONF_SYS_BOOT1	0x0A0C

@@ -403,6 +404,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226
 
 #define MUX_VAL(OFFSET,VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));

new file mode 100644
index 0000000..f7a35ce
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <[email protected]>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000

---
 Makefile                              |    3 +
 arch/arm/include/asm/arch-omap3/mux.h |   36 +++
 board/logicpd/am3517evm/Makefile      |   47 ++++
 board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h   |  405 +++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk     |   30 +++
 include/configs/am3517_evm.h          |  297 ++++++++++++++++++++++++
 7 files changed, 894 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
index 34f10ce..487ae73 100644
@@ -3169,6 +3169,9 @@ omap3_zoom1_config :	unconfig
 omap3_zoom2_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
 
+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 smdkc100_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx

index 0c01c73..8ea47b6 100644
@@ -283,6 +283,7 @@
 /*Control and debug */
 #define CONTROL_PADCONF_SYS_32K		0x0A04
 #define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
 #define CONTROL_PADCONF_SYS_NIRQ	0x01E0
 #define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
 #define CONTROL_PADCONF_SYS_BOOT1	0x0A0C

new file mode 100644
index 0000000..3c71fef

+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Any sufficiently advanced technology is indistinguishable from magic.
Clarke's Third Law       - _Profiles of the Future_ (1962; rev. 1973)
                  ``Hazards of Prophecy: The Failure of Imagination''
---
 Makefile                              |    3 +
 arch/arm/include/asm/arch-omap3/mux.h |   36 +++
 board/logicpd/am3517evm/Makefile      |   47 ++++
 board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h   |  405
 board/logicpd/am3517evm/config.mk     |   30 +++
 include/configs/am3517_evm.h          |  297 ++++++++++++++++++++++++
 7 files changed, 894 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
index 34f10ce..487ae73 100644
@@ -3169,6 +3169,9 @@ omap3_zoom1_config :	unconfig
 omap3_zoom2_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
 

+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 smdkc100_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx

@@ -283,6 +283,7 @@
 /*Control and debug */
 #define CONTROL_PADCONF_SYS_32K		0x0A04
 #define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
 #define CONTROL_PADCONF_SYS_NIRQ	0x01E0
 #define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
 #define CONTROL_PADCONF_SYS_BOOT1	0x0A0C

+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It would seem that evil retreats when forcibly confronted
	-- Yarnek of Excalbia, "The Savage Curtain", stardate 5906.5
---
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    3 +
 arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/cpu.h       |   24 ++++
 arch/arm/include/asm/arch-omap3/emif4.h     |   79 +++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    3 +
 5 files changed, 277 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h
index 8cc7802..0a23fa5 100644
@@ -36,6 +36,9 @@ COBJS	+= mem.o
 ifdef	CONFIG_SDRC
 COBJS	+= sdrc.o
 endif
+ifdef	CONFIG_EMIF4
+COBJS	+= emif4.o
+endif
 COBJS	+= syslib.o
 COBJS	+= sys_info.o
 COBJS	+= timer.o

index a49af10..25668bd 100644
@@ -217,6 +217,30 @@ struct sdrc {
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
 
+#elif defined(CONFIG_EMIF4)
+/* EMIF4 */
+typedef struct emif4 {
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
 #endif	/* CONFIG_SDRC */
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */

index 34e4e0d..7b425be 100644
@@ -35,6 +35,9 @@ void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
 #endif
+#if defined(CONFIG_EMIF4)
+void emif4_init(void);
+#endif
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);

---
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    3 +
 arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/cpu.h       |   24 ++++
 arch/arm/include/asm/arch-omap3/emif4.h     |   79 +++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    3 +
 5 files changed, 277 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h
index 8cc7802..0a23fa5 100644

@@ -36,6 +36,9 @@ COBJS	+= mem.o
 ifdef	CONFIG_SDRC
 COBJS	+= sdrc.o
 endif
+ifdef	CONFIG_EMIF4
+COBJS	+= emif4.o
+endif

index 34e4e0d..7b425be 100644
@@ -35,6 +35,9 @@ void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
 #endif
+#if defined(CONFIG_EMIF4)
+void emif4_init(void);
+#endif

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A failure will not appear until a unit has passed final inspection.
---
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    3 +
 arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168
 arch/arm/include/asm/arch-omap3/cpu.h       |   24 ++++
 arch/arm/include/asm/arch-omap3/emif4.h     |   79 +++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    3 +
 5 files changed, 277 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h
@@ -36,6 +36,9 @@ COBJS	+= mem.o
 ifdef	CONFIG_SDRC
 COBJS	+= sdrc.o
 endif
+ifdef	CONFIG_EMIF4
+COBJS	+= emif4.o
+endif

@@ -35,6 +35,9 @@ void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
 #endif
+#if defined(CONFIG_EMIF4)
+void emif4_init(void);
+#endif

+#if defined(CONFIG_EMIF4)
+void emif4_init(void);
+#endif

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Given a choice between two theories, take the one which is funnier.
---
 include/configs/omap3_evm.h |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)
index 0d99f7d..88af492 100644
@@ -151,7 +151,7 @@
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 

@@ -306,7 +306,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 

---
 include/configs/omap3_evm.h |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)
index 0d99f7d..88af492 100644
@@ -151,7 +151,7 @@
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 

@@ -306,7 +306,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
--

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"The glory of creation is in its infinite diversity." "And in the way
our differences combine to create meaning and beauty."
	-- Dr. Miranda Jones and Spock, "Is There in Truth No Beauty?",
	   stardate 5630.8
	-- Dr. Miranda Jones and Spock, "Is There in Truth No Beauty?",
	   stardate 5630.8
---
 arch/arm/cpu/arm_cortexa8/omap3/board.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)
index 7b78fa4..69a08fd 100644
@@ -282,6 +282,8 @@ int dram_init(void)
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int size0 = 0, size1 = 0;
 
+	size0 = get_sdr_cs_size(CS0);
+
 	/*
 	 * If a second bank of DDR is attached to CS1 this is
 	 * where it can be started.  Early init code will init

@@ -290,10 +292,9 @@ int dram_init(void)
 	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
 		do_sdrc_init(CS1, NOT_EARLY);
 		make_cs1_contiguous();
-	}
 
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
+		size1 = get_sdr_cs_size(CS1);
+	}
 
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = size0;

---
 arch/arm/cpu/arm_cortexa8/omap3/board.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)
index 7b78fa4..69a08fd 100644
@@ -282,6 +282,8 @@ int dram_init(void)
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int size0 = 0, size1 = 0;
 
+	size0 = get_sdr_cs_size(CS0);
+
 	/*
 	 * If a second bank of DDR is attached to CS1 this is
 	 * where it can be started.  Early init code will init

@@ -290,10 +292,9 @@ int dram_init(void)
 	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
 		do_sdrc_init(CS1, NOT_EARLY);
 		make_cs1_contiguous();
-	}
 
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
+		size1 = get_sdr_cs_size(CS1);
+	}
 
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = size0;
--

---
 arch/arm/cpu/arm_cortexa8/omap3/board.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)
index 7b78fa4..69a08fd 100644
@@ -282,6 +282,8 @@ int dram_init(void)
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int size0 = 0, size1 = 0;
 
+	size0 = get_sdr_cs_size(CS0);
+
 	/*
 	 * If a second bank of DDR is attached to CS1 this is
 	 * where it can be started.  Early init code will init

@@ -290,10 +292,9 @@ int dram_init(void)
 	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
 		do_sdrc_init(CS1, NOT_EARLY);
 		make_cs1_contiguous();
-	}
 
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
+		size1 = get_sdr_cs_size(CS1);
+	}
 
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = size0;
--

---
 MAINTAINERS                           |    4 +
 MAKEALL                               |    1 +
 Makefile                              |    3 +
 arch/arm/include/asm/arch-omap3/mux.h |   38 +++-
 board/logicpd/am3517evm/Makefile      |   46 ++++
 board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h   |  405 +++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk     |   30 +++
 include/configs/am3517_evm.h          |  296 ++++++++++++++++++++++++
 9 files changed, 898 insertions(+), 1 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
index 5cbc845..0bc65e1 100644
@@ -798,6 +798,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 
+Vaibhav Hiremath <[email protected]>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:

index bb09627..cd59daa 100755
@@ -641,6 +641,7 @@ LIST_ARM11="			\
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="		\
+	am3517_evm		\
 	devkit8000		\
 	mx51evk			\
 	omap3_beagle		\

index 2d96574..57b3491 100644
@@ -3155,6 +3155,9 @@ SMN42_config	:	unconfig
 ## ARM CORTEX Systems
 #########################################################################
 
+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 devkit8000_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
 

index 0c01c73..ffeb982 100644
@@ -283,7 +283,7 @@
 /*Control and debug */
 #define CONTROL_PADCONF_SYS_32K		0x0A04
 #define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
-#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
 #define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
 #define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
 #define CONTROL_PADCONF_SYS_BOOT2	0x0A0E

@@ -337,6 +337,7 @@
 #define CONTROL_PADCONF_ETK_D14_ES2	0x05F8
 #define CONTROL_PADCONF_ETK_D15_ES2	0x05FA
 /*Die to Die */
+#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
 #define CONTROL_PADCONF_D2D_MCAD0	0x01E4
 #define CONTROL_PADCONF_D2D_MCAD1	0x01E6
 #define CONTROL_PADCONF_D2D_MCAD2	0x01E8

@@ -403,6 +404,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226
 
 #define MUX_VAL(OFFSET,VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));

new file mode 100644
index 0000000..f7a35ce
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <[email protected]>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000

---
 MAINTAINERS                           |    4 +
 MAKEALL                               |    1 +
 Makefile                              |    3 +
 arch/arm/include/asm/arch-omap3/mux.h |   38 +++-
 board/logicpd/am3517evm/Makefile      |   46 ++++
 board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h   |  405
+++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk     |   30 +++
 include/configs/am3517_evm.h          |  296 ++++++++++++++++++++++++
 9 files changed, 898 insertions(+), 1 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
index 5cbc845..0bc65e1 100644
@@ -798,6 +798,10 @@ Alex Z
      lart            SA1100
      dnp1110         SA1110
 
+Vaibhav Hiremath <[email protected]>
+
+     am3517_evm      ARM CORTEX-A8 (AM35x SoC)
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:

index bb09627..cd59daa 100755
@@ -641,6 +641,7 @@ LIST_ARM11="                      \
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="         \
+     am3517_evm              \
      devkit8000              \
      mx51evk                 \
      omap3_beagle            \

index 2d96574..57b3491 100644
@@ -3155,6 +3155,9 @@ SMN42_config    :       unconfig
 ## ARM CORTEX Systems
 #########################################################################
 
+am3517_evm_config :  unconfig
+     @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 devkit8000_config :  unconfig
      @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
 

index 0c01c73..ffeb982 100644
@@ -283,7 +283,7 @@
 /*Control and debug */
 #define CONTROL_PADCONF_SYS_32K              0x0A04
 #define CONTROL_PADCONF_SYS_CLKREQ   0x0A06
-#define CONTROL_PADCONF_SYS_NIRQ     0x01E0
+#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
 #define CONTROL_PADCONF_SYS_BOOT0    0x0A0A
 #define CONTROL_PADCONF_SYS_BOOT1    0x0A0C
 #define CONTROL_PADCONF_SYS_BOOT2    0x0A0E

@@ -337,6 +337,7 @@
 #define CONTROL_PADCONF_ETK_D14_ES2  0x05F8
 #define CONTROL_PADCONF_ETK_D15_ES2  0x05FA
 /*Die to Die */
+#define CONTROL_PADCONF_SYS_NIRQ     0x01E0
 #define CONTROL_PADCONF_D2D_MCAD0    0x01E4
 #define CONTROL_PADCONF_D2D_MCAD1    0x01E6
 #define CONTROL_PADCONF_D2D_MCAD2    0x01E8

@@ -403,6 +404,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260
 #define CONTROL_PADCONF_SDRC_CKE0    0x0262
 #define CONTROL_PADCONF_SDRC_CKE1    0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK    0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD   0x01E6
+#define CONTROL_PADCONF_CCDC_HD              0x01E8
+#define CONTROL_PADCONF_CCDC_VD              0x01EA
+#define CONTROL_PADCONF_CCDC_WEN     0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0   0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1   0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2   0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3   0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4   0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5   0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6   0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7   0x01FC
+#define CONTROL_PADCONF_RMII_MDIO_DATA       0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK        0x0200
+#define CONTROL_PADCONF_RMII_RXD0    0x0202
+#define CONTROL_PADCONF_RMII_RXD1    0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV  0x0206
+#define CONTROL_PADCONF_RMII_RXER    0x0208
+#define CONTROL_PADCONF_RMII_TXD0    0x020A
+#define CONTROL_PADCONF_RMII_TXD1    0x020C
+#define CONTROL_PADCONF_RMII_TXEN    0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK       0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS  0x0212
+#define CONTROL_PADCONF_HECC1_TXD    0x0214
+#define CONTROL_PADCONF_HECC1_RXD    0x0216
+#define CONTROL_PADCONF_SYS_BOOT7    0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N   0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N   0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N   0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N   0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0  0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1  0x0224
+#define CONTROL_PADCONF_SYS_BOOT8    0x0226
 
 #define MUX_VAL(OFFSET,VALUE)\
      writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));

new file mode 100644
index 0000000..3a6b1a1
@@ -0,0 +1,46 @@
+#
+# Author: Vaibhav Hiremath <[email protected]>
+#
+# Based on ti/evm/Makefile
+#
+# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB  = $(obj)lib$(BOARD).a
+
+COBJS        := am3517evm.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB):      $(obj).depend $(OBJS)
+     $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+     rm -f $(OBJS)
+
+distclean:   clean
+     rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend

new file mode 100644
index 0000000..2b912a9
@@ -0,0 +1,76 @@
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <[email protected]>
+ *
+ * Based on ti/evm/evm.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517evm.h"
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+     DECLARE_GLOBAL_DATA_PTR;
+
+     gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+     /* board id for Linux */
+     gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+     /* boot param addr */
+     gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+     return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+     i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+     dieid_num_r();
+
+     return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *           hardware. Many pins need to be moved from protect to primary
+ *           mode.
+ */
+void set_muxconf_regs(void)
+{
+     MUX_AM3517EVM();
+}

new file mode 100644
index 0000000..68d746c
@@ -0,0 +1,405 @@
+/*
+ * am3517evm.h - Header file for the AM3517 EVM.
+ *
+ * Author: Vaibhav Hiremath <[email protected]>
+ *
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+     DDR_DISCRETE,
+     "AM3517EVM Board",
+     "NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+     /* SDRC */\
+     MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SDRC_DQS0N),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(SDRC_DQS1N),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(SDRC_DQS2N),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(SDRC_DQS3N),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(SDRC_CKE0),          (M0)) \
+     MUX_VAL(CP(SDRC_CKE1),          (M0)) \
+     /*sdrc_strben_dly0*/\
+     MUX_VAL(CP(STRBEN_DLY0),        (IEN  | PTD | EN  | M0)) \
+      /*sdrc_strben_dly1*/\
+     MUX_VAL(CP(STRBEN_DLY1),        (IEN  | PTD | EN  | M0)) \
+     /* GPMC */\
+     MUX_VAL(CP(GPMC_A1),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A2),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A3),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A4),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A5),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A6),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A7),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A8),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A9),            (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_A10),           (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D0),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D1),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D2),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D3),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D4),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D5),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D6),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D7),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D8),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D9),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D10),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D11),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D12),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D13),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D14),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_D15),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NCS1),          (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NCS2),          (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NCS3),          (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NCS4),          (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NCS6),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(GPMC_NCS7),          (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_CLK),           (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NBE1),          (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(GPMC_WAIT2),         (IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+                                                      /* - ETH_nRESET*/\
+     MUX_VAL(CP(GPMC_WAIT3),         (IEN  | PTU | EN  | M0)) \
+     /* DSS */\
+     MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)) \
+     /* CAMERA */\
+     MUX_VAL(CP(CAM_HS),             (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(CAM_VS),             (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(CAM_XCLKA),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_PCLK),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(CAM_FLD),            (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+                                                      /* - CAM_RESET*/\
+     MUX_VAL(CP(CAM_D0),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D1),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D2),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D3),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D4),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D5),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D6),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D7),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D8),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D9),             (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D10),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_D11),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_XCLKB),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(CAM_WEN),            (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+     MUX_VAL(CP(CAM_STROBE),         (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(CSI2_DX0),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CSI2_DY0),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CSI2_DX1),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CSI2_DY1),           (IEN  | PTD | DIS | M0)) \
+     /* MMC */\
+     MUX_VAL(CP(MMC1_CLK),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | DIS | M0)) \
+     MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | DIS | M0)) \
+     MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | DIS | M0)) \
+     MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | DIS | M0)) \
+     MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | DIS | M0)) \
+     /* WriteProtect */\
+     MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M4)) \
+     MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M4)) /*CardDetect*/\
+     MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M4)) \
+     MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M4)) \
+     \
+     MUX_VAL(CP(MMC2_CLK),           (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(MMC2_CMD),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTD | DIS | M0)) \
+     /* McBSP */\
+     MUX_VAL(CP(MCBSP_CLKS),         (IEN  | PTU | DIS | M0)) \
+     MUX_VAL(CP(MCBSP1_CLKR),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP1_FSR),         (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(MCBSP1_DX),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP1_DR),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP1_FSX),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP1_CLKX),        (IEN  | PTD | DIS | M0)) \
+     \
+     MUX_VAL(CP(MCBSP2_FSX),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP2_CLKX),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP2_DR),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP2_DX),          (IDIS | PTD | DIS | M0)) \
+     \
+     MUX_VAL(CP(MCBSP3_DX),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP3_DR),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP3_CLKX),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCBSP3_FSX),         (IEN  | PTD | DIS | M0)) \
+     \
+     MUX_VAL(CP(MCBSP4_CLKX),        (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+                                                      /* - LCD_INI*/\
+     MUX_VAL(CP(MCBSP4_DR),          (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+                                                      /* - LCD_ENVDD */\
+     MUX_VAL(CP(MCBSP4_DX),          (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+                                                      /* - LCD_QVGA/nVGA */\
+     MUX_VAL(CP(MCBSP4_FSX),         (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+                                                      /* - LCD_RESB */\
+     /* UART */\
+     MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(UART1_RTS),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(UART1_CTS),          (IEN  | PTU | DIS | M0)) \
+     \
+     MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(UART2_CTS),          (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(UART2_RTS),          (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(UART2_TX),           (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(UART2_RX),           (IEN  | PTD | DIS | M0)) \
+     \
+     MUX_VAL(CP(UART3_CTS_RCTX),     (IEN  | PTU | DIS | M0)) \
+     MUX_VAL(CP(UART3_RTS_SD),       (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)) \
+     /* I2C */\
+     MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(I2C2_SCL),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(I2C4_SCL),           (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(I2C4_SDA),           (IEN  | PTU | EN  | M0)) \
+     /* McSPI */\
+     MUX_VAL(CP(MCSPI1_CLK),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCSPI1_SIMO),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCSPI1_CS0),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(MCSPI1_CS1),         (IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+     MUX_VAL(CP(MCSPI1_CS2),         (IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+                                                      /* - LAN_INTR*/\
+     MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTD | EN  | M0)) \
+     \
+     MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTD | EN  | M4)) \
+     MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTD | EN  | M4)) \
+     /* CCDC */\
+     MUX_VAL(CP(CCDC_PCLK),          (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(CCDC_FIELD),         (IEN  | PTD | DIS | M1)) \
+     MUX_VAL(CP(CCDC_HD),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(CCDC_VD),            (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(CCDC_WEN),           (IEN  | PTD | DIS | M1)) \
+     MUX_VAL(CP(CCDC_DATA0),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CCDC_DATA1),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CCDC_DATA2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CCDC_DATA3),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CCDC_DATA4),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CCDC_DATA5),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CCDC_DATA6),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(CCDC_DATA7),         (IEN  | PTD | DIS | M0)) \
+     /* RMII */\
+     MUX_VAL(CP(RMII_MDIO_DATA),     (IEN  |  M0)) \
+     MUX_VAL(CP(RMII_MDIO_CLK),      (M0)) \
+     MUX_VAL(CP(RMII_RXD0)   ,       (IEN  | PTD | M0)) \
+     MUX_VAL(CP(RMII_RXD1),          (IEN  | PTD | M0)) \
+     MUX_VAL(CP(RMII_CRS_DV),        (IEN  | PTD | M0)) \
+     MUX_VAL(CP(RMII_RXER),          (PTD | M0)) \
+     MUX_VAL(CP(RMII_TXD0),          (PTD | M0)) \
+     MUX_VAL(CP(RMII_TXD1),          (PTD | M0)) \
+     MUX_VAL(CP(RMII_TXEN),          (PTD | M0)) \
+     MUX_VAL(CP(RMII_50MHZ_CLK),     (IEN  | PTD | EN  | M0)) \
+     /* HECC */\
+     MUX_VAL(CP(HECC1_TXD),          (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(HECC1_RXD),          (IEN  | PTU | EN  | M0)) \
+     /* HSUSB */\
+     MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(USB0_DRVBUS),        (IEN  | PTD | EN  | M0)) \
+     /* HDQ */\
+     MUX_VAL(CP(HDQ_SIO),            (IEN  | PTU | EN  | M0)) \
+     /* Control and debug */\
+     MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)) \
+     /*SYS_nRESWARM */\
+     MUX_VAL(CP(SYS_NRESWARM),       (IDIS | PTU | DIS | M4)) \
+                                                     /* - GPIO30 */\
+     MUX_VAL(CP(SYS_BOOT0),          (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+                                                      /* - PEN_IRQ */\
+     MUX_VAL(CP(SYS_BOOT1),          (IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+     MUX_VAL(CP(SYS_BOOT2),          (IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+     MUX_VAL(CP(SYS_BOOT3),          (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+     MUX_VAL(CP(SYS_BOOT4),          (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+     MUX_VAL(CP(SYS_BOOT5),          (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+     MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+                                                      /* - VIO_1V8*/\
+     MUX_VAL(CP(SYS_BOOT7),          (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(SYS_BOOT8),          (IEN  | PTD | EN  | M0)) \
+     \
+     MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(SYS_CLKOUT2),        (IEN  | PTU | EN  | M0)) \
+     /* JTAG */\
+     MUX_VAL(CP(JTAG_nTRST),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(JTAG_TCK),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(JTAG_TMS),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(JTAG_TDI),           (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(JTAG_EMU0),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(JTAG_EMU1),          (IEN  | PTD | DIS | M0)) \
+     /* ETK (ES2 onwards) */\
+     MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTU | EN  | M0)) \
+     MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D0_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D1_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D2_ES2),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(ETK_D3_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D4_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D5_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D6_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D7_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D10_ES2),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D11_ES2),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D13_ES2),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D14_ES2),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(ETK_D15_ES2),        (IEN  | PTD | DIS | M0)) \
+     /* Die to Die */\
+     MUX_VAL(CP(D2D_MCAD34),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(D2D_MCAD35),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(D2D_MCAD36),         (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(D2D_CLK26MI),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_NRESPWRON),      (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(D2D_NRESWARM),       (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(D2D_ARM9NIRQ),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_UMA2P6FIQ),      (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_SPINT),          (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(D2D_FRINT),          (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(D2D_DMAREQ0),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_DMAREQ1),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_DMAREQ2),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_DMAREQ3),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_N3GTRST),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_N3GTDI),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_N3GTDO),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_N3GTMS),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_N3GTCK),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_N3GRTCK),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_MSTDBY),         (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(D2D_SWAKEUP),        (IEN  | PTD | EN  | M0)) \
+     MUX_VAL(CP(D2D_IDLEREQ),        (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_IDLEACK),        (IEN  | PTU | EN  | M0)) \
+     MUX_VAL(CP(D2D_MWRITE),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_SWRITE),         (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_MREAD),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_SREAD),          (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_MBUSFLAG),       (IEN  | PTD | DIS | M0)) \
+     MUX_VAL(CP(D2D_SBUSFLAG),       (IEN  | PTD | DIS | M0)) \
+
+#endif

new file mode 100644
index 0000000..f7a35ce
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <[email protected]>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000

new file mode 100644
index 0000000..63f853a
@@ -0,0 +1,296 @@
+/*
+ * am3517_evm.h - Default configuration for AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <[email protected]>
+ *
+ * Based on omap3_evm_config.h
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8   1       /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP          1       /* in a TI OMAP core */
+#define CONFIG_OMAP34XX              1       /* which is a 34XX */
+#define CONFIG_OMAP3_AM3517EVM       1       /* working with AM3517EVM */
+
+#define CONFIG_EMIF4         1       /* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>            /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO               1
+#define CONFIG_DISPLAY_BOARDINFO     1
+
+/* Clock Defines */
+#define V_OSCK                       26000000        /* Clock output from T2 */
+#define V_SCLK                       (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ                                /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG           1       /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS     1
+#define CONFIG_INITRD_TAG            1
+#define CONFIG_REVISION_TAG          1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE                      (128 << 10)     /* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN                (CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE     128     /* bytes reserved for */
+                                             /* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR              1       /* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE          (256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK                        48000000        /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE  (-4)
+#define CONFIG_SYS_NS16550_CLK               V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX            3
+#define CONFIG_SYS_NS16550_COM3              OMAP34XX_UART3
+#define CONFIG_SERIAL3                       3       /* UART3 on AM3517 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE                      115200
+#define CONFIG_SYS_BAUDRATE_TABLE    {4800, 9600, 19200, 38400, 57600,\
+                                     115200}
+#define CONFIG_MMC                   1
+#define CONFIG_OMAP3_MMC             1
+#define CONFIG_DOS_PARTITION         1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2              /* EXT2 Support                 */
+#define CONFIG_CMD_FAT               /* FAT support                  */
+#define CONFIG_CMD_JFFS2     /* JFFS2 Support                */
+
+#define CONFIG_CMD_I2C               /* I2C serial bus support       */
+#define CONFIG_CMD_MMC               /* MMC support                  */
+#define CONFIG_CMD_NAND              /* NAND support                 */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH              /* flinfo, erase, protect       */
+#undef CONFIG_CMD_FPGA               /* FPGA configuration Support   */
+#undef CONFIG_CMD_IMI                /* iminfo                       */
+#undef CONFIG_CMD_IMLS               /* List all found images        */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C                      1
+#define CONFIG_SYS_I2C_SPEED         100000
+#define CONFIG_SYS_I2C_SLAVE         1
+#define CONFIG_SYS_I2C_BUS           0
+#define CONFIG_SYS_I2C_BUS_SELECT    1
+#define CONFIG_DRIVER_OMAP34XX_I2C   1
+
+#undef CONFIG_CMD_NET
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR         NAND_BASE       /* physical address */
+                                                     /* to access nand */
+#define CONFIG_SYS_NAND_BASE         NAND_BASE       /* physical address */
+                                                     /* to access */
+                                                     /* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE   1               /* Max number of */
+                                                     /* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF            /* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV             "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET     0x680000
+#define CONFIG_JFFS2_PART_SIZE               0xf980000       /* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY     10
+
+#define CONFIG_BOOTFILE              uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+     "loadaddr=0x82000000\0" \
+     "console=ttyS2,115200n8\0" \
+     "mmcargs=setenv bootargs console=${console} " \
+             "root=/dev/mmcblk0p2 rw " \
+             "rootfstype=ext3 rootwait\0" \
+     "nandargs=setenv bootargs console=${console} " \
+             "root=/dev/mtdblock4 rw " \
+             "rootfstype=jffs2\0" \
+     "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+     "bootscript=echo Running bootscript from mmc ...; " \
+             "source ${loadaddr}\0" \
+     "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+     "mmcboot=echo Booting from mmc ...; " \
+             "run mmcargs; " \
+             "bootm ${loadaddr}\0" \
+     "nandboot=echo Booting from nand ...; " \
+             "run nandargs; " \
+             "nand read ${loadaddr} 280000 400000; " \
+             "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+     "if mmc init; then " \
+             "if run loadbootscript; then " \
+                     "run bootscript; " \
+             "else " \
+                     "if run loaduimage; then " \
+                             "run mmcboot; " \
+                     "else run nandboot; " \
+                     "fi; " \
+             "fi; " \
+     "else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT                     "AM3517_EVM # "
+
+#define CONFIG_SYS_LONGHELP          /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER               /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2   "> "
+#define CONFIG_SYS_PROMPT            V_PROMPT
+#define CONFIG_SYS_CBSIZE            512     /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE            (CONFIG_SYS_CBSIZE + \
+                                     sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS           32      /* max number of command */
+                                             /* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE          (CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START     (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END               (OMAP34XX_SDRC_CS0 + \
+                                     0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR         (OMAP34XX_SDRC_CS0) /* default load */
+                                                             /* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE         OMAP34XX_GPT2
+#define CONFIG_SYS_PTV                       2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ                        1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE     (128 << 10)     /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10)       /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10)       /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2       /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1         OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE    (32 << 20)      /*@least 32 MiB */
+#define PHYS_SDRAM_2         OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C           1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE             GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE             GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT    520     /* max number of sectors */
+                                             /* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS   2       /* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN               (256 << 10)     /* Reserve 2 sectors

+
+#define CONFIG_SYS_FLASH_BASE                boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE              CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT  1
+#define CONFIG_ENV_IS_IN_NAND                1
+#define SMNAND_ENV_OFFSET            0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE     boot_flash_sec
+#define CONFIG_ENV_OFFSET            boot_flash_off
+#define CONFIG_ENV_ADDR                      boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT  (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT  (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS     (CONFIG_SYS_MAX_FLASH_BANKS + \
+                                     CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK  CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS   1
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
--

index 5cbc845..0bc65e1 100644
@@ -798,6 +798,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 
+Vaibhav Hiremath <[email protected]>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+

index 0c01c73..ffeb982 100644

+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6

@@ -0,0 +1,76 @@

+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Genius doesn't work on an assembly line basis.  You can't simply say,
"Today I will be brilliant."
	-- Kirk, "The Ultimate Computer", stardate 4731.3
index 5cbc845..0bc65e1 100644
@@ -798,6 +798,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 

+Vaibhav Hiremath <[email protected]>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+

+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6

@@ -0,0 +1,76 @@

+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;

index 5cbc845..0bc65e1 100644
@@ -798,6 +798,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 

+Vaibhav Hiremath <[email protected]>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+

+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6

@@ -0,0 +1,76 @@

+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;

index 5cbc845..0bc65e1 100644
@@ -798,6 +798,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 
+Vaibhav Hiremath <[email protected]>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+

+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When you die, the first thing you lose is your life. The  next  thing
is the illusions.                       - Terry Pratchett, _Pyramids_
index 5cbc845..0bc65e1 100644
@@ -798,6 +798,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 
+Vaibhav Hiremath <[email protected]>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+

+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6

---
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    1 +
 arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/cpu.h       |   24 ++++
 arch/arm/include/asm/arch-omap3/emif4.h     |   79 +++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 include/configs/am3517_evm.h                |    2 +-
 6 files changed, 274 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h
index 1e80eb3..d25bfd5 100644
@@ -38,6 +38,7 @@ COBJS	+= sys_info.o
 COBJS	+= timer.o
 
 COBJS-$(CONFIG_SDRC)	+= sdrc.o
+COBJS-$(CONFIG_EMIF4)	+=emif4.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))

index ce16da7..c072c27 100644
@@ -216,6 +216,30 @@ struct sdrc {
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
 
+/* EMIF4 */
+typedef struct emif4 {
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 

index 4608f30..db7b42a 100644
@@ -33,6 +33,7 @@ void per_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);

index 63f853a..0106031 100644
@@ -33,7 +33,7 @@
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
 
-#define CONFIG_EMIF4		1	/* The chip has EMIF4 controller */
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>

index 1e80eb3..d25bfd5 100644
@@ -38,6 +38,7 @@ COBJS	+= sys_info.o
 COBJS	+= timer.o
 
 COBJS-$(CONFIG_SDRC)	+= sdrc.o
+COBJS-$(CONFIG_EMIF4)	+=emif4.o

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The complexity of software is an essential property, not an  acciden-
tal  one. Hence, descriptions of a software entity that abstract away
its complexity often abstract away its essence.    - Fred Brooks, Jr.
@@ -38,6 +38,7 @@ COBJS	+= sys_info.o
 COBJS	+= timer.o
 

 COBJS-$(CONFIG_SDRC)	+= sdrc.o
+COBJS-$(CONFIG_EMIF4)	+=emif4.o

 include/configs/omap3_evm.h |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)
index 0d99f7d..88af492 100644
@@ -151,7 +151,7 @@
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 

@@ -306,7 +306,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 

 include/configs/omap3_evm.h |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)
index 0d99f7d..88af492 100644
@@ -151,7 +151,7 @@
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 

@@ -306,7 +306,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
--

 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    4 +-
 arch/arm/cpu/arm_cortexa8/omap3/board.c     |   35 +-----
 arch/arm/cpu/arm_cortexa8/omap3/mem.c       |   90 ------------
 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c      |  202 +++++++++++++++++++++++++++
 arch/arm/cpu/arm_cortexa8/omap3/sys_info.c  |   41 ------
 arch/arm/include/asm/arch-omap3/cpu.h       |    1 +
 arch/arm/include/asm/arch-omap3/mem.h       |   13 ++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    2 -
 include/configs/devkit8000.h                |    2 +
 include/configs/omap3_beagle.h              |    2 +
 include/configs/omap3_evm.h                 |    2 +
 include/configs/omap3_overo.h               |    2 +
 include/configs/omap3_pandora.h             |    2 +
 include/configs/omap3_sdp3430.h             |    2 +
 include/configs/omap3_zoom1.h               |    2 +
 include/configs/omap3_zoom2.h               |    2 +
 16 files changed, 236 insertions(+), 168 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
index 136b163..1e80eb3 100644
@@ -37,8 +37,10 @@ COBJS	+= syslib.o
 COBJS	+= sys_info.o
 COBJS	+= timer.o
 
+COBJS-$(CONFIG_SDRC)	+= sdrc.o
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
 
 all:	 $(obj).depend $(LIB)
 

index 69a08fd..d2500ca 100644
@@ -40,8 +40,6 @@
 
 extern omap3_sysinfo sysinfo;
 
-extern u32 is_mem_sdr(void);
-
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works

@@ -233,7 +231,7 @@ void s_init(void)
 	per_clocks_enable();
 
 	if (!in_sdram)
-		sdrc_init();
+		mem_init();
 }
 
 /******************************************************************************

@@ -274,37 +272,6 @@ void watchdog_init(void)
 }
 
 /******************************************************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- *****************************************************************************/
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-
-		size1 = get_sdr_cs_size(CS1);
-	}
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-
-/******************************************************************************
  * Dummy function to handle errors for EABI incompatibility
  *****************************************************************************/
 void abort(void)

index aa8de32..ce16da7 100644
@@ -215,6 +215,7 @@ struct sdrc {
 	u8 res4[0xC];
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 

index 9439758..a78cf9f 100644
@@ -270,4 +270,17 @@ enum {
 #define PISMO1_ONEN_BASE	ONENAND_MAP
 #define DBG_MPDB_BASE		DEBUG_BASE
 
+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif	/* __ASSEMBLY__ */
+
 #endif /* endif _MEM_H_ */

index 34bd515..4608f30 100644
@@ -46,8 +46,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);

index 7d1332f..1076de6 100644
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_DEVKIT8000	1	/* working with DevKit8000 */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 08d79ac..e018b21 100644
@@ -37,6 +37,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 88af492..af7c65a 100644
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_EVM	1	/* working with EVM */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index a43500b..b441831 100644
@@ -29,6 +29,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_OVERO	1	/* working with overo */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 945c053..9eba003 100644
@@ -32,6 +32,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index b4919db..d4482d3 100644
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index ae7ebf9..1e88dc0 100644
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index c88c732..be9daf4 100644
@@ -39,6 +39,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 

 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    4 +-
 arch/arm/cpu/arm_cortexa8/omap3/board.c     |   35 +-----
 arch/arm/cpu/arm_cortexa8/omap3/mem.c       |   90 ------------
 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c      |  202
+++++++++++++++++++++++++++
 arch/arm/cpu/arm_cortexa8/omap3/sys_info.c  |   41 ------
 arch/arm/include/asm/arch-omap3/cpu.h       |    1 +
 arch/arm/include/asm/arch-omap3/mem.h       |   13 ++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    2 -
 include/configs/devkit8000.h                |    2 +
 include/configs/omap3_beagle.h              |    2 +
 include/configs/omap3_evm.h                 |    2 +
 include/configs/omap3_overo.h               |    2 +
 include/configs/omap3_pandora.h             |    2 +
 include/configs/omap3_sdp3430.h             |    2 +
 include/configs/omap3_zoom1.h               |    2 +
 include/configs/omap3_zoom2.h               |    2 +
 16 files changed, 236 insertions(+), 168 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
index 136b163..1e80eb3 100644
@@ -37,8 +37,10 @@ COBJS      += syslib.o
 COBJS        += sys_info.o
 COBJS        += timer.o
 
+COBJS-$(CONFIG_SDRC) += sdrc.o
+
 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
 
 all:  $(obj).depend $(LIB)
 

index 69a08fd..d2500ca 100644
@@ -40,8 +40,6 @@
 
 extern omap3_sysinfo sysinfo;
 
-extern u32 is_mem_sdr(void);
-
 
 /***************************************************************************
 ***

@@ -233,7 +231,7 @@ void s_init(void)
      per_clocks_enable();
 
      if (!in_sdram)
-             sdrc_init();
+             mem_init();
 }
 
 

@@ -274,37 +272,6 @@ void watchdog_init(void)
 }
 
 
 /***************************************************************************
 ***
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
-
 ****************************************************************************

-int dram_init(void)
-{
-     DECLARE_GLOBAL_DATA_PTR;
-     unsigned int size0 = 0, size1 = 0;
-
-     size0 = get_sdr_cs_size(CS0);
-
-     /*
-      * If a second bank of DDR is attached to CS1 this is
-      * where it can be started.  Early init code will init
-      * memory on CS0.
-      */
-     if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-             do_sdrc_init(CS1, NOT_EARLY);
-             make_cs1_contiguous();
-
-             size1 = get_sdr_cs_size(CS1);
-     }
-
-     gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-     gd->bd->bi_dram[0].size = size0;
-     gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-     gd->bd->bi_dram[1].size = size1;
-
-     return 0;
-}
-
-

index dfb7e4c..bd914b0 100644
@@ -79,26 +79,6 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {
 
 #endif
 
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- *  command line mem=xyz use all memory with out discontinuous support
- *  compiled in.  Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
-
 **************************************************************************/
-void make_cs1_contiguous(void)
-{
-     u32 size, a_add_low, a_add_high;
-
-     size = get_sdr_cs_size(CS0);
-     size >>= 25;    /* divide by 32 MiB to find size to offset CS1 */
-     a_add_high = (size & 3) << 8;   /* set up low field */
-     a_add_low = (size & 0x3C) >> 2; /* set up high field */
-     writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
 /********************************************************
  *  mem_ok() - test used to see if timings are correct

@@ -123,76 +103,6 @@ u32 mem_ok(u32 cs)
              return 1;
 }
 
-/********************************************************
- *  sdrc_init() - init the sdrc chip selects CS0 and CS1
- *  - early init routines, called from flash or
- *  SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
-     /* only init up first bank here */
-     do_sdrc_init(CS0, EARLY_INIT);
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- *  -code sets up SDRAM basic SDRC timings for CS0
- *  -optimal settings can be placed here, or redone after i2c
- *      inspection of board info
- *
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *      time depending on memory configuration from stack+global context
-
 **************************************************************************/
-
-void do_sdrc_init(u32 cs, u32 early)
-{
-     struct sdrc_actim *sdrc_actim_base;
-
-     if(cs)
-             sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-     else
-             sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
-     if (early) {
-             /* reset sdrc controller */
-             writel(SOFTRESET, &sdrc_base->sysconfig);
-             wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
-                           12000000);
-             writel(0, &sdrc_base->sysconfig);
-
-             /* setup sdrc to ball mux */
-             writel(SDRC_SHARING, &sdrc_base->sharing);
-
-             /* Disable Power Down of CKE cuz of 1 CKE on combo part */
-             writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
-                             &sdrc_base->power);
-
-             writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
-             sdelay(0x20000);
-     }
-
-     writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
-             RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
-             DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
-     writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
-     writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
-     writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
-
-     writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
-     writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-     writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-     writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
-     /*
-      * CAS latency 3, Write Burst = Read Burst, Serial Mode,
-      * Burst length = 4
-      */
-     writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
-
-     if (!mem_ok(cs))
-             writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32
 base,

                      u32 size)
new file mode 100644
index 0000000..96fd990
@@ -0,0 +1,202 @@
+/*
+ * Functions related to OMAP3 SDRC.
+ *
+ * This file has been created after exctracting and consolidating
+ * the SDRC related content from mem.c and board.c, also created
+ * generic init function (mem_init).
+ *
+ * Copyright (C) 2004-2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ *     Vaibhav Hiremath <[email protected]>
+ *
+ * Original implementation by (mem.c, board.c) :
+ *      Sunil Kumar <[email protected]>
+ *      Shashi Ranjan <[email protected]>
+ *      Manikandan Pillai <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+
+extern omap3_sysinfo sysinfo;
+
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ *  - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+     if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
+             return 1;
+     return 0;
+}
+
+/*
+ * make_cs1_contiguous -
+ *  - For es2 and above remap cs1 behind cs0 to allow command line
+ *    mem=xyz use all memory with out discontinuous support compiled in.
+ *    Could do it at the ATAG, but there really is two banks...
+ *  - Called as part of 2nd phase DDR init.
+ */
+void make_cs1_contiguous(void)
+{
+     u32 size, a_add_low, a_add_high;
+
+     size = get_sdr_cs_size(CS0);
+     size >>= 25;    /* divide by 32 MiB to find size to offset CS1 */
+     a_add_high = (size & 3) << 8;   /* set up low field */
+     a_add_low = (size & 0x3C) >> 2; /* set up high field */
+     writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
+
+}
+
+
+/*
+ * get_sdr_cs_size -
+ *  - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+     u32 size;
+
+     /* get ram size field */
+     size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+     size &= 0x3FF;          /* remove unwanted bits */
+     size <<= 21;            /* multiply by 2 MiB to find size in MB */
+     return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ *  - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+     u32 offset;
+
+     if (!cs)
+             return 0;
+
+     offset = readl(&sdrc_base->cs_cfg);
+     offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+     return offset;
+}
+
+/*
+ * do_sdrc_init -
+ *  - Initialize the SDRAM for use.
+ *  - Sets up SDRC timings for CS0
+ *  - code called once in C-Stack only context for CS0 and a possible 2nd
+ *    time depending on memory configuration from stack+global context
+ */
+void do_sdrc_init(u32 cs, u32 early)
+{
+     struct sdrc_actim *sdrc_actim_base;
+
+     if (cs)
+             sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+     else
+             sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+     if (early) {
+             /* reset sdrc controller */
+             writel(SOFTRESET, &sdrc_base->sysconfig);
+             wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
+                             12000000);
+             writel(0, &sdrc_base->sysconfig);
+
+             /* setup sdrc to ball mux */
+             writel(SDRC_SHARING, &sdrc_base->sharing);
+
+             /* Disable Power Down of CKE cuz of 1 CKE on combo part */
+             writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
+                             &sdrc_base->power);
+
+             writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
+             sdelay(0x20000);
+     }
+
+     writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
+                     RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
+                     DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
+     writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
+     writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
+     writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
+
+     writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+     writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+     writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+     writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+     /*
+      * CAS latency 3, Write Burst = Read Burst, Serial Mode,
+      * Burst length = 4
+      */
+     writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+
+     if (!mem_ok(cs))
+             writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/*
+ * dram_init -
+ *  - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+     DECLARE_GLOBAL_DATA_PTR;
+     unsigned int size0 = 0, size1 = 0;
+
+     size0 = get_sdr_cs_size(CS0);
+     /*
+      * If a second bank of DDR is attached to CS1 this is
+      * where it can be started.  Early init code will init
+      * memory on CS0.
+      */
+     if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+             do_sdrc_init(CS1, NOT_EARLY);
+             make_cs1_contiguous();
+
+             size1 = get_sdr_cs_size(CS1);
+     }
+
+     gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+     gd->bd->bi_dram[0].size = size0;
+     gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+     gd->bd->bi_dram[1].size = size1;
+
+     return 0;
+}
+
+/*
+ * mem_init -
+ *  - Init the sdrc chip,
+ *  - Selects CS0 and CS1,
+ */
+void mem_init(void)
+{
+     /* only init up first bank here */
+     do_sdrc_init(CS0, EARLY_INIT);
+}

index 08fb32e..1df4401 100644
@@ -32,7 +32,6 @@
 #include <i2c.h>
 
 extern omap3_sysinfo sysinfo;
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 static char *rev_s[CPU_3XX_MAX_REV] = {
                              "1.0",

@@ -104,46 +103,6 @@ u32 get_cpu_rev(void)
      }
 }
 
-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
-     if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
-             return 1;
-     return 0;
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 cs)
-{
-     u32 size;
-
-     /* get ram size field */
-     size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
-     size &= 0x3FF;          /* remove unwanted bits */
-     size <<= 21;            /* multiply by 2 MiB to find size in MB */
-     return size;
-}
-
-/***********************************************************************
- * get_sdr_cs_offset() - get offset of cs from cs0 start
- ************************************************************************/
-u32 get_sdr_cs_offset(u32 cs)
-{
-     u32 offset;
-
-     if (!cs)
-             return 0;
-
-     offset = readl(&sdrc_base->cs_cfg);
-     offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
-
-     return offset;
-}
-
 
 /***************************************************************************
  *  get_gpmc0_base() - Return current address hardware will be

index aa8de32..ce16da7 100644
@@ -215,6 +215,7 @@ struct sdrc {
      u8 res4[0xC];
      struct sdrc_cs cs[2];   /* 0x80 || 0xB0 */
 };
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 

index 9439758..a78cf9f 100644
@@ -270,4 +270,17 @@ enum {
 #define PISMO1_ONEN_BASE     ONENAND_MAP
 #define DBG_MPDB_BASE                DEBUG_BASE
 
+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif       /* __ASSEMBLY__ */
+
 #endif /* endif _MEM_H_ */

index 34bd515..4608f30 100644
@@ -46,8 +46,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);

index 7d1332f..1076de6 100644
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430              1       /* which is in a 3430 */
 #define CONFIG_OMAP3_DEVKIT8000      1       /* working with DevKit8000 */
 
+#define CONFIG_SDRC  /* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>            /* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 08d79ac..e018b21 100644
@@ -37,6 +37,8 @@
 #define CONFIG_OMAP3430              1       /* which is in a 3430 */
 #define CONFIG_OMAP3_BEAGLE  1       /* working with BEAGLE */
 
+#define CONFIG_SDRC  /* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>            /* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 88af492..af7c65a 100644
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430              1       /* which is in a 3430 */
 #define CONFIG_OMAP3_EVM     1       /* working with EVM */
 
+#define CONFIG_SDRC  /* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>    /* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index a43500b..b441831 100644
@@ -29,6 +29,8 @@
 #define CONFIG_OMAP3430              1       /* which is in a 3430 */
 #define CONFIG_OMAP3_OVERO   1       /* working with overo */
 
+#define CONFIG_SDRC  /* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>    /* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index 945c053..9eba003 100644
@@ -32,6 +32,8 @@
 #define CONFIG_OMAP3430              1       /* which is in a 3430 */
 #define CONFIG_OMAP3_PANDORA 1       /* working with pandora */
 
+#define CONFIG_SDRC  /* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>    /* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index b4919db..d4482d3 100644
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430              1       /* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP 1       /* working with SDP Rev2 */
 
+#define CONFIG_SDRC  /* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>            /* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index ae7ebf9..1e88dc0 100644
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430              1       /* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM1   1       /* working with Zoom MDK Rev1 */
 
+#define CONFIG_SDRC  /* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>            /* get chip and board defs */
 #include <asm/arch/omap3.h>
 

index c88c732..be9daf4 100644
@@ -39,6 +39,8 @@
 #define CONFIG_OMAP3430              1       /* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM2   1       /* working with Zoom II */
 
+#define CONFIG_SDRC  /* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>    /* get chip and board defs */
 #include <asm/arch/omap3.h>
 
--

 MAINTAINERS                         |    4 +
 MAKEALL                             |    1 +
 Makefile                            |    3 +
 board/logicpd/am3517evm/Makefile    |   46 ++++
 board/logicpd/am3517evm/am3517evm.c |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h |  445 +++++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk   |   30 +++
 include/configs/am3517_evm.h        |  296 +++++++++++++++++++++++
 8 files changed, 901 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
index 7a13d28..3f9df78 100644
@@ -600,6 +600,10 @@ Kshitij Gupta <[email protected]>
 	omap1510inn	ARM925T
 	omap1610inn	ARM926EJS
 
+Vaibhav Hiremath <[email protected]>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+
 Grazvydas Ignotas <[email protected]>
 
 	omap3_pandora	ARM CORTEX-A8 (OMAP3xx SoC)

index 2527352..2066587 100755
@@ -641,6 +641,7 @@ LIST_ARM11="			\
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="		\
+	am3517_evm		\
 	devkit8000		\
 	mx51evk			\
 	omap3_beagle		\

index c26e491..b935c1a 100644
@@ -3155,6 +3155,9 @@ SMN42_config	:	unconfig
 ## ARM CORTEX Systems
 #########################################################################
 
+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 devkit8000_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
 

new file mode 100644
index 0000000..f7a35ce
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <[email protected]>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000

 MAINTAINERS                         |    4 +
 MAKEALL                             |    1 +
 Makefile                            |    3 +
 board/logicpd/am3517evm/Makefile    |   46 ++++
 board/logicpd/am3517evm/am3517evm.c |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h |  445
+++++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk   |   30 +++
 include/configs/am3517_evm.h        |  296 +++++++++++++++++++++++
 8 files changed, 901 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h
---
 board/logicpd/am3517evm/config.mk |    2 +-
 include/configs/am3517_evm.h      |    6 ++++++
 2 files changed, 7 insertions(+), 1 deletions(-)
index 102d32b..71ec5d0 100644
@@ -27,4 +27,4 @@
 # (mem base + reserved)
 
 # For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000

index 9a9ba88..3dda1e9 100644
@@ -330,4 +330,10 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #endif /* __CONFIG_H */

1.6.2.4
---
 board/logicpd/am3517evm/config.mk |    2 +-
 include/configs/am3517_evm.h      |    6 ++++++
 2 files changed, 7 insertions(+), 1 deletions(-)
index 102d32b..71ec5d0 100644
@@ -27,4 +27,4 @@
 # (mem base + reserved)
 
 # For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000

index 9a9ba88..3dda1e9 100644
@@ -330,4 +330,10 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #endif /* __CONFIG_H */
--

---
 include/configs/am3517_evm.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
index 3dda1e9..70e8f07 100644
@@ -163,6 +163,7 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 /*
  * Board NAND Info.
  */

1.6.2.4
---
 include/configs/am3517_evm.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
index 3dda1e9..70e8f07 100644
@@ -163,6 +163,7 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 /*
  * Board NAND Info.
  */
--

---
 arch/arm/cpu/armv7/omap3/emif4.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)
index 0870857..2227576 100644
@@ -48,10 +48,11 @@ u32 is_mem_sdr(void)
  */
 u32 get_sdr_cs_size(u32 cs)
 {
-	u32 size;
+	u32 size = 0;
 
 	/* TODO: Calculate the size based on EMIF4 configuration */
-	size = CONFIG_SYS_CS0_SIZE;
+	if (cs == CS0)
+		size = CONFIG_SYS_CS0_SIZE;
 
 	return size;
 }

1.6.2.4
---
 arch/arm/cpu/armv7/omap3/emif4.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)
index 0870857..2227576 100644
@@ -48,10 +48,11 @@ u32 is_mem_sdr(void)
  */
 u32 get_sdr_cs_size(u32 cs)
 {
-	u32 size;
+	u32 size = 0;
 
 	/* TODO: Calculate the size based on EMIF4 configuration */
-	size = CONFIG_SYS_CS0_SIZE;
+	if (cs == CS0)
+		size = CONFIG_SYS_CS0_SIZE;
 
 	return size;
 }
--

---
 include/configs/omap3_beagle.h  |    2 +-
 include/configs/omap3_evm.h     |    2 +-
 include/configs/omap3_overo.h   |    2 +-
 include/configs/omap3_pandora.h |    2 +-
 include/configs/omap3_sdp3430.h |    2 +-
 include/configs/omap3_zoom1.h   |    2 +-
 include/configs/omap3_zoom2.h   |    2 +-
 include/configs/omap4_panda.h   |    2 +-
 include/configs/omap4_sdp4430.h |    2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)
index 9fd80ed..14586eb 100644
@@ -262,7 +262,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP3 beagleboard.org # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 13a4fbf..ed230b6 100644
@@ -238,7 +238,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP3_EVM # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 242b317..8cf67fd 100644
@@ -214,7 +214,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"Overo # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 39c87a8..88f421b 100644
@@ -197,7 +197,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"Pandora # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 55bbcd4..f957354 100644
@@ -270,7 +270,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP34XX SDP # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 9183849..f26b28f 100644
@@ -221,7 +221,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP3 Zoom1 # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 3573edf..f0cfd41 100644
@@ -201,7 +201,7 @@
 
 #define CONFIG_SYS_PROMPT		"OMAP3 Zoom2 # "
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_CBSIZE		512
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS		16

index 1daffb7..df7aab6 100644
@@ -185,7 +185,7 @@
 #define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"Panda # "
-#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_CBSIZE		512
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 68ffa87..4c183d7 100644
@@ -191,7 +191,7 @@
 #define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP4430 SDP # "
-#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_CBSIZE		512
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

1.6.2.4
---
 include/configs/omap3_beagle.h  |    2 +-
 include/configs/omap3_evm.h     |    2 +-
 include/configs/omap3_overo.h   |    2 +-
 include/configs/omap3_pandora.h |    2 +-
 include/configs/omap3_sdp3430.h |    2 +-
 include/configs/omap3_zoom1.h   |    2 +-
 include/configs/omap3_zoom2.h   |    2 +-
 include/configs/omap4_panda.h   |    2 +-
 include/configs/omap4_sdp4430.h |    2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)
index 9fd80ed..14586eb 100644
@@ -262,7 +262,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP3 beagleboard.org # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 13a4fbf..ed230b6 100644
@@ -238,7 +238,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP3_EVM # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 242b317..8cf67fd 100644
@@ -214,7 +214,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"Overo # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 39c87a8..88f421b 100644
@@ -197,7 +197,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"Pandora # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 55bbcd4..f957354 100644
@@ -270,7 +270,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP34XX SDP # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 9183849..f26b28f 100644
@@ -221,7 +221,7 @@
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP3 Zoom1 # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 3573edf..f0cfd41 100644
@@ -201,7 +201,7 @@
 
 #define CONFIG_SYS_PROMPT		"OMAP3 Zoom2 # "
 #define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_CBSIZE		512
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					 sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS		16

index 1daffb7..df7aab6 100644
@@ -185,7 +185,7 @@
 #define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"Panda # "
-#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_CBSIZE		512
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)

index 68ffa87..4c183d7 100644
@@ -191,7 +191,7 @@
 #define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP4430 SDP # "
-#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_CBSIZE		512
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
--

---
 board/ti/evm/evm.c          |    9 +++++++++
 include/configs/omap3_evm.h |   10 ++++++----
 2 files changed, 15 insertions(+), 4 deletions(-)
index aaf3033..916a13e 100644
@@ -33,6 +33,7 @@
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
 #include <i2c.h>
 #include <asm/mach-types.h>
 #include "evm.h"

@@ -192,3 +193,11 @@ int board_eth_init(bd_t *bis)
 #endif
 	return rc;
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+       omap_mmc_init(0);
+       return 0;
+}
+#endif

index 6455b0e..72c00ab 100644
@@ -99,7 +99,8 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 #define CONFIG_MMC			1
-#define CONFIG_OMAP3_MMC		1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_OMAP_HSMMC		1
 #define CONFIG_DOS_PARTITION		1
 
 /* DDR - I use Micron DDR */

@@ -200,6 +201,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"usbtty=cdc_acm\0" \
+	"mmcdev=0\0" \
 	"console=ttyS2,115200n8\0" \
 	"mmcargs=setenv bootargs console=${console} " \
 		"root=/dev/mmcblk0p2 rw " \

@@ -207,10 +209,10 @@
 	"nandargs=setenv bootargs console=${console} " \
 		"root=/dev/mtdblock4 rw " \
 		"rootfstype=jffs2\0" \
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \

@@ -220,7 +222,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmc init; then " \
+	"if mmc rescan ${mmcdev}; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \

---
 board/logicpd/am3517evm/am3517evm.c |    9 +++++++++
 include/configs/am3517_evm.h        |   12 +++++++-----
 2 files changed, 16 insertions(+), 5 deletions(-)
index bbb6e83..c0a006a 100644
@@ -28,6 +28,7 @@
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
 #include <asm/mach-types.h>
 #include <i2c.h>
 #include "am3517evm.h"

@@ -74,3 +75,11 @@ void set_muxconf_regs(void)
 {
 	MUX_AM3517EVM();
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+       omap_mmc_init(0);
+       return 0;
+}
+#endif

index 70e8f07..caae7fe 100644
@@ -95,7 +95,8 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 #define CONFIG_MMC			1
-#define CONFIG_OMAP3_MMC		1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_OMAP_HSMMC		1
 #define CONFIG_DOS_PARTITION		1
 
 /*

@@ -191,17 +192,18 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
-	"console=ttyS2,115200n8\0" \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
 	"mmcargs=setenv bootargs console=${console} " \
 		"root=/dev/mmcblk0p2 rw " \
 		"rootfstype=ext3 rootwait\0" \
 	"nandargs=setenv bootargs console=${console} " \
 		"root=/dev/mtdblock4 rw " \
 		"rootfstype=jffs2\0" \
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \

@@ -211,7 +213,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmc init; then " \
+	"if mmc rescan ${mmcdev}; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \

      https://patchwork.kernel.org/patch/1056302/
 arch/arm/mach-omap2/Kconfig                    |   10 ++++
 arch/arm/mach-omap2/Makefile                   |    2 +
 arch/arm/mach-omap2/board-am335xevm.c          |   57 ++++++++++++++++++++++++
 arch/arm/mach-omap2/clock3xxx_data.c           |    3 +
 arch/arm/mach-omap2/common.c                   |   16 +++++++
 arch/arm/mach-omap2/id.c                       |    6 +++
 arch/arm/mach-omap2/include/mach/debug-macro.S |   22 +++++++++
 arch/arm/mach-omap2/io.c                       |   25 ++++++++++
 arch/arm/plat-omap/include/plat/am33xx.h       |   25 ++++++++++
 arch/arm/plat-omap/include/plat/clkdev_omap.h  |    1 +
 arch/arm/plat-omap/include/plat/clock.h        |    1 +
 arch/arm/plat-omap/include/plat/common.h       |    1 +
 arch/arm/plat-omap/include/plat/cpu.h          |   23 ++++++++++
 arch/arm/plat-omap/include/plat/hardware.h     |    1 +
 arch/arm/plat-omap/include/plat/io.h           |   20 ++++++++
 arch/arm/plat-omap/include/plat/omap34xx.h     |    2 +
 arch/arm/plat-omap/include/plat/serial.h       |    4 ++
 arch/arm/plat-omap/include/plat/uncompress.h   |    6 +++
 arch/arm/plat-omap/io.c                        |    3 +
 19 files changed, 228 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap2/board-am335xevm.c
 create mode 100644 arch/arm/plat-omap/include/plat/am33xx.h
---
 arch/arm/mach-omap2/Kconfig                   |    5 +++++
 arch/arm/mach-omap2/clock.c                   |    2 +-
 arch/arm/mach-omap2/clock.h                   |    2 +-
 arch/arm/mach-omap2/opp2xxx.h                 |    2 +-
 arch/arm/plat-omap/include/plat/clkdev_omap.h |    1 +
 arch/arm/plat-omap/include/plat/clock.h       |    3 ++-
 arch/arm/plat-omap/include/plat/cpu.h         |   25 +++++++++++++++++++++++++
 7 files changed, 36 insertions(+), 4 deletions(-)
index 57b66d5..12ab835 100644
@@ -78,6 +78,11 @@ config SOC_OMAPTI816X
 	depends on ARCH_OMAP3
 	default y
 
+config SOC_OMAPAM33XX
+	bool "AM33XX support"
+	depends on ARCH_OMAP3
+	default y
+
 config OMAP_PACKAGE_ZAF
        bool
 

index 1f3481f..f57ed5b 100644
@@ -35,7 +35,7 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-u8 cpu_mask;
+u16 cpu_mask;
 
 /*
  * clkdm_control: if true, then when a clock is enabled in the

index 48ac568..687d3d3 100644
@@ -130,7 +130,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 			       const char *core_ck_name,
 			       const char *mpu_ck_name);
 
-extern u8 cpu_mask;
+extern u16 cpu_mask;
 
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_dummy;

index 8affc66..8fae534 100644
@@ -51,7 +51,7 @@ struct prcm_config {
 	unsigned long cm_clksel2_pll;	/* dpllx1 or x2 out */
 	unsigned long cm_clksel_mdm;	/* modem dividers 2430 only */
 	unsigned long base_sdrc_rfr;	/* base refresh timing for a set */
-	unsigned char flags;
+	unsigned short flags;
 };
 
 

index 387a963..6d84c0c 100644
@@ -40,6 +40,7 @@ struct omap_clk {
 #define CK_443X		(1 << 11)
 #define CK_TI816X	(1 << 12)
 #define CK_446X		(1 << 13)
+#define CK_AM33XX	(1 << 14)	/* AM33xx specific clocks */
 
 
 #define CK_34XX		(CK_3430ES1 | CK_3430ES2PLUS)

index 197ca03..168c54e 100644
@@ -59,6 +59,7 @@ struct clkops {
 #define RATE_IN_4430		(1 << 5)
 #define RATE_IN_TI816X		(1 << 6)
 #define RATE_IN_4460		(1 << 7)
+#define RATE_IN_AM33XX		(1 << 8)
 
 #define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)
 #define RATE_IN_34XX		(RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)

@@ -84,7 +85,7 @@ struct clkops {
 struct clksel_rate {
 	u32			val;
 	u8			div;
-	u8			flags;
+	u16			flags;
 };
 
 /**

index 2f90269..9f4d5c3 100644
@@ -78,6 +78,14 @@ static inline int is_omap ##class (void)		\
 	return (GET_OMAP_CLASS == (id)) ? 1 : 0;	\
 }
 
+#define GET_AM_CLASS	((omap_rev() >> 24) & 0xff)
+
+#define IS_AM_CLASS(class, id)			\
+static inline int is_am ##class (void)		\
+{							\
+	return (GET_AM_CLASS == (id)) ? 1 : 0;	\
+}
+
 #define GET_OMAP_SUBCLASS	((omap_rev() >> 20) & 0x0fff)
 
 #define IS_OMAP_SUBCLASS(subclass, id)			\

@@ -92,12 +100,19 @@ static inline int is_ti ##subclass (void)		\
 	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
 }
 
+#define IS_AM_SUBCLASS(subclass, id)			\
+static inline int is_am ##subclass (void)		\
+{							\
+	return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;	\
+}
+
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
 IS_OMAP_CLASS(44xx, 0x44)
+IS_AM_CLASS(33xx, 0x33)
 
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)

@@ -107,6 +122,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 IS_OMAP_SUBCLASS(446x, 0x446)
 
 IS_TI_SUBCLASS(816x, 0x816)
+IS_AM_SUBCLASS(335x, 0x335)
 
 #define cpu_is_omap7xx()		0
 #define cpu_is_omap15xx()		0

@@ -117,6 +133,8 @@ IS_TI_SUBCLASS(816x, 0x816)
 #define cpu_is_omap34xx()		0
 #define cpu_is_omap343x()		0
 #define cpu_is_ti816x()			0
+#define cpu_is_am33xx()			0
+#define cpu_is_am335x()			0
 #define cpu_is_omap44xx()		0
 #define cpu_is_omap443x()		0
 #define cpu_is_omap446x()		0

@@ -323,6 +341,8 @@ IS_OMAP_TYPE(3517, 0x3517)
 # undef cpu_is_omap3505
 # undef cpu_is_omap3517
 # undef cpu_is_ti816x
+# undef cpu_is_am33xx
+# undef cpu_is_am335x
 # define cpu_is_omap3430()		is_omap3430()
 # define cpu_is_omap3503()		(cpu_is_omap3430() &&		\
 						(!omap3_has_iva()) &&	\

@@ -340,6 +360,8 @@ IS_OMAP_TYPE(3517, 0x3517)
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()		is_omap363x()
 # define cpu_is_ti816x()		is_ti816x()
+# define cpu_is_am33xx()		is_am33xx()
+# define cpu_is_am335x()		is_am335x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)

@@ -386,6 +408,9 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define TI8168_REV_ES1_0	TI816X_CLASS
 #define TI8168_REV_ES1_1	(TI816X_CLASS | (0x1 << 8))
 
+#define AM335X_CLASS		0x33500034
+#define AM335X_REV_ES1_0	AM335X_CLASS
+
 #define OMAP443X_CLASS		0x44300044
 #define OMAP4430_REV_ES1_0	(OMAP443X_CLASS | (0x10 << 8))
 #define OMAP4430_REV_ES2_0	(OMAP443X_CLASS | (0x20 << 8))

---
 arch/arm/mach-omap2/clock3xxx_data.c       |    6 +++++-
 arch/arm/mach-omap2/common.c               |   16 ++++++++++++++++
 arch/arm/mach-omap2/id.c                   |   10 ++++++++--
 arch/arm/mach-omap2/io.c                   |   25 +++++++++++++++++++++++++
 arch/arm/mach-omap2/serial.c               |    6 +++---
 arch/arm/plat-omap/include/plat/am33xx.h   |   25 +++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/common.h   |    1 +
 arch/arm/plat-omap/include/plat/hardware.h |    1 +
 arch/arm/plat-omap/include/plat/io.h       |   20 ++++++++++++++++++++
 arch/arm/plat-omap/include/plat/omap34xx.h |    2 ++
 arch/arm/plat-omap/io.c                    |    5 +++++
 11 files changed, 111 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/am33xx.h
index dadb8c6..2ee472c 100644
@@ -3493,6 +3493,9 @@ int __init omap3xxx_clk_init(void)
 	} else if (cpu_is_ti816x()) {
 		cpu_mask = RATE_IN_TI816X;
 		cpu_clkflg = CK_TI816X;
+	} else if (cpu_is_am33xx()) {
+		cpu_mask = RATE_IN_AM33XX;
+		cpu_clkflg = CK_AM33XX;
 	} else if (cpu_is_omap34xx()) {
 		if (omap_rev() == OMAP3430_REV_ES1_0) {
 			cpu_mask = RATE_IN_3430ES1;

@@ -3576,7 +3579,8 @@ int __init omap3xxx_clk_init(void)
 	 * Lock DPLL5 -- here only until other device init code can
 	 * handle this
 	 */
-	if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+	if (!cpu_is_ti816x() && !cpu_is_am33xx() &&
+			(omap_rev() >= OMAP3430_REV_ES2_0))
 		omap3_clk_lock_dpll5();
 
 	/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */

index 3f20cbb..395a9b6 100644
@@ -119,6 +119,22 @@ void __init omap2_set_globals_ti816x(void)
 {
 	__omap2_set_globals(&ti816x_globals);
 }
+
+#define AM33XX_TAP_BASE		(AM33XX_CTRL_BASE + \
+				TI816X_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals am33xx_globals = {
+	.class  = OMAP343X_CLASS,
+	.tap    = OMAP2_L4_IO_ADDRESS(AM33XX_TAP_BASE),
+	.ctrl   = AM33XX_CTRL_BASE,
+	.prm    = AM33XX_PRCM_BASE,
+	.cm     = AM33XX_PRCM_BASE,
+};
+
+void __init omap2_set_globals_am33xx(void)
+{
+	__omap2_set_globals(&am33xx_globals);
+}
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)

index d27daf9..540b6f1 100644
@@ -337,6 +337,10 @@ static void __init omap3_check_revision(const char **cpu_rev)
 			break;
 		}
 		break;
+	case 0xb944:
+		omap_revision = AM335X_REV_ES1_0;
+		*cpu_rev = "1.0";
+		break;
 	default:
 		/* Unknown default to latest silicon rev as default */
 		omap_revision = OMAP3630_REV_ES1_2;

@@ -429,6 +433,8 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
 		cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 	} else if (cpu_is_ti816x()) {
 		cpu_name = "TI816X";
+	} else if (cpu_is_am335x()) {
+		cpu_name =  "AM335X";
 	} else if (omap3_has_iva() && omap3_has_sgx()) {
 		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 		cpu_name = "OMAP3430/3530";

@@ -469,8 +475,8 @@ void __init omap2_check_revision(void)
 	} else if (cpu_is_omap34xx()) {
 		omap3_check_revision(&cpu_rev);
 
-		/* TI816X doesn't have feature register */
-		if (!cpu_is_ti816x())
+		/* TI816X/AM335X doesn't have feature register */
+		if (!cpu_is_ti816x() && !cpu_is_am33xx())
 			omap3_check_features();
 		else
 			ti816x_check_features();

index 40b6d47..ccd50de 100644
@@ -182,7 +182,24 @@ static struct map_desc omapti816x_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
 		.length		= L4_34XX_SIZE,
 		.type		= MT_DEVICE
+	}
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
+	{
+		.virtual	= L4_34XX_VIRT,
+		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
+		.length		= L4_34XX_SIZE,
+		.type		= MT_DEVICE
 	},
+	{
+		.virtual	= L4_WK_AM33XX_VIRT,
+		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
+		.length		= L4_WK_AM33XX_SIZE,
+		.type		= MT_DEVICE
+	}
 };
 #endif
 

@@ -286,6 +303,14 @@ void __init omapti816x_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
+{
+	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
+	_omap2_map_common_io();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap44xx_map_common_io(void)
 {

index 466fc72..b7782ee 100644
@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
 		mod_timer(&uart->timer, jiffies + uart->timeout);
 	omap_uart_smart_idle_enable(uart, 0);
 
-	if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx())) {
 		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 		u32 wk_mask = 0;
 		u32 padconf = 0;

@@ -768,7 +768,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
 	 */
 	uart->regshift = p->regshift;
 	uart->membase = p->membase;
-	if (cpu_is_omap44xx() || cpu_is_ti816x())
+	if (cpu_is_omap44xx() || cpu_is_ti816x() || cpu_is_am33xx())
 		uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 	else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
 			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)

@@ -851,7 +851,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
 	}
 
 	/* Enable the MDR1 errata for OMAP3 */
-	if (cpu_is_omap34xx() && !cpu_is_ti816x())
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx()))
 		uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 

new file mode 100644
index 0000000..06c19bb
@@ -0,0 +1,25 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+#define L4_SLOW_AM33XX_BASE	0x48000000
+
+#define AM33XX_SCM_BASE		0x44E10000
+#define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
+#define AM33XX_PRCM_BASE	0x44E00000
+
+#endif /* __ASM_ARCH_AM33XX_H */

index 4564cc6..6827e34 100644
@@ -67,6 +67,7 @@ void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
 void omap2_set_globals_ti816x(void);
+void omap2_set_globals_am33xx(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);

index e87efe1..e6521e1 100644
@@ -287,5 +287,6 @@
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
 #include <plat/ti816x.h>
+#include <plat/am33xx.h>
 
 #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */

index d72ec85..0c54a00 100644
@@ -73,6 +73,9 @@
 #define OMAP4_L3_IO_OFFSET	0xb4000000
 #define OMAP4_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
 
+#define AM33XX_L4_WK_IO_OFFSET	0xb5000000
+#define AM33XX_L4_WK_IO_ADDRESS(pa)	IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
+
 #define OMAP4_L3_PER_IO_OFFSET	0xb1100000
 #define OMAP4_L3_PER_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
 

@@ -154,6 +157,15 @@
 #define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 
 /*
+ * ----------------------------------------------------------------------------
+ * AM33XX specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L4_WK_AM33XX_PHYS		L4_WK_AM33XX_BASE
+#define L4_WK_AM33XX_VIRT		(L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
+#define L4_WK_AM33XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+
+/*
  * Need to look at the Size 4M for L4.
  * VPOM3430 was not working for Int controller
  */

@@ -291,6 +303,14 @@ static inline void omapti816x_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
+{
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 extern void omap44xx_map_common_io(void);
 #else

index b9e8588..0d818ac 100644
@@ -35,6 +35,8 @@
 #define L4_EMU_34XX_BASE	0x54000000
 #define L3_34XX_BASE		0x68000000
 
+#define L4_WK_AM33XX_BASE	0x44C00000
+
 #define OMAP3430_32KSYNCT_BASE	0x48320000
 #define OMAP3430_CM_BASE	0x48004800
 #define OMAP3430_PRM_BASE	0x48306800

index f1ecfa9..25a32b2 100644
@@ -88,6 +88,11 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
 	if (cpu_is_ti816x()) {
 		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
 			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+	} else if (cpu_is_am33xx()) {
+		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+		if (BETWEEN(p, L4_WK_AM33XX_PHYS, L4_WK_AM33XX_SIZE))
+			return XLATE(p, L4_WK_AM33XX_PHYS, L4_WK_AM33XX_VIRT);
 	} else if (cpu_is_omap34xx()) {
 		if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
 			return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);

@@ -3576,7 +3579,8 @@ int __init omap3xxx_clk_init(void)
 	 * Lock DPLL5 -- here only until other device init code can
 	 * handle this
 	 */
-	if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+	if (!cpu_is_ti816x() && !cpu_is_am33xx() &&
+			(omap_rev() >= OMAP3430_REV_ES2_0))
 		omap3_clk_lock_dpll5();

@@ -3576,7 +3579,8 @@ int __init omap3xxx_clk_init(void)
 	 * Lock DPLL5 -- here only until other device init code can
 	 * handle this
 	 */
-	if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+	if (!cpu_is_ti816x() && !cpu_is_am33xx() &&
+			(omap_rev() >= OMAP3430_REV_ES2_0))
 		omap3_clk_lock_dpll5();

@@ -3576,7 +3579,8 @@ int __init omap3xxx_clk_init(void)
 	 * Lock DPLL5 -- here only until other device init code can
 	 * handle this
 	 */
-	if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+	if (!cpu_is_ti816x() && !cpu_is_am33xx() &&
+			(omap_rev() >= OMAP3430_REV_ES2_0))
 		omap3_clk_lock_dpll5();

---
 arch/arm/mach-omap2/clock3xxx_data.c       |    6 +++++-
 arch/arm/mach-omap2/common.c               |   16 ++++++++++++++++
 arch/arm/mach-omap2/id.c                   |   10 ++++++++--
 arch/arm/mach-omap2/io.c                   |   25
+++++++++++++++++++++++++
 arch/arm/mach-omap2/serial.c               |    6 +++---
 arch/arm/plat-omap/include/plat/am33xx.h   |   25
+++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/common.h   |    1 +
 arch/arm/plat-omap/include/plat/hardware.h |    1 +
 arch/arm/plat-omap/include/plat/io.h       |   20 ++++++++++++++++++++
 arch/arm/plat-omap/include/plat/omap34xx.h |    2 ++
 arch/arm/plat-omap/io.c                    |    5 +++++
 11 files changed, 111 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/am33xx.h
@@ -3493,6 +3493,9 @@ int __init omap3xxx_clk_init(void)
 	} else if (cpu_is_ti816x()) {
 		cpu_mask = RATE_IN_TI816X;
 		cpu_clkflg = CK_TI816X;
+	} else if (cpu_is_am33xx()) {
+		cpu_mask = RATE_IN_AM33XX;
+		cpu_clkflg = CK_AM33XX;
 	} else if (cpu_is_omap34xx()) {
 		if (omap_rev() == OMAP3430_REV_ES1_0) {
 			cpu_mask = RATE_IN_3430ES1;

@@ -3576,7 +3579,8 @@ int __init omap3xxx_clk_init(void)
 	 * Lock DPLL5 -- here only until other device init code can
 	 * handle this
 	 */
-	if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+	if (!cpu_is_ti816x() && !cpu_is_am33xx() &&
+			(omap_rev() >= OMAP3430_REV_ES2_0))
 		omap3_clk_lock_dpll5();
 
 	/* Avoid sleeping during omap3_core_dpll_m2_set_rate() */

index 3f20cbb..395a9b6 100644
@@ -119,6 +119,22 @@ void __init omap2_set_globals_ti816x(void)
 {
 	__omap2_set_globals(&ti816x_globals);
 }
+
+#define AM33XX_TAP_BASE		(AM33XX_CTRL_BASE + \
+				TI816X_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals am33xx_globals = {
+	.class  = OMAP343X_CLASS,
+	.tap    = OMAP2_L4_IO_ADDRESS(AM33XX_TAP_BASE),
+	.ctrl   = AM33XX_CTRL_BASE,
+	.prm    = AM33XX_PRCM_BASE,
+	.cm     = AM33XX_PRCM_BASE,
+};
+
+void __init omap2_set_globals_am33xx(void)
+{
+	__omap2_set_globals(&am33xx_globals);
+}
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)

index d27daf9..540b6f1 100644
@@ -337,6 +337,10 @@ static void __init omap3_check_revision(const char
 **cpu_rev)
 			break;
 		}
 		break;
+	case 0xb944:
+		omap_revision = AM335X_REV_ES1_0;
+		*cpu_rev = "1.0";
+		break;
 	default:
 		/* Unknown default to latest silicon rev as default */

 		omap_revision = OMAP3630_REV_ES1_2;

@@ -429,6 +433,8 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
 		cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 	} else if (cpu_is_ti816x()) {
 		cpu_name = "TI816X";
+	} else if (cpu_is_am335x()) {
+		cpu_name =  "AM335X";
 	} else if (omap3_has_iva() && omap3_has_sgx()) {
 		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 		cpu_name = "OMAP3430/3530";

@@ -469,8 +475,8 @@ void __init omap2_check_revision(void)
 	} else if (cpu_is_omap34xx()) {
 		omap3_check_revision(&cpu_rev);
 
-		/* TI816X doesn't have feature register */
-		if (!cpu_is_ti816x())
+		/* TI816X/AM335X doesn't have feature register */
+		if (!cpu_is_ti816x() && !cpu_is_am33xx())
 			omap3_check_features();
 		else
 			ti816x_check_features();

index 40b6d47..ccd50de 100644
@@ -182,7 +182,24 @@ static struct map_desc omapti816x_io_desc[]
 __initdata = {
 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
 		.length		= L4_34XX_SIZE,
 		.type		= MT_DEVICE
+	}
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
+	{
+		.virtual	= L4_34XX_VIRT,
+		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
+		.length		= L4_34XX_SIZE,
+		.type		= MT_DEVICE
 	},
+	{
+		.virtual	= L4_WK_AM33XX_VIRT,
+		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
+		.length		= L4_WK_AM33XX_SIZE,
+		.type		= MT_DEVICE
+	}
 };
 #endif

@@ -286,6 +303,14 @@ void __init omapti816x_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
+{
+	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
+	_omap2_map_common_io();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap44xx_map_common_io(void)
 {

index 466fc72..b7782ee 100644
@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state
 *uart)
 		mod_timer(&uart->timer, jiffies + uart->timeout);
 	omap_uart_smart_idle_enable(uart, 0);
 
-	if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx())) {
 		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 		u32 wk_mask = 0;

 		u32 padconf = 0;

@@ -768,7 +768,7 @@ void __init omap_serial_init_port(struct
 omap_board_data *bdata)
 	 */
 	uart->regshift = p->regshift;
 	uart->membase = p->membase;
-	if (cpu_is_omap44xx() || cpu_is_ti816x())
+	if (cpu_is_omap44xx() || cpu_is_ti816x() || cpu_is_am33xx())
 		uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 	else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)

 			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)

@@ -851,7 +851,7 @@ void __init omap_serial_init_port(struct
 omap_board_data *bdata)
 	}

         * omap3xxx: Never read empty UART fifo on UARTs
         * with IP rev >=0x52
         */
        uart->regshift = p->regshift;
        uart->membase = p->membase;
                uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;

        if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
 	/* Enable the MDR1 errata for OMAP3 */
-	if (cpu_is_omap34xx() && !cpu_is_ti816x())
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx()))
 		uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 

@@ -0,0 +1,25 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+#define L4_SLOW_AM33XX_BASE	0x48000000
+
+#define AM33XX_SCM_BASE		0x44E10000
+#define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
+#define AM33XX_PRCM_BASE	0x44E00000
+
+#endif /* __ASM_ARCH_AM33XX_H */

@@ -67,6 +67,7 @@ void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
 void omap2_set_globals_ti816x(void);
+void omap2_set_globals_am33xx(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);

@@ -287,5 +287,6 @@
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
 #include <plat/ti816x.h>
+#include <plat/am33xx.h>
 
 #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */

@@ -73,6 +73,9 @@
 #define OMAP4_L3_IO_OFFSET	0xb4000000
 #define OMAP4_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3
 */
 
+#define AM33XX_L4_WK_IO_OFFSET	0xb5000000
+#define AM33XX_L4_WK_IO_ADDRESS(pa)	IOMEM((pa) +
 AM33XX_L4_WK_IO_OFFSET)
+
 #define OMAP4_L3_PER_IO_OFFSET	0xb1100000

@@ -154,6 +157,15 @@
 #define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect
 */
 
 /*
+ * ----------------------------------------------------------------------
------
+ * AM33XX specific IO mapping
+ * ----------------------------------------------------------------------
------
+ */
+#define L4_WK_AM33XX_PHYS		L4_WK_AM33XX_BASE
+#define L4_WK_AM33XX_VIRT		(L4_WK_AM33XX_PHYS +

+
+/*
  * Need to look at the Size 4M for L4.
  * VPOM3430 was not working for Int controller
  */

@@ -291,6 +303,14 @@ static inline void omapti816x_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
+{
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 extern void omap44xx_map_common_io(void);
 #else

@@ -35,6 +35,8 @@
 #define L4_EMU_34XX_BASE	0x54000000
 #define L3_34XX_BASE		0x68000000
 
+#define L4_WK_AM33XX_BASE	0x44C00000
+
 #define OMAP3430_32KSYNCT_BASE	0x48320000
 #define OMAP3430_CM_BASE	0x48004800
 #define OMAP3430_PRM_BASE	0x48306800

index f1ecfa9..25a32b2 100644
@@ -88,6 +88,11 @@ void __iomem *omap_ioremap(unsigned long p, size_t size,
 unsigned int type)
 	if (cpu_is_ti816x()) {
 		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
 			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+	} else if (cpu_is_am33xx()) {
+		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+		if (BETWEEN(p, L4_WK_AM33XX_PHYS, L4_WK_AM33XX_SIZE))
+			return XLATE(p, L4_WK_AM33XX_PHYS, L4_WK_AM33XX_VIRT);
 	} else if (cpu_is_omap34xx()) {
 		if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))

---
 arch/arm/mach-omap2/clock3xxx_data.c       |    6 +++++-
 arch/arm/mach-omap2/common.c               |   16 ++++++++++++++++
 arch/arm/mach-omap2/id.c                   |   10 ++++++++--
 arch/arm/mach-omap2/io.c                   |   25
+++++++++++++++++++++++++
 arch/arm/mach-omap2/serial.c               |    6 +++---
 arch/arm/plat-omap/include/plat/am33xx.h   |   25
+++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/common.h   |    1 +
 arch/arm/plat-omap/include/plat/hardware.h |    1 +
 arch/arm/plat-omap/include/plat/io.h       |   20 ++++++++++++++++++++
 arch/arm/plat-omap/include/plat/omap34xx.h |    2 ++
 arch/arm/plat-omap/io.c                    |    5 +++++
 11 files changed, 111 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/am33xx.h
index 466fc72..b7782ee 100644
@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct

 *uart)
 		mod_timer(&uart->timer, jiffies + uart->timeout);
 	omap_uart_smart_idle_enable(uart, 0);
 
-	if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx())) {
 		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 		u32 wk_mask = 0;

 		u32 padconf = 0;

@@ -768,7 +768,7 @@ void __init omap_serial_init_port(struct
 omap_board_data *bdata)
 	 */
 	uart->regshift = p->regshift;
 	uart->membase = p->membase;
-	if (cpu_is_omap44xx() || cpu_is_ti816x())
+	if (cpu_is_omap44xx() || cpu_is_ti816x() || cpu_is_am33xx())
 		uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 	else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)

 			>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)

@@ -851,7 +851,7 @@ void __init omap_serial_init_port(struct
 omap_board_data *bdata)
 	}

-        * omap44xx, ti816x: Never read empty UART fifo
+        * all >omap3 family of devices: Never read empty UART fifo
         * omap3xxx: Never read empty UART fifo on UARTs
         * with IP rev >=0x52
         */
        uart->regshift = p->regshift;
        uart->membase = p->membase;
-       if (cpu_is_omap44xx() || cpu_is_ti816x() || cpu_is_am33xx())
-               uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;

-       else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
-                       >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
+
+       if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
+                       < UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
+               uart->errata &= ~UART_ERRATA_FIFO_FULL_ABORT;
+       else
                uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 
        if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {

                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
---
 arch/arm/mach-omap2/Kconfig           |    5 +++
 arch/arm/mach-omap2/Makefile          |    2 +
 arch/arm/mach-omap2/board-am335xevm.c |   57 +++++++++++++++++++++++++++++++++
 3 files changed, 64 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap2/board-am335xevm.c
index 12ab835..8533008 100644
@@ -315,6 +315,11 @@ config MACH_TI8168EVM
 	depends on SOC_OMAPTI816X
 	default y
 
+config MACH_AM335XEVM
+	bool "AM335X Evaluation Module"
+	depends on SOC_OMAPAM33XX
+	default y
+
 config MACH_OMAP_4430SDP
 	bool "OMAP 4430 SDP board"
 	default y

index 5a6fe73..47d8de1 100644
@@ -259,6 +259,8 @@ obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
 obj-$(CONFIG_MACH_SBC3530)		+= board-omap3stalker.o \
 					   hsmmc.o
 obj-$(CONFIG_MACH_TI8168EVM)		+= board-ti8168evm.o
+obj-$(CONFIG_MACH_AM335XEVM)		+= board-am335xevm.o
+
 # Platform specific device init code
 usbfs-$(CONFIG_ARCH_OMAP_OTG)		:= usb-fs.o
 obj-y					+= $(usbfs-m) $(usbfs-y)

+
+MACHINE_START(AM335XEVM, "am335xevm")
+	/* Maintainer: Texas Instruments */
+	.boot_params	= 0x80000100,
+	.map_io		= am335x_evm_map_io,
+	.init_early	= am335x_init_early,
+	.init_irq	= ti816x_init_irq,
+	.timer		= &omap3_timer,
+	.init_machine	= am335x_evm_init,
+MACHINE_END

---
 arch/arm/mach-omap2/include/mach/debug-macro.S |   22 ++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/serial.h       |    4 ++++
 arch/arm/plat-omap/include/plat/uncompress.h   |    6 ++++++
 3 files changed, 32 insertions(+), 0 deletions(-)
index 48adfe9..f649973 100644
@@ -78,6 +78,8 @@ omap_uart_lsr:	.word	0
 		beq	82f			@ configure UART2
 		cmp	\rp, #TI816XUART3	@ ti816x UART offsets different
 		beq	83f			@ configure UART3
+		cmp	\rp, #AM33XXUART1	@ AM33XX UART offsets different
+		beq	84f			@ configure UART1
 		cmp	\rp, #ZOOM_UART		@ only on zoom2/3
 		beq	95f			@ configure ZOOM_UART
 

@@ -106,6 +108,9 @@ omap_uart_lsr:	.word	0
 		b	98f
 83:		mov	\rp, #UART_OFFSET(TI816X_UART3_BASE)
 		b	98f
+84:		ldr	\rp, =AM33XX_UART1_BASE
+		and	\rp, \rp, #0x00ffffff
+		b	97f
 95:		ldr	\rp, =ZOOM_UART_BASE
 		mrc	p15, 0, \rv, c1, c0
 		tst	\rv, #1			@ MMU enabled?

@@ -121,6 +126,23 @@ omap_uart_lsr:	.word	0
 		b	10b
 
 		/* Store both phys and virt address for the uart */
+97:		add	\rp, \rp, #0x44000000	@ phys base
+		mrc	p15, 0, \rv, c1, c0
+		tst	\rv, #1			@ MMU enabled?
+		ldreq	\rv, =omap_uart_v2p(omap_uart_phys)	@ MMU disabled
+		ldrne	\rv, =omap_uart_phys	@ MMU enabled
+		str	\rp, [\rv, #0]
+		sub	\rp, \rp, #0x44000000	@ phys base
+		add	\rp, \rp, #0xf9000000	@ virt base
+		add	\rv, \rv, #4		@ omap_uart_virt
+		str	\rp, [\rv, #0]
+		mov	\rp, #(UART_LSR << OMAP_PORT_SHIFT)
+		add	\rv, \rv, #4		@ omap_uart_lsr
+		str	\rp, [\rv, #0]
+
+		b	10b
+
+		/* Store both phys and virt address for the uart */
 98:		add	\rp, \rp, #0x48000000	@ phys base
 		mrc	p15, 0, \rv, c1, c0
 		tst	\rv, #1			@ MMU enabled?

index de3b10c..ad19377 100644
@@ -59,6 +59,9 @@
 /* AM3505/3517 UART4 */
 #define AM35XX_UART4_BASE	0x4809E000	/* Only on AM3505/3517 */
 
+/* AM33XX serial port */
+#define AM33XX_UART1_BASE	0x44E09000
+
 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE		0x10000000
 #define ZOOM_UART_VIRT		0xfa400000

@@ -92,6 +95,7 @@
 #define TI816XUART1		81
 #define TI816XUART2		82
 #define TI816XUART3		83
+#define AM33XXUART1		84
 #define ZOOM_UART		95		/* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */

index a067484..bd1e051 100644
@@ -97,6 +97,10 @@ static inline void flush(void)
 	_DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT,	\
 		TI816XUART##p)
 
+#define DEBUG_LL_AM33XX(p, mach)					\
+	_DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,	\
+		AM33XXUART##p)
+
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
 	int port = 0;

@@ -173,6 +177,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 		/* TI8168 base boards using UART3 */
 		DEBUG_LL_TI816X(3, ti8168evm);
 
+		/* AM33XX base boards using UART1 */
+		DEBUG_LL_AM33XX(1, am335xevm);
 	} while (0);
 }
 

	- Rebased against Paul's OMAP_CHIP* cleanup patches
	    git://git.pwsan.com/linux-2.6_omap_chip_remove_cleanup_3.2
 arch/arm/mach-omap2/Kconfig                    |    5 ++++
 arch/arm/mach-omap2/Makefile                   |    1 +
 arch/arm/mach-omap2/board-am3517evm.c          |   21 ++++++++++++++++
 arch/arm/mach-omap2/clock3xxx_data.c           |    3 ++
 arch/arm/mach-omap2/common.c                   |   21 ++++++++++++++++
 arch/arm/mach-omap2/id.c                       |    6 ++++
 arch/arm/mach-omap2/include/mach/debug-macro.S |   17 ++++++++++++-
 arch/arm/mach-omap2/io.c                       |   31 ++++++++++++++++++++++++
 arch/arm/mach-omap2/serial.c                   |    4 +-
 arch/arm/mach-omap2/timer.c                    |    2 +
 arch/arm/plat-omap/include/plat/am33xx.h       |   25 +++++++++++++++++++
 arch/arm/plat-omap/include/plat/common.h       |    4 +++
 arch/arm/plat-omap/include/plat/hardware.h     |    1 +
 arch/arm/plat-omap/include/plat/io.h           |   20 +++++++++++++++
 arch/arm/plat-omap/include/plat/omap34xx.h     |    2 +
 arch/arm/plat-omap/include/plat/serial.h       |    4 +++
 arch/arm/plat-omap/include/plat/uncompress.h   |    6 ++++
 arch/arm/plat-omap/io.c                        |    5 ++++
 18 files changed, 175 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/am33xx.h
---
 arch/arm/mach-omap2/clock3xxx_data.c       |    3 +++
 arch/arm/mach-omap2/common.c               |   21 +++++++++++++++++++++
 arch/arm/mach-omap2/id.c                   |    6 ++++++
 arch/arm/mach-omap2/io.c                   |   24 ++++++++++++++++++++++++
 arch/arm/mach-omap2/serial.c               |    4 ++--
 arch/arm/plat-omap/include/plat/am33xx.h   |   25 +++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/common.h   |    2 ++
 arch/arm/plat-omap/include/plat/hardware.h |    1 +
 arch/arm/plat-omap/include/plat/io.h       |   20 ++++++++++++++++++++
 arch/arm/plat-omap/include/plat/omap34xx.h |    2 ++
 arch/arm/plat-omap/io.c                    |    5 +++++
 11 files changed, 111 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/am33xx.h
index 5d0064a..c1ab6bc 100644
@@ -3517,6 +3517,9 @@ int __init omap3xxx_clk_init(void)
 	} else if (cpu_is_ti816x()) {
 		cpu_mask = RATE_IN_TI816X;
 		cpu_clkflg = CK_TI816X;
+	} else if (cpu_is_am33xx()) {
+		cpu_mask = RATE_IN_AM33XX;
+		cpu_clkflg = CK_AM33XX;
 	} else if (cpu_is_omap34xx()) {
 		if (omap_rev() == OMAP3430_REV_ES1_0) {
 			cpu_mask = RATE_IN_3430ES1;

index 110e5b9..16bac26 100644
@@ -128,6 +128,27 @@ void __init omap2_set_globals_ti816x(void)
 {
 	__omap2_set_globals(&ti816x_globals);
 }
+
+#define AM33XX_TAP_BASE		(AM33XX_CTRL_BASE + \
+				TI816X_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals am33xx_globals = {
+	.class  = AM335X_CLASS,
+	.tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
+	.ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+	.prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+	.cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+};
+
+void __init omap2_set_globals_am33xx(void)
+{
+	__omap2_set_globals(&am33xx_globals);
+}
+
+void __init am33xx_map_io(void)
+{
+	omapam33xx_map_common_io();
+}
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)

index f1784ee..37fe42f 100644
@@ -340,6 +340,10 @@ static void __init omap3_check_revision(const char **cpu_rev)
 			break;
 		}
 		break;
+	case 0xb944:
+		omap_revision = AM335X_REV_ES1_0;
+		*cpu_rev = "1.0";
+		break;
 	default:
 		/* Unknown default to latest silicon rev as default */
 		omap_revision = OMAP3630_REV_ES1_2;

@@ -432,6 +436,8 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
 		cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 	} else if (cpu_is_ti816x()) {
 		cpu_name = "TI816X";
+	} else if (cpu_is_am335x()) {
+		cpu_name =  "AM335X";
 	} else if (omap3_has_iva() && omap3_has_sgx()) {
 		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 		cpu_name = "OMAP3430/3530";

index da9bc4a..74e84c6 100644
@@ -183,7 +183,24 @@ static struct map_desc omapti816x_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
 		.length		= L4_34XX_SIZE,
 		.type		= MT_DEVICE
+	}
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
+	{
+		.virtual	= L4_34XX_VIRT,
+		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
+		.length		= L4_34XX_SIZE,
+		.type		= MT_DEVICE
 	},
+	{
+		.virtual	= L4_WK_AM33XX_VIRT,
+		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
+		.length		= L4_WK_AM33XX_SIZE,
+		.type		= MT_DEVICE
+	}
 };
 #endif
 

@@ -270,6 +287,13 @@ void __init omapti816x_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
+{
+	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap44xx_map_common_io(void)
 {

index 0dbd5a2..03fc153 100644
@@ -464,7 +464,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
 		mod_timer(&uart->timer, jiffies + uart->timeout);
 	omap_uart_smart_idle_enable(uart, 0);
 
-	if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx())) {
 		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 		u32 wk_mask = 0;
 		u32 padconf = 0;

@@ -828,7 +828,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
 	}
 
 	/* Enable the MDR1 errata for OMAP3 */
-	if (cpu_is_omap34xx() && !cpu_is_ti816x())
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx()))
 		uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 

new file mode 100644
index 0000000..06c19bb
@@ -0,0 +1,25 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+#define L4_SLOW_AM33XX_BASE	0x48000000
+
+#define AM33XX_SCM_BASE		0x44E10000
+#define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
+#define AM33XX_PRCM_BASE	0x44E00000
+
+#endif /* __ASM_ARCH_AM33XX_H */

index 3ff3e36..bb8a6c1 100644
@@ -82,6 +82,7 @@ void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
 void omap2_set_globals_ti816x(void);
+void omap2_set_globals_am33xx(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);

@@ -92,6 +93,7 @@ void omap2_set_globals_prcm(struct omap_globals *);
 void omap242x_map_io(void);
 void omap243x_map_io(void);
 void omap3_map_io(void);
+void am33xx_map_io(void);
 void omap4_map_io(void);
 
 

index e87efe1..e6521e1 100644
@@ -287,5 +287,6 @@
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
 #include <plat/ti816x.h>
+#include <plat/am33xx.h>
 
 #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */

index 7f2969e..ffed821 100644
@@ -73,6 +73,9 @@
 #define OMAP4_L3_IO_OFFSET	0xb4000000
 #define OMAP4_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
 
+#define AM33XX_L4_WK_IO_OFFSET	0xb5000000
+#define AM33XX_L4_WK_IO_ADDRESS(pa)	IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
+
 #define OMAP4_L3_PER_IO_OFFSET	0xb1100000
 #define OMAP4_L3_PER_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
 

@@ -154,6 +157,15 @@
 #define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 
 /*
+ * ----------------------------------------------------------------------------
+ * AM33XX specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L4_WK_AM33XX_PHYS	L4_WK_AM33XX_BASE
+#define L4_WK_AM33XX_VIRT	(L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
+#define L4_WK_AM33XX_SIZE	SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+
+/*
  * Need to look at the Size 4M for L4.
  * VPOM3430 was not working for Int controller
  */

@@ -316,6 +328,14 @@ static inline void omapti816x_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
+{
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 extern void omap44xx_map_common_io(void);
 #else

index b9e8588..0d818ac 100644
@@ -35,6 +35,8 @@
 #define L4_EMU_34XX_BASE	0x54000000
 #define L3_34XX_BASE		0x68000000
 
+#define L4_WK_AM33XX_BASE	0x44C00000
+
 #define OMAP3430_32KSYNCT_BASE	0x48320000
 #define OMAP3430_CM_BASE	0x48004800
 #define OMAP3430_PRM_BASE	0x48306800

index 333871f..14c421a 100644
@@ -94,6 +94,11 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
 	if (cpu_is_ti816x()) {
 		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
 			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+	} else if (cpu_is_am33xx()) {
+		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+		if (BETWEEN(p, L4_WK_AM33XX_PHYS, L4_WK_AM33XX_SIZE))
+			return XLATE(p, L4_WK_AM33XX_PHYS, L4_WK_AM33XX_VIRT);
 	} else if (cpu_is_omap34xx()) {
 		if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
 			return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);

index 5d0064a..c1ab6bc 100644
@@ -3517,6 +3517,9 @@ int __init omap3xxx_clk_init(void)
 	} else if (cpu_is_ti816x()) {
 		cpu_mask = RATE_IN_TI816X;
 		cpu_clkflg = CK_TI816X;
+	} else if (cpu_is_am33xx()) {
+		cpu_mask = RATE_IN_AM33XX;
+		cpu_clkflg = CK_AM33XX;
 	} else if (cpu_is_omap34xx()) {
 		if (omap_rev() == OMAP3430_REV_ES1_0) {
 			cpu_mask = RATE_IN_3430ES1;

index 684b8a7..c900dcb 100644
@@ -128,6 +128,27 @@ void __init omap2_set_globals_ti816x(void)
 {
 	__omap2_set_globals(&ti816x_globals);
 }
+
+#define AM33XX_TAP_BASE		(AM33XX_CTRL_BASE + \
+				TI816X_CONTROL_DEVICE_ID - 0x204)
+
+static struct omap_globals am33xx_globals = {
+	.class  = AM335X_CLASS,
+	.tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
+	.ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+	.prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+	.cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+};
+
+void __init omap2_set_globals_am33xx(void)
+{
+	__omap2_set_globals(&am33xx_globals);
+}
+
+void __init am33xx_map_io(void)
+{
+	omapam33xx_map_common_io();
+}
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)

index 012bac7..9b733e3 100644
@@ -60,6 +60,14 @@ static inline void omapti816x_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
+{
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 extern void omap44xx_map_common_io(void);
 #else

@@ -107,6 +115,7 @@ void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
 void omap2_set_globals_ti816x(void);
+void omap2_set_globals_am33xx(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);

@@ -117,6 +126,7 @@ void omap2_set_globals_prcm(struct omap_globals *);
 void omap242x_map_io(void);
 void omap243x_map_io(void);
 void omap3_map_io(void);
+void am33xx_map_io(void);
 void omap4_map_io(void);
 
 /**

index 27ad722..7ab09f7 100644
@@ -340,6 +340,10 @@ static void __init omap3_check_revision(const char **cpu_rev)
 			break;
 		}
 		break;
+	case 0xb944:
+		omap_revision = AM335X_REV_ES1_0;
+		*cpu_rev = "1.0";
+		break;
 	default:
 		/* Unknown default to latest silicon rev as default */
 		omap_revision = OMAP3630_REV_ES1_2;

@@ -432,6 +436,8 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
 		cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 	} else if (cpu_is_ti816x()) {
 		cpu_name = "TI816X";
+	} else if (cpu_is_am335x()) {
+		cpu_name =  "AM335X";
 	} else if (omap3_has_iva() && omap3_has_sgx()) {
 		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 		cpu_name = "OMAP3430/3530";

index 3f565dd..088d2ba 100644
@@ -183,7 +183,24 @@ static struct map_desc omapti816x_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
 		.length		= L4_34XX_SIZE,
 		.type		= MT_DEVICE
+	}
+};
+#endif
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
+	{
+		.virtual	= L4_34XX_VIRT,
+		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
+		.length		= L4_34XX_SIZE,
+		.type		= MT_DEVICE
 	},
+	{
+		.virtual	= L4_WK_AM33XX_VIRT,
+		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
+		.length		= L4_WK_AM33XX_SIZE,
+		.type		= MT_DEVICE
+	}
 };
 #endif
 

@@ -270,6 +287,13 @@ void __init omapti816x_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
+{
+	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap44xx_map_common_io(void)
 {

index 42c3267..9770c76 100644
@@ -464,7 +464,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
 		mod_timer(&uart->timer, jiffies + uart->timeout);
 	omap_uart_smart_idle_enable(uart, 0);
 
-	if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx())) {
 		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 		u32 wk_mask = 0;
 		u32 padconf = 0;

@@ -828,7 +828,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
 	}
 
 	/* Enable the MDR1 errata for OMAP3 */
-	if (cpu_is_omap34xx() && !cpu_is_ti816x())
+	if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx()))
 		uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 

new file mode 100644
index 0000000..06c19bb
@@ -0,0 +1,25 @@
+/*
+ * This file contains the address info for various AM33XX modules.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+#define L4_SLOW_AM33XX_BASE	0x48000000
+
+#define AM33XX_SCM_BASE		0x44E10000
+#define AM33XX_CTRL_BASE	AM33XX_SCM_BASE
+#define AM33XX_PRCM_BASE	0x44E00000
+
+#endif /* __ASM_ARCH_AM33XX_H */

index e87efe1..e6521e1 100644
@@ -287,5 +287,6 @@
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
 #include <plat/ti816x.h>
+#include <plat/am33xx.h>
 
 #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */

index 1234944..0696bae 100644
@@ -73,6 +73,9 @@
 #define OMAP4_L3_IO_OFFSET	0xb4000000
 #define OMAP4_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
 
+#define AM33XX_L4_WK_IO_OFFSET	0xb5000000
+#define AM33XX_L4_WK_IO_ADDRESS(pa)	IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
+
 #define OMAP4_L3_PER_IO_OFFSET	0xb1100000
 #define OMAP4_L3_PER_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
 

@@ -154,6 +157,15 @@
 #define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 
 /*
+ * ----------------------------------------------------------------------------
+ * AM33XX specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L4_WK_AM33XX_PHYS	L4_WK_AM33XX_BASE
+#define L4_WK_AM33XX_VIRT	(L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
+#define L4_WK_AM33XX_SIZE	SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+
+/*
  * Need to look at the Size 4M for L4.
  * VPOM3430 was not working for Int controller
  */

index b9e8588..0d818ac 100644
@@ -35,6 +35,8 @@
 #define L4_EMU_34XX_BASE	0x54000000
 #define L3_34XX_BASE		0x68000000
 
+#define L4_WK_AM33XX_BASE	0x44C00000
+
 #define OMAP3430_32KSYNCT_BASE	0x48320000
 #define OMAP3430_CM_BASE	0x48004800
 #define OMAP3430_PRM_BASE	0x48306800

---
 arch/arm/mach-omap2/Kconfig              |    5 +++++
 arch/arm/mach-omap2/Makefile             |    1 +
 arch/arm/mach-omap2/board-am3517evm.c    |   21 +++++++++++++++++++++
 arch/arm/mach-omap2/io.c                 |    7 +++++++
 arch/arm/mach-omap2/timer.c              |    2 ++
 arch/arm/plat-omap/include/plat/common.h |    2 ++
 6 files changed, 38 insertions(+), 0 deletions(-)
index 09ea525..c0e4a70 100644
@@ -326,6 +326,11 @@ config MACH_TI8168EVM
 	depends on SOC_OMAPTI816X
 	default y
 
+config MACH_AM335XEVM
+	bool "AM335X Evaluation Module"
+	depends on SOC_OMAPAM33XX
+	default y
+
 config MACH_OMAP_4430SDP
 	bool "OMAP 4430 SDP board"
 	default y

index a12a069..89099a3 100644
@@ -233,6 +233,7 @@ obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
 
 obj-$(CONFIG_MACH_SBC3530)		+= board-omap3stalker.o
 obj-$(CONFIG_MACH_TI8168EVM)		+= board-ti8168evm.o
+obj-$(CONFIG_MACH_AM335XEVM)		+= board-am3517evm.o
 
 # Platform specific device init code
 

index f7df8d3..090457f 100644
@@ -516,3 +516,24 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
 	.init_machine	= am3517_evm_init,
 	.timer		= &omap3_timer,
 MACHINE_END
+
+static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
+};
+
+static void __init am335x_evm_init(void)
+{
+	omap_serial_init();
+	omap_sdrc_init(NULL, NULL);
+	omap_board_config = am335x_evm_config;
+	omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
+}
+
+MACHINE_START(AM335XEVM, "am335xevm")
+	/* Maintainer: Texas Instruments */
+	.atag_offset	= 0x100,
+	.map_io		= am33xx_map_io,
+	.init_early	= am33xx_init_early,
+	.init_irq	= ti816x_init_irq,
+	.timer		= &omap3_am33xx_timer,
+	.init_machine	= am335x_evm_init,
+MACHINE_END

index 74e84c6..e958c04 100644
@@ -460,6 +460,13 @@ void __init ti816x_init_early(void)
 	omap_hwmod_init_postsetup();
 	omap3xxx_clk_init();
 }
+
+void __init am33xx_init_early(void)
+{
+	omap2_set_globals_am33xx();
+	omap_common_init_early();
+	omap3xxx_clk_init();
+}
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4

index 037b0d7..7b29197 100644
@@ -333,6 +333,8 @@ OMAP_SYS_TIMER(3)
 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 			2, OMAP3_MPU_SOURCE)
 OMAP_SYS_TIMER(3_secure)
+OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(3_am33xx)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4

index bb8a6c1..9d7cc3c 100644
@@ -39,6 +39,7 @@ extern struct sys_timer omap1_timer;
 extern struct sys_timer omap2_timer;
 extern struct sys_timer omap3_timer;
 extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap3_am33xx_timer;
 extern struct sys_timer omap4_timer;
 extern bool omap_32k_timer_init(void);
 extern int __init omap_init_clocksource_32k(void);

@@ -55,6 +56,7 @@ void omap3_init_early(void);	/* Do not use this one */
 void am35xx_init_early(void);
 void ti816x_init_early(void);
 void omap4430_init_early(void);
+void am33xx_init_early(void);
 
 extern int omap_dss_reset(struct omap_hwmod *);
 

---
 arch/arm/mach-omap2/Kconfig           |    5 ++++
 arch/arm/mach-omap2/Makefile          |    1 +
 arch/arm/mach-omap2/board-am335xevm.c |   46 +++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/common.h          |    2 ++
 arch/arm/mach-omap2/io.c              |    8 ++++++
 arch/arm/mach-omap2/timer.c           |    2 ++
 6 files changed, 64 insertions(+)
 create mode 100644 arch/arm/mach-omap2/board-am335xevm.c
index 5ae756a..d5aa936 100644
@@ -335,6 +335,11 @@ config MACH_TI8148EVM
 	depends on SOC_OMAPTI81XX
 	default y
 
+config MACH_AM335XEVM
+	bool "AM335X Evaluation Module"
+	depends on SOC_OMAPAM33XX
+	default y
+
 config MACH_OMAP_4430SDP
 	bool "OMAP 4430 SDP board"
 	default y

index c538b3e..d3c33df 100644
@@ -241,6 +241,7 @@ obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
 obj-$(CONFIG_MACH_SBC3530)		+= board-omap3stalker.o
 obj-$(CONFIG_MACH_TI8168EVM)		+= board-ti8168evm.o
 obj-$(CONFIG_MACH_TI8148EVM)		+= board-ti8168evm.o
+obj-$(CONFIG_MACH_AM335XEVM)		+= board-am335xevm.o
 
 # Platform specific device init code
 

index 57da7f4..dae39a3 100644
@@ -83,6 +83,7 @@ extern void omap2_init_common_infrastructure(void);
 extern struct sys_timer omap2_timer;
 extern struct sys_timer omap3_timer;
 extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap3_am33xx_timer;
 extern struct sys_timer omap4_timer;
 
 void omap2420_init_early(void);

@@ -94,6 +95,7 @@ void omap3_init_early(void);	/* Do not use this one */
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void omap4430_init_early(void);
+void am33xx_init_early(void);
 void omap_prcm_restart(char, const char *);
 
 /*

index 065bd76..056db56 100644
@@ -466,6 +466,14 @@ void __init ti81xx_init_early(void)
 	omap_hwmod_init_postsetup();
 	omap3xxx_clk_init();
 }
+#endif /* CONFIG_ARCH_OMAP3 */
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init am33xx_init_early(void)
+{
+	omap2_set_globals_am33xx();
+	omap_common_init_early();
+}
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4

index c512bac..b2f747b 100644
@@ -321,6 +321,8 @@ OMAP_SYS_TIMER(3)
 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 			2, OMAP3_MPU_SOURCE)
 OMAP_SYS_TIMER(3_secure)
+OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(3_am33xx)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4

1.7.10
---
 arch/arm/mach-omap2/Kconfig           |    5 ++++
 arch/arm/mach-omap2/Makefile          |    1 +
 arch/arm/mach-omap2/board-am335xevm.c |   46 +++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/common.h          |    2 ++
 arch/arm/mach-omap2/io.c              |    8 ++++++
 arch/arm/mach-omap2/timer.c           |    2 ++
 6 files changed, 64 insertions(+)
 create mode 100644 arch/arm/mach-omap2/board-am335xevm.c
index 5ae756a..d5aa936 100644
@@ -335,6 +335,11 @@ config MACH_TI8148EVM
 	depends on SOC_OMAPTI81XX
 	default y
 
+config MACH_AM335XEVM
+	bool "AM335X Evaluation Module"
+	depends on SOC_OMAPAM33XX
+	default y
+
 config MACH_OMAP_4430SDP
 	bool "OMAP 4430 SDP board"
 	default y

index c538b3e..d3c33df 100644
@@ -241,6 +241,7 @@ obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
 obj-$(CONFIG_MACH_SBC3530)		+= board-omap3stalker.o
 obj-$(CONFIG_MACH_TI8168EVM)		+= board-ti8168evm.o
 obj-$(CONFIG_MACH_TI8148EVM)		+= board-ti8168evm.o
+obj-$(CONFIG_MACH_AM335XEVM)		+= board-am335xevm.o
 
 # Platform specific device init code
 

new file mode 100644
index 0000000..324752e
@@ -0,0 +1,46 @@
+/*
+ * board-am335xevm.c - support the TI AM335x EVM board
+ *
+ * Copyright (C) 2011-2012 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/board.h>
+#include "common.h"
+
+static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
+};
+
+static void __init am335x_evm_init(void)
+{
+	omap_serial_init();
+	omap_sdrc_init(NULL, NULL);
+	omap_board_config = am335x_evm_config;
+	omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
+}
+
+MACHINE_START(AM335XEVM, "am335xevm")
+	/* Maintainer: Texas Instruments */
+	.atag_offset	= 0x100,
+	.map_io		= am33xx_map_io,
+	.init_early	= am33xx_init_early,
+	.init_irq	= ti81xx_init_irq,
+	.timer		= &omap3_am33xx_timer,
+	.init_machine	= am335x_evm_init,
+MACHINE_END

index 57da7f4..dae39a3 100644
@@ -83,6 +83,7 @@ extern void omap2_init_common_infrastructure(void);
 extern struct sys_timer omap2_timer;
 extern struct sys_timer omap3_timer;
 extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap3_am33xx_timer;
 extern struct sys_timer omap4_timer;
 
 void omap2420_init_early(void);

@@ -94,6 +95,7 @@ void omap3_init_early(void);	/* Do not use this one */
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void omap4430_init_early(void);
+void am33xx_init_early(void);
 void omap_prcm_restart(char, const char *);
 
 /*

index 065bd76..056db56 100644
@@ -466,6 +466,14 @@ void __init ti81xx_init_early(void)
 	omap_hwmod_init_postsetup();
 	omap3xxx_clk_init();
 }
+#endif /* CONFIG_ARCH_OMAP3 */
+
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init am33xx_init_early(void)
+{
+	omap2_set_globals_am33xx();
+	omap_common_init_early();
+}
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4

index c512bac..b2f747b 100644
@@ -321,6 +321,8 @@ OMAP_SYS_TIMER(3)
 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 			2, OMAP3_MPU_SOURCE)
 OMAP_SYS_TIMER(3_secure)
+OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(3_am33xx)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4

1.7.10
 Documentation/kernel-parameters.txt        |    3 +
 arch/arm/mach-omap2/Makefile               |    2 +-
 arch/arm/mach-omap2/cclock33xx_data.c      |   47 +++++++++++++++--
 arch/arm/mach-omap2/debugss.c              |   80 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |   69 ++++++++++++++++--------
 5 files changed, 173 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/mach-omap2/debugss.c
 Documentation/kernel-parameters.txt        |    3 +
 arch/arm/mach-omap2/Makefile               |    2 +-
 arch/arm/mach-omap2/cclock33xx_data.c      |   47 +++++++++++++++--
 arch/arm/mach-omap2/debugss.c              |   80
++++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c |   69 ++++++++++++++++----
----
 5 files changed, 173 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/mach-omap2/debugss.c
---
 arch/arm/mach-omap2/cclock33xx_data.c |   47 +++++++++++++++++++++++++++++---
 1 files changed, 42 insertions(+), 5 deletions(-)
index 3d5a0e5..12db88c 100644
@@ -422,15 +422,11 @@ DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
  *  - Driver code is not yet migrated to use hwmod/runtime pm
  *  - Modules outside kernel access (to disable them by default)
  *
- *     - debugss
  *     - mmu (gfx domain)
  *     - cefuse
  *     - usbotg_fck (its additional clock and not really a modulemode)
  *     - ieee5000
  */
-DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-		AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-		0x0, NULL);
 
 DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
 		AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,

@@ -833,6 +829,42 @@ static struct clk_hw_omap wdt1_fck_hw = {
 DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
 
 /*
+ * debugss optional clocks
+ */
+DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
+		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+		AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
+		0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+		AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
+
+static const char *stm_pmd_clock_mux_ck_parents[] = {
+	"dbg_sysclk_ck", "dbg_clka_ck",
+};
+
+DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
+	       AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+	       AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+	       AM33XX_TRC_PMD_CLKSEL_SHIFT,
+	       AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
+		   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+		   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
+		   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+		   NULL);
+
+DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
+		   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+		   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
+		   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+		   NULL);
+
+/*
  * clkdev
  */
 static struct omap_clk am33xx_clks[] = {

@@ -869,7 +901,6 @@ static struct omap_clk am33xx_clks[] = {
 	CLK("481cc000.d_can",	NULL,		&dcan0_fck,	CK_AM33XX),
 	CLK(NULL,	"dcan1_fck",		&dcan1_fck,	CK_AM33XX),
 	CLK("481d0000.d_can",	NULL,		&dcan1_fck,	CK_AM33XX),
-	CLK(NULL,	"debugss_ick",		&debugss_ick,	CK_AM33XX),
 	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk,	CK_AM33XX),
 	CLK(NULL,	"mcasp0_fck",		&mcasp0_fck,	CK_AM33XX),
 	CLK(NULL,	"mcasp1_fck",		&mcasp1_fck,	CK_AM33XX),

@@ -910,6 +941,12 @@ static struct omap_clk am33xx_clks[] = {
 	CLK(NULL,	"clkout2_div_ck",	&clkout2_div_ck,	CK_AM33XX),
 	CLK(NULL,	"timer_32k_ck",		&clkdiv32k_ick,	CK_AM33XX),
 	CLK(NULL,	"timer_sys_ck",		&sys_clkin_ck,	CK_AM33XX),
+	CLK(NULL,	"dbg_sysclk_ck",	&dbg_sysclk_ck,	CK_AM33XX),
+	CLK(NULL,	"dbg_clka_ck",		&dbg_clka_ck,	CK_AM33XX),
+	CLK(NULL,	"stm_pmd_clock_mux_ck",	&stm_pmd_clock_mux_ck,	CK_AM33XX),
+	CLK(NULL,	"trace_pmd_clk_mux_ck",	&trace_pmd_clk_mux_ck,	CK_AM33XX),
+	CLK(NULL,	"stm_clk_div_ck",	&stm_clk_div_ck,	CK_AM33XX),
+	CLK(NULL,	"trace_clk_div_ck",	&trace_clk_div_ck,	CK_AM33XX),
 };
 
 

 Documentation/kernel-parameters.txt |    3 +
 arch/arm/mach-omap2/Makefile        |    2 +-
 arch/arm/mach-omap2/debugss.c       |   80 +++++++++++++++++++++++++++++++++++
 3 files changed, 84 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/debugss.c
index 6c72381..bf1c822 100644
@@ -2051,6 +2051,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			For example, to override I2C bus2:
 			omap_mux=i2c2_scl.i2c2_scl=0x100,i2c2_sda.i2c2_sda=0x100
 
+	omap_debugss_en	[OMAP] Enable Debug Sub-System module required
+			for JTAG debugging.
+
 	oprofile.timer=	[HW]
 			Use timer interrupt instead of performance counters
 

index d1156cf..aaf5cc2 100644
@@ -5,7 +5,7 @@
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
 	 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
-	 omap_device.o sram.o
+	 omap_device.o sram.o debugss.o
 
 omap-2-3-common				= irq.o
 hwmod-common				= omap_hwmod.o \

 Documentation/kernel-parameters.txt |    3 +
 arch/arm/mach-omap2/Makefile        |    2 +-
 arch/arm/mach-omap2/debugss.c       |   80 +++++++++++++++++++++++++++++++++++
 3 files changed, 84 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/debugss.c
index 6c72381..bf1c822 100644
@@ -2051,6 +2051,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 			For example, to override I2C bus2:
 			omap_mux=i2c2_scl.i2c2_scl=0x100,i2c2_sda.i2c2_sda=0x100
 
+	omap_debugss_en	[OMAP] Enable Debug Sub-System module required
+			for JTAG debugging.
+
 	oprofile.timer=	[HW]
 			Use timer interrupt instead of performance counters
 

index d1156cf..aaf5cc2 100644
@@ -5,7 +5,7 @@
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
 	 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
-	 omap_device.o sram.o
+	 omap_device.o sram.o debugss.o
 
 omap-2-3-common				= irq.o
 hwmod-common				= omap_hwmod.o \

new file mode 100644
index 0000000..b45bf2c
@@ -0,0 +1,80 @@
+/*
+ * debugss.c: Debug Sus-System related code goes in here
+ *
+ * Copyright (C) {2013} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include "omap_hwmod.h"
+
+static bool is_debugss_en;
+
+/**
+ * omap_debugss_en - Enable debugss clock/module based on user config
+ *
+ * During kernel bootup, omap2 hwmod framework will disable all the
+ * unused/unclaimed modules, which in turn also disables debugss module.
+ * This breaks any further debugging capability provided by HW.
+ *
+ *
+ * Introduce early param which allows user to enable clock/module -
+ *
+ *   omap_debugss_en	(For all OMAP2 architectures)
+ *
+ * Please note that, with this command-line param, module always remain
+ * enabled.
+ */
+static int __init omap_debugss_en(char *str)
+{
+	is_debugss_en = true;
+	return 0;
+}
+early_param("omap_debugss_en", omap_debugss_en);
+
+static int __init _omap2_debugss_enable(void)
+{
+	const char oh_name[10] = "debugss";
+	struct omap_hwmod *oh;
+	int ret;
+
+	if (is_debugss_en) {
+		struct omap_hwmod_opt_clk *oc;
+		int i;
+
+		oh = omap_hwmod_lookup(oh_name);
+		if (!oh) {
+			pr_err("debugss device not found\n");
+			return 0;
+		}
+
+		/* Make sure that hwmod internal data structures are setup */
+		ret = omap_hwmod_setup_one(oh_name);
+		if (ret) {
+			pr_err("failed to setup hwmod for %s\n", oh_name);
+			return 0;
+		}
+		/* Enable optional clocks */
+		for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)	{
+			if (oc->_clk)
+				clk_prepare_enable(oc->_clk);
+		}
+		/* Enable debugss clock/module  */
+		omap_hwmod_enable(oh);
+	}
+
+	return 0;
+}
+device_initcall(_omap2_debugss_enable);
--

	debugss: debugss at 4b000000 {
		compatible = "ti,debugss";
		ti,hwmods = "debugss";
		reg = <0x4b000000 1000000>;
		status = "disabled";	/* User need to enable it if he need JTAG connectivity*/
	};
	static int __init _omap2_debugss_enable(void)
	{
		struct device_node *np;
	
		np = of_find_matching_node(oh_name);
		if (!node || ! of_device_is_available()) {
			pr_err("debugss device is not found\n");
			return -ENODEV;
		}
		...
		hwmod lookup./setup/enable along with optional clock enable.
		...

	}
	device_initcall(_omap2_debugss_enable);
	debugss: debugss at 4b000000 {
		compatible = "ti,debugss";
		ti,hwmods = "debugss";
		reg = <0x4b000000 1000000>;
		status = "disabled";	/* User need to enable it if he need JTAG connectivity*/
	};
	static int __init _omap2_debugss_enable(void)
	{
		struct device_node *np;
	
		np = of_find_matching_node(oh_name);
		if (!node || ! of_device_is_available()) {
			pr_err("debugss device is not found\n");
			return -ENODEV;
		}
		...
		hwmod lookup./setup/enable along with optional clock enable.
		...

	}
	device_initcall(_omap2_debugss_enable);
---
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    1 +
 board/ti/am335x/board.c                     |    6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)
index ae43ef8..7ab3baf 100644
@@ -28,6 +28,7 @@
 #define VTP_CTRL_START_EN	(0x1)
 #define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
+#define PHY_EN_DYN_PWRDN	(0x1 << 20)
 
 /* Micron MT47H128M16RT-25E */
 #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005

index 48e6896..22d7b25 100644
@@ -251,7 +251,8 @@ static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 	.zq_config = MT41J128MJT125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 };
 
 static struct emif_regs ddr3_evm_emif_reg_data = {

@@ -261,7 +262,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 };
 #endif
 

1.7.0.4
---
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    1 +
 board/ti/am335x/board.c                     |    6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)
index ae43ef8..7ab3baf 100644
@@ -28,6 +28,7 @@
 #define VTP_CTRL_START_EN	(0x1)
 #define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
+#define PHY_EN_DYN_PWRDN	(0x1 << 20)
 
 /* Micron MT47H128M16RT-25E */
 #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005

index 48e6896..22d7b25 100644
@@ -251,7 +251,8 @@ static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 	.zq_config = MT41J128MJT125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 };
 
 static struct emif_regs ddr3_evm_emif_reg_data = {

@@ -261,7 +262,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 };
 #endif

Tom
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 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    1 +
 board/ti/am335x/board.c                     |    6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)
@@ -28,6 +28,7 @@
 
 #define VTP_CTRL_START_EN	(0x1)
 #define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
 
+#define PHY_EN_DYN_PWRDN	(0x1 << 20)
 

index 48e6896..22d7b25 100644
@@ -251,7 +251,8 @@ static struct emif_regs ddr3_emif_reg_data = {
 
 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 	.zq_config = MT41J128MJT125_ZQ_CFG,
 
-	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 

@@ -261,7 +262,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
 
-	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 

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