gpio: Add PCA9698 40-bit I2C I/O port

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new file mode 100644
index 0000000..2506088
@@ -0,0 +1,9 @@
+#ifndef __PCA9698_H_
+#define __PCA9698_H_
+
+int pca9698_direction_input(u8 chip, unsigned offset);
+int pca9698_direction_output(u8 chip, unsigned offset);
+int pca9698_get_input(u8 chip, unsigned offset);
+int pca9698_set_output(u8 chip, unsigned offset, int value);
+
+#endif /* __PCA9698_H_ */

index 3ff4a86..931a43f 100644
@@ -37,10 +37,10 @@
 #define CONFIG_460EX		1	/* Specific PPC460EX		*/
 #ifdef CONFIG_DEVCONCENTER
 #define CONFIG_HOSTNAME		devconcenter
-#define CONFIG_IDENT_STRING	" devconcenter 0.02"
+#define CONFIG_IDENT_STRING	" devconcenter 0.03"
 #else
 #define CONFIG_HOSTNAME		intip
-#define CONFIG_IDENT_STRING	" intip 0.02"
+#define CONFIG_IDENT_STRING	" intip 0.03"
 #endif
 #define CONFIG_440		1
 #define CONFIG_4xx		1	/* ... PPC4xx family */

@@ -63,6 +63,10 @@
 #define CONFIG_FIT
 #define CFG_ALT_MEMTEST
 
+#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)

index 4fc5262..1468197 100644
@@ -34,7 +34,7 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		dlvsion-10g
-#define CONFIG_IDENT_STRING	" dlvision-10g 0.01"
+#define CONFIG_IDENT_STRING	" dlvision-10g 0.02"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */

@@ -117,8 +117,8 @@
 #define CONFIG_DTT_LM63		1	/* National LM63	*/
 #define CONFIG_DTT_SENSORS	{ 0x4c, 0x4e }	/* Sensor addresses	*/
 #define CONFIG_DTT_PWM_LOOKUPTABLE	\
-		{ { 40, 10 }, { 43, 13 }, { 46, 16 },  \
-		  { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
+		{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
+		  { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
 #define CONFIG_DTT_TACH_LIMIT	0xa10
 
 /* EBC peripherals */

index 9885b14..1be0a34 100644
@@ -130,6 +130,10 @@ ulong monitor_flash_len;
 #include <bedbug/type.h>
 #endif
 
+#ifdef CONFIG_SYS_FPGA_COUNT
+#include <gdsys_fpga.h>
+#endif
+
 /************************************************************************
  * Utilities								*
  ************************************************************************

@@ -322,6 +326,9 @@ init_fnc_t *init_sequence[] = {
 #ifdef CONFIG_POST
 	post_init_f,
 #endif
+#ifdef CONFIG_FPGA_INIT
+	init_func_fpga,
+#endif
 	INIT_FUNC_WATCHDOG_RESET
 	init_func_ram,
 #if defined(CONFIG_SYS_DRAM_TEST)

250 lines not on this page · raw message

new file mode 100644
index 0000000..b15623f
@@ -0,0 +1,10 @@
+#ifndef __405EX_H_
+#define __405EX_H_
+
+/* functions to be provided by board implementation */
+void gd405ex_init(void);
+void gd405ex_set_fpga_reset(unsigned state);
+void gd405ex_setup_hw(void);
+int gd405ex_get_fpga_done(unsigned fpga);
+
+#endif /* __405EX_H_ */

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index c0b1b5c..e7a072b 100644
@@ -24,9 +24,12 @@
 #ifndef __GDSYS_FPGA_H
 #define __GDSYS_FPGA_H
 
+int init_func_fpga(void);
+
 enum {
 	FPGA_STATE_DONE_FAILED = 1 << 0,
 	FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+	FPGA_STATE_PLATFORM = 1 << 2,
 };
 
 int get_fpga_state(unsigned dev);

@@ -68,6 +71,22 @@ typedef struct ihs_fpga {
 } ihs_fpga_t;
 #endif
 
+#ifdef CONFIG_IO64
+typedef struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[5];	/* 0x0008 */
+	u16 quad_serdes_reset;	/* 0x0012 */
+	u16 reserved_1[502];	/* 0x0014 */
+	u16 ch0_status_int;	/* 0x0400 */
+	u16 ch0_config_int;	/* 0x0402 */
+	u16 reserved_2[7677];	/* 0x0404 */
+	u16 reflection_high;	/* 0x3ffe */
+} ihs_fpga_t;
+#endif
+
 #ifdef CONFIG_IOCON
 typedef struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */

index 931a43f..92b65af 100644
@@ -37,10 +37,10 @@
 #define CONFIG_460EX		1	/* Specific PPC460EX		*/
 #ifdef CONFIG_DEVCONCENTER
 #define CONFIG_HOSTNAME		devconcenter
-#define CONFIG_IDENT_STRING	" devconcenter 0.03"
+#define CONFIG_IDENT_STRING	" devconcenter 0.05"
 #else
 #define CONFIG_HOSTNAME		intip
-#define CONFIG_IDENT_STRING	" intip 0.03"
+#define CONFIG_IDENT_STRING	" intip 0.05"
 #endif
 #define CONFIG_440		1
 #define CONFIG_4xx		1	/* ... PPC4xx family */

@@ -200,13 +200,13 @@
 #define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
 #define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
 #define CONFIG_SYS_SDRAM0_INITPLR4	0x81010002
-#define CONFIG_SYS_SDRAM0_INITPLR5	0xE4000542
+#define CONFIG_SYS_SDRAM0_INITPLR5	0xE4000552
 #define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
 #define CONFIG_SYS_SDRAM0_INITPLR7	0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR8	0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR9	0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR10	0x8A880000
-#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000442
+#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000452
 #define CONFIG_SYS_SDRAM0_INITPLR12	0x81010382
 #define CONFIG_SYS_SDRAM0_INITPLR13	0x81010002
 #define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000

@@ -216,11 +216,11 @@
 #define CONFIG_SYS_SDRAM0_RDCC		0x40000000
 #define CONFIG_SYS_SDRAM0_DLCR		0x00000000
 #define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR		0x84000823
+#define CONFIG_SYS_SDRAM0_WRDTR		0x86000823
 #define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
 #define CONFIG_SYS_SDRAM0_SDTR2		0x32204232
 #define CONFIG_SYS_SDRAM0_SDTR3		0x090C0D15
-#define CONFIG_SYS_SDRAM0_MMODE		0x00000442
+#define CONFIG_SYS_SDRAM0_MMODE		0x00000452
 #define CONFIG_SYS_SDRAM0_MEMODE	0x00000002
 
 #define CONFIG_SYS_MBYTES_SDRAM	256	/* 256MB */