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S3C2416: Enable armdiv and armclk

PATCH New Heiko Stübner 2 participants 12 messages Sep 28, 2011 – Oct 14, 2011

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm Samsung Exynos
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Heiko Stübner

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#0 lore raw

cover S3C2416: Enable armdiv and armclk

To enable cpu frequency scaling on the S3C2416/2450 it is necessary to define the arm-divider and armclock.

The layout of the clocks (i.e. msysclk -> armdiv -> armclk) is the same on all three architectures (S3C2443/2416/2450) and only the possible dividers for armdiv differ.
Therefore it is possible to move the armdiv and armclk to common code with only the divider table definition remaining in the respective clock.c-files.
The s3c2443_common_init_clocks method is modified to make it possible to transmit the divider table to the common code.

As the armdiv is available in common code now, the fdiv function pointer passed to s3c2443_common_init_clocks becomes obsolete and is therefore removed as the fclk rate can be set by a clk_get_rate call.

It works as expected on S3C2416, is compile-tested on S3C2443 and checkpatch was happy.

Heiko Stuebner (8):
S3C2416: Add armdiv_mask constant.
S3C2443: Add infrastructure to transmit armdiv to common code
S3C2443: Move clk_arm and clk_armdiv to common code.
S3C2416: Add comment describing the armdiv/armclk.
S3C2443: Add get_rate operation for clk_armdiv
S3C2443: handle unset armdiv values gracefully.
S3C2443: Accommodate cpufreq frequency scheme in armdiv
S3C2443: use clk_get_rate to init fclk in common_setup_clocks

 .../mach-s3c2410/include/mach/regs-s3c2443-clock.h |    1 +
 arch/arm/mach-s3c2416/clock.c                      |   21 ++--
 arch/arm/mach-s3c2443/clock.c                      |   98 +--------------
 arch/arm/plat-s3c24xx/include/plat/s3c2443.h       |    7 +-
 arch/arm/plat-s3c24xx/s3c2443-clock.c              |  134 +++++++++++++++++++-
 5 files changed, 152 insertions(+), 109 deletions(-)
Signature · 1 line
1.7.5.4
author
#1 lore raw

PATCH 1/8 S3C2416: Add armdiv_mask constant

The S3C2416/2450 has only 3 bits for the armdiv setting instead of the 4 bits of the S3C2443.

Signed-off-by Heiko Stuebner <[email protected]>
---
 .../mach-s3c2410/include/mach/regs-s3c2443-clock.h |    1 +
 arch/arm/mach-s3c2416/clock.c                      |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +1 -0
index df6434f..c3feff3 100644
@@ -65,6 +65,7 @@
 #define S3C2443_CLKDIV0_PREDIV_MASK	(3<<4)
 #define S3C2443_CLKDIV0_PREDIV_SHIFT	(4)
 
+#define S3C2416_CLKDIV0_ARMDIV_MASK	(7 << 9)
 #define S3C2443_CLKDIV0_ARMDIV_MASK	(15<<9)
 #define S3C2443_CLKDIV0_ARMDIV_SHIFT	(9)
 #define S3C2443_CLKDIV0_ARMDIV_1	(0<<9)
arch/arm/mach-s3c2416/clock.c +1 -1
index 72b7c62..5569def 100644
@@ -127,7 +127,7 @@ static struct clk hsmmc0_clk = {
 
 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
 {
-	clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
+	clkcon0 &= S3C2416_CLKDIV0_ARMDIV_MASK;
 
 	return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
 }
Signature · 1 line
1.7.5.4
author
#2 lore raw

PATCH 2/8 S3C2443: Add infrastructure to transmit armdiv to common code

In reply to Heiko Stübner

This is needed for making the armdiv clock common to S3C2443 and S3C2416/2450.

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/mach-s3c2416/clock.c                |    4 +++-
 arch/arm/mach-s3c2443/clock.c                |    4 +++-
 arch/arm/plat-s3c24xx/include/plat/s3c2443.h |    4 +++-
 arch/arm/plat-s3c24xx/s3c2443-clock.c        |   12 +++++++++++-
 4 files changed, 20 insertions(+), 4 deletions(-)
arch/arm/mach-s3c2416/clock.c +3 -1
index 5569def..3060796 100644
@@ -158,7 +158,9 @@ void __init s3c2416_init_clocks(int xtal)
 
 	clk_epll.parent = &clk_epllref.clk;
 
-	s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
+	s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div,
+				   armdiv, ARRAY_SIZE(armdiv),
+				   S3C2416_CLKDIV0_ARMDIV_MASK);
 
 	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 		s3c_register_clksrc(clksrcs[ptr], 1);
arch/arm/mach-s3c2443/clock.c +3 -1
index cd51d04..88edc55 100644
@@ -283,7 +283,9 @@ void __init s3c2443_init_clocks(int xtal)
 	clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
 	clk_epll.parent = &clk_epllref.clk;
 
-	s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
+	s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div,
+				   armdiv, ARRAY_SIZE(armdiv),
+				   S3C2443_CLKDIV0_ARMDIV_MASK);
 
 	s3c2443_setup_clocks();
arch/arm/plat-s3c24xx/include/plat/s3c2443.h +3 -1
index a19715f..7b824cb 100644
@@ -40,7 +40,9 @@ typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
 typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
 
 extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
-extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
+extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv,
+				       unsigned int *divs, int nr_divs,
+				       int divmask);
 
 extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
 extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
arch/arm/plat-s3c24xx/s3c2443-clock.c +11 -1
index 07a4c81..3f2117b 100644
@@ -160,6 +160,10 @@ static struct clk clk_prediv = {
 	},
 };
 
+static unsigned int *armdiv;
+static int nr_armdiv;
+static int armdivmask;
+
 /* usbhost
  *
  * usb host bus-clock, usually 48MHz to provide USB bus clock timing

@@ -470,10 +474,16 @@ static struct clksrc_clk *clksrcs[] __initdata = {
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-				       fdiv_fn get_fdiv)
+				       fdiv_fn get_fdiv,
+				       unsigned int *divs, int nr_divs,
+				       int divmask)
 {
 	int ptr;
 
+	armdiv = divs;
+	nr_armdiv = nr_divs;
+	armdivmask = divmask;
+
 	/* s3c2443 parents h and p clocks from prediv */
 	clk_h.parent = &clk_prediv;
 	clk_p.parent = &clk_prediv;
Signature · 1 line
1.7.5.4
author
#3 lore raw

PATCH 3/8 S3C2443: Move clk_arm and clk_armdiv to common code

In reply to Heiko Stübner

The system-layout of the armdiv and armclk is common to S3C2443/2416/2450 and only differs in the array of possible dividers. Therefore it is possible to reuse the clock definitions for all of these SoCs.

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/mach-s3c2443/clock.c         |   85 +-------------------------------
 arch/arm/plat-s3c24xx/s3c2443-clock.c |   87 +++++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+), 83 deletions(-)
arch/arm/mach-s3c2443/clock.c +2 -83
index 88edc55..6fda4bf 100644
@@ -61,10 +61,10 @@
  *
  * this clock is sourced from msysclk and can have a number of
  * divider values applied to it to then be fed into armclk.
+ * The real clock definition is done in s3c2443-clock.c,
+ * only the armdiv divisor table must be defined here.
 */
 
-/* armdiv divisor table */
-
 static unsigned int armdiv[16] = {
 	[S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 1,
 	[S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 2,

@@ -83,85 +83,6 @@ static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
 	return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
 }
 
-static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
-					      unsigned long rate)
-{
-	unsigned long parent = clk_get_rate(clk->parent);
-	unsigned long calc;
-	unsigned best = 256; /* bigger than any value */
-	unsigned div;
-	int ptr;
-
-	for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
-		div = armdiv[ptr];
-		calc = parent / div;
-		if (calc <= rate && div < best)
-			best = div;
-	}
-
-	return parent / best;
-}
-
-static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
-{
-	unsigned long parent = clk_get_rate(clk->parent);
-	unsigned long calc;
-	unsigned div;
-	unsigned best = 256; /* bigger than any value */
-	int ptr;
-	int val = -1;
-
-	for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
-		div = armdiv[ptr];
-		calc = parent / div;
-		if (calc <= rate && div < best) {
-			best = div;
-			val = ptr;
-		}
-	}
-
-	if (val >= 0) {
-		unsigned long clkcon0;
-
-		clkcon0 = __raw_readl(S3C2443_CLKDIV0);
-		clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
-		clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
-		__raw_writel(clkcon0, S3C2443_CLKDIV0);
-	}
-
-	return (val == -1) ? -EINVAL : 0;
-}
-
-static struct clk clk_armdiv = {
-	.name		= "armdiv",
-	.parent		= &clk_msysclk.clk,
-	.ops		= &(struct clk_ops) {
-		.round_rate = s3c2443_armclk_roundrate,
-		.set_rate = s3c2443_armclk_setrate,
-	},
-};
-
-/* armclk
- *
- * this is the clock fed into the ARM core itself, from armdiv or from hclk.
- */
-
-static struct clk *clk_arm_sources[] = {
-	[0] = &clk_armdiv,
-	[1] = &clk_h,
-};
-
-static struct clksrc_clk clk_arm = {
-	.clk	= {
-		.name		= "armclk",
-	},
-	.sources = &(struct clksrc_sources) {
-		.sources = clk_arm_sources,
-		.nr_sources = ARRAY_SIZE(clk_arm_sources),
-	},
-	.reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
-};
-
 /* hsspi
  *
  * high-speed spi clock, sourced from esysclk

@@ -260,14 +181,12 @@ static struct clk init_clocks[] = {
 /* clocks to add straight away */
 
 static struct clksrc_clk *clksrcs[] __initdata = {
-	&clk_arm,
 	&clk_hsspi,
 	&clk_hsmmc_div,
 };
 
 static struct clk *clks[] __initdata = {
 	&clk_hsmmc,
-	&clk_armdiv,
 };
 
 void __init_or_cpufreq s3c2443_setup_clocks(void)
arch/arm/plat-s3c24xx/s3c2443-clock.c +87 -0

109 lines not on this page · raw message

Signature · 1 line
1.7.5.4
author
#4 lore raw

PATCH 4/8 S3C2416: Add comment describing the armdiv/armclk

In reply to Heiko Stübner
Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/mach-s3c2416/clock.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
arch/arm/mach-s3c2416/clock.c +8 -0
index 3060796..7aa0cfa 100644
@@ -28,6 +28,14 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-s3c2443-clock.h>
 
+/* armdiv
+ *
+ * this clock is sourced from msysclk and can have a number of
+ * divider values applied to it to then be fed into armclk.
+ * The real clock definition is done in s3c2443-clock.c,
+ * only the armdiv divisor table must be defined here.
+*/
+
 static unsigned int armdiv[8] = {
 	[0] = 1,
 	[1] = 2,
Signature · 1 line
1.7.5.4
author
#5 lore raw

PATCH 5/8 S3C2443: Add get_rate operation for clk_armdiv

In reply to Heiko Stübner
Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/plat-s3c24xx/s3c2443-clock.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)
arch/arm/plat-s3c24xx/s3c2443-clock.c +14 -0
index f9c5b03..fea3d5c 100644
@@ -189,6 +189,19 @@ static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
 	return parent / best;
 }
 
+static unsigned long s3c2443_armclk_getrate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned long clkcon0;
+	int val;
+
+	clkcon0 = __raw_readl(S3C2443_CLKDIV0);
+	clkcon0 &= armdivmask;
+	val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
+
+	return rate / armdiv[val];
+}
+
 static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
 {
 	unsigned long parent = clk_get_rate(clk->parent);

@@ -224,6 +237,7 @@ static struct clk clk_armdiv = {
 	.parent		= &clk_msysclk.clk,
 	.ops		= &(struct clk_ops) {
 		.round_rate = s3c2443_armclk_roundrate,
+		.get_rate = s3c2443_armclk_getrate,
 		.set_rate = s3c2443_armclk_setrate,
 	},
 };
Signature · 1 line
1.7.5.4
author
#6 lore raw

PATCH 6/8 S3C2443: handle unset armdiv values gracefully

In reply to Heiko Stübner

The armdiv array may contain unset divider values. Check the relevant value to prevent division by zero errors. Also check for set nr_armdiv and armdivmask before meddling with clkdiv0.

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/plat-s3c24xx/s3c2443-clock.c |   27 ++++++++++++++++++++-------
 1 files changed, 20 insertions(+), 7 deletions(-)
arch/arm/plat-s3c24xx/s3c2443-clock.c +20 -7
index fea3d5c..31f97f1 100644
@@ -179,11 +179,16 @@ static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
 	unsigned div;
 	int ptr;
 
+	if (!nr_armdiv)
+		return -EINVAL;
+
 	for (ptr = 0; ptr < nr_armdiv; ptr++) {
 		div = armdiv[ptr];
-		calc = parent / div;
-		if (calc <= rate && div < best)
-			best = div;
+		if (div) {
+			calc = parent / div;
+			if (calc <= rate && div < best)
+				best = div;
+		}
 	}
 
 	return parent / best;

@@ -195,6 +200,9 @@ static unsigned long s3c2443_armclk_getrate(struct clk *clk)
 	unsigned long clkcon0;
 	int val;
 
+	if (!nr_armdiv || !armdivmask)
+		return -EINVAL;
+
 	clkcon0 = __raw_readl(S3C2443_CLKDIV0);
 	clkcon0 &= armdivmask;
 	val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;

@@ -211,12 +219,17 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
 	int ptr;
 	int val = -1;
 
+	if (!nr_armdiv || !armdivmask)
+		return -EINVAL;
+
 	for (ptr = 0; ptr < nr_armdiv; ptr++) {
 		div = armdiv[ptr];
-		calc = parent / div;
-		if (calc <= rate && div < best) {
-			best = div;
-			val = ptr;
+		if (div) {
+			calc = parent / div;
+			if (calc <= rate && div < best) {
+				best = div;
+				val = ptr;
+			}
 		}
 	}
Signature · 1 line
1.7.5.4
author
#7 lore raw

PATCH 7/8 S3C2443: Accommodate cpufreq frequency scheme in armdiv

In reply to Heiko Stübner

Cpufreq uses frequencies in kHz and not Hz, so set_rate and round_rate would be called with a frequency of 266666000 instead of 266666666 but the clock functions check for rates smaller or equal to the targetrate.

As the armdiv does not support steps this small we can accommodate this by simply also setting the last 3 digits of the calculated rate to zero.

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/plat-s3c24xx/s3c2443-clock.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)
arch/arm/plat-s3c24xx/s3c2443-clock.c +4 -2
index 31f97f1..40a8720 100644
@@ -185,7 +185,8 @@ static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
 	for (ptr = 0; ptr < nr_armdiv; ptr++) {
 		div = armdiv[ptr];
 		if (div) {
-			calc = parent / div;
+			/* cpufreq provides 266mhz as 266666000 not 266666666 */
+			calc = (parent / div / 1000) * 1000;
 			if (calc <= rate && div < best)
 				best = div;
 		}

@@ -225,7 +226,8 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
 	for (ptr = 0; ptr < nr_armdiv; ptr++) {
 		div = armdiv[ptr];
 		if (div) {
-			calc = parent / div;
+			/* cpufreq provides 266mhz as 266666000 not 266666666 */
+			calc = (parent / div / 1000) * 1000;
 			if (calc <= rate && div < best) {
 				best = div;
 				val = ptr;
Signature · 1 line
1.7.5.4
author
#8 lore raw

PATCH 8/8 S3C2443: use clk_get_rate to init fclk in common_setup_clocks

In reply to Heiko Stübner

Previously the fclk rate was calculated by dividing the pll through the divider value of the armdiv. With a real armdiv clk in place it's possible to simply read its value, which does essentially the same.

This change makes the whole fdiv_fn function pointers supplied to s3c2443_common_init_clocks and s3c2443_common_setup_clocks obsolete, so remove it too.

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/mach-s3c2416/clock.c                |   11 ++---------
 arch/arm/mach-s3c2443/clock.c                |   11 ++---------
 arch/arm/plat-s3c24xx/include/plat/s3c2443.h |    5 ++---
 arch/arm/plat-s3c24xx/s3c2443-clock.c        |    8 +++-----
 4 files changed, 9 insertions(+), 26 deletions(-)
arch/arm/mach-s3c2416/clock.c +2 -9
index 7aa0cfa..afbbe8b 100644
@@ -133,16 +133,9 @@ static struct clk hsmmc0_clk = {
 	.ctrlbit	= S3C2416_HCLKCON_HSMMC0,
 };
 
-static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
-{
-	clkcon0 &= S3C2416_CLKDIV0_ARMDIV_MASK;
-
-	return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
-}
-
 void __init_or_cpufreq s3c2416_setup_clocks(void)
 {
-	s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
+	s3c2443_common_setup_clocks(s3c2416_get_pll);
 }
 
 

@@ -166,7 +159,7 @@ void __init s3c2416_init_clocks(int xtal)
 
 	clk_epll.parent = &clk_epllref.clk;
 
-	s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div,
+	s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
 				   armdiv, ARRAY_SIZE(armdiv),
 				   S3C2416_CLKDIV0_ARMDIV_MASK);
arch/arm/mach-s3c2443/clock.c +2 -9
index 6fda4bf..b93cb96 100644
@@ -76,13 +76,6 @@ static unsigned int armdiv[16] = {
 	[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]	= 16,
 };
 
-static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
-{
-	clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
-
-	return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
-}
-
 /* hsspi
  *
  * high-speed spi clock, sourced from esysclk

@@ -191,7 +184,7 @@ static struct clk *clks[] __initdata = {
 
 void __init_or_cpufreq s3c2443_setup_clocks(void)
 {
-	s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
+	s3c2443_common_setup_clocks(s3c2443_get_mpll);
 }
 
 void __init s3c2443_init_clocks(int xtal)

@@ -202,7 +195,7 @@ void __init s3c2443_init_clocks(int xtal)
 	clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
 	clk_epll.parent = &clk_epllref.clk;
 
-	s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div,
+	s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
 				   armdiv, ARRAY_SIZE(armdiv),
 				   S3C2443_CLKDIV0_ARMDIV_MASK);
arch/arm/plat-s3c24xx/include/plat/s3c2443.h +2 -3
index 7b824cb..5496316 100644
@@ -37,10 +37,9 @@ extern  int s3c2443_baseclk_add(void);
 struct clk;	/* some files don't need clk.h otherwise */
 
 typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
-typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
 
-extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
-extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv,
+extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
+extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
 				       unsigned int *divs, int nr_divs,
 				       int divmask);
arch/arm/plat-s3c24xx/s3c2443-clock.c +3 -5
index 40a8720..d3ebbee 100644
@@ -520,8 +520,7 @@ static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
 
 /* EPLLCON compatible enough to get on/off information */
 
-void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
-						   fdiv_fn get_fdiv)
+void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 {
 	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
 	unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);

@@ -541,7 +540,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
 	pll = get_mpll(mpllcon, xtal);
 	clk_msysclk.clk.rate = pll;
 
-	fclk = pll / get_fdiv(clkdiv0);
+	fclk = clk_get_rate(&clk_armdiv);
 	hclk = s3c2443_prediv_getrate(&clk_prediv);
 	hclk /= s3c2443_get_hdiv(clkdiv0);
 	pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);

@@ -590,7 +589,6 @@ static struct clksrc_clk *clksrcs[] __initdata = {
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-				       fdiv_fn get_fdiv,
 				       unsigned int *divs, int nr_divs,
 				       int divmask)
 {

@@ -620,5 +618,5 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
 	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
-	s3c2443_common_setup_clocks(get_mpll, get_fdiv);
+	s3c2443_common_setup_clocks(get_mpll);
 }
Signature · 1 line
1.7.5.4
#9 lore raw

cover S3C2416: Enable armdiv and armclk

In reply to Heiko Stübner
Quoted 39 lines · Heiko St?bner

To enable cpu frequency scaling on the S3C2416/2450 it is necessary to define the arm-divider and armclock.

The layout of the clocks (i.e. msysclk -> armdiv -> armclk) is the same on all three architectures (S3C2443/2416/2450) and only the possible dividers for armdiv differ.
Therefore it is possible to move the armdiv and armclk to common code with only the divider table definition remaining in the respective clock.c-files.
The s3c2443_common_init_clocks method is modified to make it possible to transmit the divider table to the common code.

As the armdiv is available in common code now, the fdiv function pointer passed to s3c2443_common_init_clocks becomes obsolete and is therefore removed as the fclk rate can be set by a clk_get_rate call.

It works as expected on S3C2416, is compile-tested on S3C2443 and checkpatch was happy.

Heiko Stuebner (8):
S3C2416: Add armdiv_mask constant.
S3C2443: Add infrastructure to transmit armdiv to common code
S3C2443: Move clk_arm and clk_armdiv to common code.
S3C2416: Add comment describing the armdiv/armclk.
S3C2443: Add get_rate operation for clk_armdiv
S3C2443: handle unset armdiv values gracefully.
S3C2443: Accommodate cpufreq frequency scheme in armdiv
S3C2443: use clk_get_rate to init fclk in common_setup_clocks

 .../mach-s3c2410/include/mach/regs-s3c2443-clock.h |    1 +
 arch/arm/mach-s3c2416/clock.c                      |   21 ++--
 arch/arm/mach-s3c2443/clock.c                      |   98 +--------------
 arch/arm/plat-s3c24xx/include/plat/s3c2443.h       |    7 +-
 arch/arm/plat-s3c24xx/s3c2443-clock.c              |  134
+++++++++++++++++++-
 5 files changed, 152 insertions(+), 109 deletions(-)
Quoted 2 lines

--
1.7.5.4

Looks ok to me, applied.

As a note, if required, 1st patch which is fixing will be sent to stable.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

author
#10 lore raw

cover S3C2416: Enable armdiv and armclk

Hi Kgene,

Am Freitag, 14. Oktober 2011, 09:14:11 schrieb Kukjin Kim:

Quoted 1 line

Heiko St?bner wrote:

[...]

Quoted 2 lines
Quoted 2 lines

Heiko Stuebner (8):
S3C2416: Add armdiv_mask constant.

[...]

Quoted 1 line

As a note, if required, 1st patch which is fixing will be sent to stable.

I don't think this is really necessary.

The original code was essentially correct but hard to read.
The constant makes sense in the rework, as the armdiv_mask is is used in more places now and not contained in a single static function.

Heiko

#11 lore raw

cover S3C2416: Enable armdiv and armclk

Quoted 10 lines · Heiko St?bner

Hi Kgene,

Am Freitag, 14. Oktober 2011, 09:14:11 schrieb Kukjin Kim:

Quoted 1 line

Heiko St?bner wrote:

[...]

Quoted 2 lines
Quoted 2 lines

Heiko Stuebner (8):
S3C2416: Add armdiv_mask constant.

[...]

Quoted 1 line

As a note, if required, 1st patch which is fixing will be sent to

stable.

Quoted 5 lines

I don't think this is really necessary.

The original code was essentially correct but hard to read. The constant makes sense in the rework, as the armdiv_mask is is used in

more

Quoted 2 lines

places now and not contained in a single static function.

OK.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.