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pxa: fix usb host register mismatch

PATCH New Stefan Herbrechtsmeier 4 participants 18 messages Oct 17, 2011 – Dec 19, 2011

Subsystems (2)
Arm (32-bit) USB
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Stefan Herbrechtsmeier

author
#0 lore raw

PATCH 1/5 pxa: fix usb host register mismatch

Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Remy Bohmer <[email protected]>
---
 arch/arm/cpu/pxa/usb.c                   |    2 +-
 arch/arm/include/asm/arch-pxa/pxa-regs.h |    2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)
arch/arm/cpu/pxa/usb.c +1 -1
index 0311d5e..7f78ab7 100644
@@ -72,7 +72,7 @@ int usb_cpu_stop(void)
 	udelay(11);
 	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
+	writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
 	udelay(10);
 
 #if defined(CONFIG_CPU_MONAHANS)
arch/arm/include/asm/arch-pxa/pxa-regs.h +2 -0
index 109fdc0..a4d50a7 100644
@@ -946,6 +946,8 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UHCHIE		0x4C000068
 #define UHCHIT		0x4C00006C
 
+#define UHCCOMS_HCR	(1<<0)
+
 #define UHCHR_FSBIR	(1<<0)
 #define UHCHR_FHR	(1<<1)
 #define UHCHR_CGR	(1<<2)
Signature · 1 line
1.7.0.4
author
#1 lore raw

PATCH 2/5 pxa: activate the first usb host port on pxa27x by default

The pxa27x has 3 usb host ports. Activate all by default.

Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Remy Bohmer <[email protected]>
---
 arch/arm/cpu/pxa/usb.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/pxa/usb.c +2 -2
index 7f78ab7..9cc454d 100644
@@ -55,7 +55,7 @@ int usb_cpu_init(void)
 	while (readl(UHCHR) & UHCHR_FSBIR)
 		udelay(1);
 
-#if defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
 	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
 #endif
 #if defined(CONFIG_PXA27X)

@@ -75,7 +75,7 @@ int usb_cpu_stop(void)
 	writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
 	udelay(10);
 
-#if defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
 	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
 #endif
 #if defined(CONFIG_PXA27X)
Signature · 1 line
1.7.0.4
author
#3 lore raw

PATCH 3/5 pxa: convert pxa27x_udc to use read and write functions

In reply to Stefan Herbrechtsmeier
Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Remy Bohmer <[email protected]>
---
 arch/arm/include/asm/arch-pxa/pxa-regs.h |    8 +-
 drivers/usb/gadget/pxa27x_udc.c          |  183 ++++++++++++++++--------------
 2 files changed, 104 insertions(+), 87 deletions(-)
arch/arm/include/asm/arch-pxa/pxa-regs.h +4 -4
index a4d50a7..055dfe0 100644
@@ -756,7 +756,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCOTGICR_IEIDR		(1 << 1)	/* OTG ID Change Rising Edge Interrupt Enable */
 #define UDCOTGICR_IEIDF		(1 << 0)	/* OTG ID Change Falling Edge Interrupt Enable */
 
-#define UDCCSN(x)	__REG2(0x40600100, (x) << 2)
+#define UDCCSN(x)	(0x40600100 + ((x) << 2))
 #define UDCCSR0		0x40600100 /* UDC Control/Status register - Endpoint 0 */
 
 #define UDCCSR0_SA	(1 << 7)	/* Setup Active */

@@ -804,7 +804,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCSR_PC	(1 << 1)	/* Packet Complete */
 #define UDCCSR_FS	(1 << 0)	/* FIFO needs service */
 
-#define UDCBCN(x)	__REG2(0x40600200, (x)<<2)
+#define UDCBCN(x)	(0x40600200 + ((x) << 2))
 #define UDCBCR0         0x40600200 /* Byte Count Register - EP0 */
 #define UDCBCRA         0x40600204 /* Byte Count Register - EPA */
 #define UDCBCRB         0x40600208 /* Byte Count Register - EPB */

@@ -830,7 +830,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCBCRW         0x40600258 /* Byte Count Register - EPW */
 #define UDCBCRX         0x4060025C /* Byte Count Register - EPX */
 
-#define UDCDN(x)	__REG2(0x40600300, (x)<<2)
+#define UDCDN(x)	(0x40600300 + ((x) << 2))
 #define UDCDR0          0x40600300 /* Data Register - EP0 */
 #define UDCDRA          0x40600304 /* Data Register - EPA */
 #define UDCDRB          0x40600308 /* Data Register - EPB */

@@ -856,7 +856,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCDRW          0x40600358 /* Data Register - EPW */
 #define UDCDRX          0x4060035C /* Data Register - EPX */
 
-#define UDCCN(x)	__REG2(0x40600400, (x)<<2)
+#define UDCCN(x)	(0x40600400 + ((x) << 2))
 #define UDCCRA          0x40600404 /* Configuration register EPA */
 #define UDCCRB          0x40600408 /* Configuration register EPB */
 #define UDCCRC          0x4060040C /* Configuration register EPC */
drivers/usb/gadget/pxa27x_udc.c +100 -83

470 lines not on this page · raw message

Signature · 1 line
1.7.0.4
#4 lore raw

PATCH 3/5 pxa: convert pxa27x_udc to use read and write functions

Quoted 4 lines · Stefan Herbrechtsmeier
Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Remy Bohmer <[email protected]>

---

Hi Stefan,

this patch is awesome, I really need this one. But ...

Can you possibly convert the register definitions to struct based access ?

Like

struct pxa_usb_regs {
u32 reg1;
u32 reg2;
...
};

and then use it in the functions :

type fn()

{
	struct pxa_usb_regs regs = (struct pxa_usb_regs)0x46000000;
...
	writel(val, &regs->reg1);
}

Thanks!!

author
#5 lore raw

PATCH 3/5 pxa: convert pxa27x_udc to use read and write functions

Am 17.10.2011 19:31, schrieb Marek Vasut:

Quoted 8 lines · Stefan Herbrechtsmeier
Quoted 4 lines
Signed-off-by Stefan Herbrechtsmeier<[email protected]>
CC Marek Vasut<[email protected]>
CC Remy Bohmer<[email protected]>

---

Hi Stefan,

this patch is awesome, I really need this one. But ...

Do you plan do add support for this driver to one of the upstream boards?

Quoted 1 line

Can you possibly convert the register definitions to struct based access ?

I can do this, but then this is the only pxa driver which use a struct for this.

Regards,
Stefan

#6 lore raw

PATCH 3/5 pxa: convert pxa27x_udc to use read and write functions

In reply to Marek Vasut

Hi,

2011/10/17 Marek Vasut <[email protected]>:

Quoted 20 lines · Stefan Herbrechtsmeier
Quoted 4 lines
Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Remy Bohmer ?<[email protected]>

---

Hi Stefan,

this patch is awesome, I really need this one. But ...

Can you possibly convert the register definitions to struct based access ?

Like

struct pxa_usb_regs {
u32 reg1;
u32 reg2;
...
};

Quoted 8 lines

and then use it in the functions :

type fn()
{
? ? ? ?struct pxa_usb_regs regs = (struct pxa_usb_regs)0x46000000;
...
? ? ? ?writel(val, &regs->reg1);
}

I agree with this remark, but I think this should be done in a different patch.

So, I applied it to u-boot-usb as-is.

Kind regards,

Remy

#7 lore raw

PATCH 1/1 drivers/usb/gadget/pxa27x_udc.c: Coding Style cleanup

In reply to Stefan Herbrechtsmeier

Commit bdbcdc89 "pxa: convert pxa27x_udc to use read and write functions" added a number of C++ comments. Fix these.

Signed-off-by Wolfgang Denk <[email protected]>
---
 drivers/usb/gadget/pxa27x_udc.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)
drivers/usb/gadget/pxa27x_udc.c +2 -3
index 0d3a988..4c00081 100644
@@ -195,12 +195,12 @@ static int udc_read_urb_ep0(void)
 
 	for (i = 0; i < w; i++) {
 		data32[ep0_urb->actual_length / 4 + i] = readl(UDCDN(0));
-//		ep0_urb->actual_length += 4;
+		/* ep0_urb->actual_length += 4; */
 	}
 
 	for (i = 0; i < b; i++) {
 		data8[ep0_urb->actual_length + w * 4 + i] = readb(UDCDN(0));
-//		ep0_urb->actual_length++;
+		/* ep0_urb->actual_length++; */
 	}
 
 	ep0_urb->actual_length += n;

@@ -599,7 +599,6 @@ void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
 
 	writel(tmp, UDCCN(ep_num));
 
-	//usbdbg
 	usbdbg("UDCCR%c = %x", 'A' + ep_num-1, readl(UDCCN(ep_num)));
 	usbdbg("UDCCSR%c = %x", 'A' + ep_num-1, readl(UDCCSN(ep_num)));
 }
Signature · 1 line
1.7.7.4
Applied
#8 lore raw

PATCH 1/1 drivers/usb/gadget/pxa27x_udc.c: Coding Style cleanup

Dear Wolfgang Denk,

Quoted 7 lines · In message <[email protected]> you wrote:

Commit bdbcdc89 "pxa: convert pxa27x_udc to use read and write functions" added a number of C++ comments. Fix these.

Signed-off-by Wolfgang Denk <[email protected]>
---
 drivers/usb/gadget/pxa27x_udc.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Let's say the docs present a simplified view of reality...    :-)
                      - Larry Wall in  <[email protected]>
author
#9 lore raw

PATCH 4/5 usbtty: init endpoints prior to startup events

In reply to Stefan Herbrechtsmeier

On some usb device controllers (pxa) the endpoint configuration must be programmed prior to enable it.

Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Remy Bohmer <[email protected]>
---
 drivers/serial/usbtty.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
drivers/serial/usbtty.c +2 -2
index cffd5a2..e2e87fe 100644
@@ -554,11 +554,11 @@ int drv_usbtty_init (void)
 	usbtty_init_strings ();
 	usbtty_init_instances ();
 
+	usbtty_init_endpoints ();
+
 	udc_startup_events (device_instance);/* Enable dev, init udc pointers */
 	udc_connect ();		/* Enable pullup for host detection */
 
-	usbtty_init_endpoints ();
-
 	/* Device initialization */
 	memset (&usbttydev, 0, sizeof (usbttydev));
Signature · 1 line
1.7.0.4
#10 lore raw

PATCH 4/5 usbtty: init endpoints prior to startup events

Hi,

2011/10/17 Stefan Herbrechtsmeier <[email protected]>:

Quoted 8 lines

On some usb device controllers (pxa) the endpoint configuration must be programmed prior to enable it.

Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Remy Bohmer ?<[email protected]>

---
?drivers/serial/usbtty.c | ? ?4 ++--
?1 files changed, 2 insertions(+), 2 deletions(-)

Applied to u-boot-usb

Kind regards,

Remy

author
#11 lore raw

PATCH 4/5 usbtty: init endpoints prior to startup events

Am 26.11.2011 23:25, schrieb Remy Bohmer:

Quoted 10 lines

2011/10/17 Stefan Herbrechtsmeier<[email protected]>:

Quoted 8 lines

On some usb device controllers (pxa) the endpoint configuration must be programmed prior to enable it.

Signed-off-by Stefan Herbrechtsmeier<[email protected]>
CC Marek Vasut<[email protected]>
CC Remy Bohmer<[email protected]>
---
  drivers/serial/usbtty.c |    4 ++--
  1 files changed, 2 insertions(+), 2 deletions(-)

Applied to u-boot-usb

I was surprised that the patch was applied without comments as it change the usbtty core
behaviour and has the possibility to break other drivers.

Should I CC the affected driver and board maintainer to hopefully get some feedback?

Regards,
Stefan

#12 lore raw

PATCH 4/5 usbtty: init endpoints prior to startup events

Hi Stefan,

2011/11/28 Stefan Herbrechtsmeier <[email protected]>:

Quoted 14 lines

Am 26.11.2011 23:25, schrieb Remy Bohmer:

Quoted 12 lines

2011/10/17 Stefan Herbrechtsmeier<[email protected]>:

Quoted 10 lines

On some usb device controllers (pxa) the endpoint configuration must be programmed prior to enable it.

Signed-off-by Stefan Herbrechtsmeier<[email protected]>
CC Marek Vasut<[email protected]>
CC Remy Bohmer<[email protected]>

---
?drivers/serial/usbtty.c | ? ?4 ++--
?1 files changed, 2 insertions(+), 2 deletions(-)

Quoted 5 lines
Quoted 1 line

Applied to u-boot-usb

I was surprised that the patch was applied without comments as it change the usbtty core
behaviour and has the possibility to break other drivers.

I was not really surprised ;-)
Looking at the code it seemed to me that it was indeed cleaner to initialize the endpoints before enabling them.
That you have problems on your board confirmed that. So, to me this was a plain bugfix.

Quoted 2 lines

Should I CC the affected driver and board maintainer to hopefully get some feedback?

This would not harm at all. I did not ask Wolfgang to pull the u-boot-usb tree yet, so it is not in mainline yet.
I need to do some more testing on the current u-boot-usb tree as well. So, if more people look at it, it would be a good thing.

Kind regards,

Remy

author
#13 lore raw

PATCH 4/5 usbtty: init endpoints prior to startup events

Am 30.11.2011 22:21, schrieb Remy Bohmer:

Quoted 14 lines

2011/11/28 Stefan Herbrechtsmeier<[email protected]>:

Quoted 13 lines

Am 26.11.2011 23:25, schrieb Remy Bohmer:

Quoted 11 lines

2011/10/17 Stefan Herbrechtsmeier<[email protected]>:

Quoted 9 lines

On some usb device controllers (pxa) the endpoint configuration must be programmed prior to enable it.

Signed-off-by Stefan Herbrechtsmeier<[email protected]>
CC Marek Vasut<[email protected]>
CC Remy Bohmer<[email protected]>
---
  drivers/serial/usbtty.c |    4 ++--
  1 files changed, 2 insertions(+), 2 deletions(-)

Applied to u-boot-usb

Quoted 8 lines
Quoted 3 lines

I was surprised that the patch was applied without comments as it change the usbtty core
behaviour and has the possibility to break other drivers.

I was not really surprised ;-)
Looking at the code it seemed to me that it was indeed cleaner to initialize the endpoints before enabling them.
That you have problems on your board confirmed that. So, to me this was a plain bugfix.

Ideally the change should not break other boards, as udc_setup_ep in usbtty_init_endpoints
is already used before udc_startup_events in usbtty_init_instances.

Quoted 6 lines
Quoted 2 lines

Should I CC the affected driver and board maintainer to hopefully get some feedback?

This would not harm at all. I did not ask Wolfgang to pull the u-boot-usb tree yet, so it is not in mainline yet.
I need to do some more testing on the current u-boot-usb tree as well. So, if more people look at it, it would be a good thing.

I have cc the maintainer and / or author of the USB related changes for the Adder (mpc8xx_udc) and SX1 (omap1510_udc),
the custodian of the omap and davinci (musb_udc)
and the maintainer of the spear boards (spr_udc).

It would be nice if the affected people could confirm, that the change don't break there
USB device support.

Kindly regards,
Stefan

author
#14 lore raw

PATCH 5/5 pxa: fix relocation

In reply to Stefan Herbrechtsmeier

The current relocation don't work correct, as it doesn't clear the initial ram (dcache) after relocation. This leads to missing bootargs during Linux boot. Additionally the current relocation use the sdram address for the initial ram which introduce a bug in the sdram initialization.

This patch extend the relocation in order to disable the mmu and to clear the dcache after the relocation. Additionally it makes the initial ram address and size configurable and fix the various CONFIG_SYS_INIT_SP_ADDR definitions in the pxa board config files.

Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Prakash Kumar <[email protected]>
CC Robert Schwebel <[email protected]>
CC Cliff Brake <[email protected]>
CC Stefano Babic <[email protected]>
---
 arch/arm/cpu/pxa/start.S         |   38 ++++++++++++++++++++++++++++----------
 include/configs/balloon3.h       |    7 +++++--
 include/configs/cerf250.h        |    6 +++++-
 include/configs/colibri_pxa270.h |    6 +++++-
 include/configs/cradle.h         |    6 +++++-
 include/configs/csb226.h         |    6 +++++-
 include/configs/innokom.h        |    6 +++++-
 include/configs/lubbock.h        |    6 +++++-
 include/configs/palmld.h         |    6 +++++-
 include/configs/palmtc.h         |    6 +++++-
 include/configs/pleb2.h          |    6 +++++-
 include/configs/pxa255_idp.h     |    6 +++++-
 include/configs/trizepsiv.h      |    6 +++++-
 include/configs/vpac270.h        |    7 +++++--
 include/configs/xaeniax.h        |    6 +++++-
 include/configs/xm250.h          |    6 +++++-
 include/configs/zipitz2.h        |    6 +++++-
 17 files changed, 108 insertions(+), 28 deletions(-)
arch/arm/cpu/pxa/start.S +28 -10
index 6191a73..2a2d722 100644
@@ -185,7 +185,7 @@ reset:
 
 	/* Flush TLB */
 	mcr	p15, 0, r0, c8, c7, 0
-	/* Allocate 4096 bytes of Dcache as RAM */
+	/* Allocate CONFIG_SYS_INIT_RAM_SIZE bytes of Dcache as RAM */
 
 	/* Drain pending loads and stores */
 	mcr	p15, 0, r0, c7, c10, 4

@@ -196,9 +196,9 @@ reset:
 	mcr	p15, 0, r0, c9, c2, 0
 	CPWAIT	r0
 
-	/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
-	mov	r0, #128
-	mov	r1, #0xa0000000
+	/* lines to reserve (32bytes per cache line) */
+	ldr	r0, =(CONFIG_SYS_INIT_RAM_SIZE >> 5)
+	ldr	r1, =(CONFIG_SYS_INIT_RAM_ADDR)
 alloc:
 	mcr	p15, 0, r1, c7, c2, 5
 	/* Drain pending loads and stores */

@@ -316,6 +316,20 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
+
+disable_mmu:
+	mov	r0, #0
+	/* Flush Dcache */
+	mcr	p15, 0, r0, c7, c6, 0
+
+	/* Flush dTLB */
+	mcr	p15, 0, r0, c8, c6, 0
+
+	/* Disable MMU and DCache */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, #0x0005		/* (---- -C-M) */
+	mcr	p15, 0, r0, c1, c0, 0
+	CPWAIT	r0
 #endif	/* #ifndef CONFIG_SPL_BUILD */
 
 /*

@@ -589,18 +603,22 @@ reset_endless:
 	.align	14
 	.globl	mmu_table
 mmu_table:
-	/* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
+	/* 0x00000000 -- CONFIG_SYS_INIT_RAM_ADDR */
+	/* 1:1, uncached mapping */
 	.set	__base, 0
-	.rept	0xa00
+	.rept	CONFIG_SYS_INIT_RAM_ADDR >> 20
 	.word	(__base << 20) | 0xc12
 	.set	__base, __base + 1
 	.endr
 
-	/* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
-	.word	(0xa00 << 20) | 0x1c1e
+	/* CONFIG_SYS_INIT_RAM_ADDR -- CONFIG_SYS_INIT_RAM_ADDR + 0x100000 */
+	/* 1:1, cached mapping */
+	.word	CONFIG_SYS_INIT_RAM_ADDR | 0x1c1e
 
-	.set	__base, 0xa01
-	.rept	0x1000 - 0xa01
+	/* CONFIG_SYS_INIT_RAM_ADDR + 0x100000 -- 0x100000000 */
+	/* 1:1, uncached mapping */
+	.set	__base, (CONFIG_SYS_INIT_RAM_ADDR >> 20) + 1
+	.rept	0x1000 - ((CONFIG_SYS_INIT_RAM_ADDR >> 20) + 1)
 	.word	(__base << 20) | 0xc12
 	.set	__base, __base + 1
 	.endr
include/configs/balloon3.h +5 -2
index b604b52..36cb896 100644
@@ -132,8 +132,11 @@
 #define	CONFIG_SYS_LOAD_ADDR		0xa1000000
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		\
-	(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * NOR FLASH
include/configs/cerf250.h +5 -1
index be325e8..1fe34d8 100644
@@ -155,7 +155,11 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * GPIO settings
include/configs/colibri_pxa270.h +5 -1
index 011731b..ce3432d 100644
@@ -167,7 +167,11 @@
 #define	CONFIG_SYS_LOAD_ADDR		(0xa1000000)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * NOR FLASH
include/configs/cradle.h +5 -1
index 25be616..2ee875d 100644
@@ -138,7 +138,11 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * FLASH and environment organization
include/configs/csb226.h +5 -1
index 804469b..0fadee0 100644
@@ -180,7 +180,11 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 # if 0
 /* FIXME: switch to _documented_ registers */
include/configs/innokom.h +5 -1
index a0a3da1..0a5eba2 100644
@@ -195,7 +195,11 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * JFFS2 partitions
include/configs/lubbock.h +5 -1
index bbdae3c..fe9f711 100644
@@ -175,7 +175,11 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
include/configs/palmld.h +5 -1
index 514bcaa..0259b41 100644
@@ -156,7 +156,11 @@
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * NOR FLASH
include/configs/palmtc.h +5 -1
index bdb5f57..6ef363a 100644
@@ -157,7 +157,11 @@
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * NOR FLASH
include/configs/pleb2.h +5 -1
index 7dd6246..a9b0523 100644
@@ -174,7 +174,11 @@
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * GPIO settings
include/configs/pxa255_idp.h +5 -1
index cd95081..77edeb0 100644
@@ -291,7 +291,11 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * GPIO settings
include/configs/trizepsiv.h +5 -1
index 6ec9b80..3c38a19 100644
@@ -213,7 +213,11 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * GPIO settings
include/configs/vpac270.h +5 -2
index 9db4d99..2537704 100644
@@ -181,8 +181,11 @@
 #define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
 #define	CONFIG_SYS_IPL_LOAD_ADDR	(0x5c000000)
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		\
-	(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * NOR FLASH
include/configs/xaeniax.h +5 -1
index 8a41416..8275b70 100644
@@ -168,7 +168,11 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * FLASH and environment organization
include/configs/xm250.h +5 -1
index a35bce3..9254793 100644
@@ -175,7 +175,11 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * FLASH and environment organization
include/configs/zipitz2.h +5 -1
index ade40b5..e9c2774 100644
@@ -177,7 +177,11 @@ unsigned char zipitz2_spi_read(void);
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xc0000000	/* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000		/* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 
 /*
  * NOR FLASH
Signature · 1 line
1.7.0.4
#15 lore raw

PATCH 5/5 pxa: fix relocation

Hi,

2011/10/17 Stefan Herbrechtsmeier <[email protected]>:

Quoted 11 lines

The current relocation don't work correct, as it doesn't clear the initial ram (dcache) after relocation. This leads to missing bootargs during Linux boot. Additionally the current relocation use the sdram address for the initial ram which introduce a bug in the sdram initialization.

This patch extend the relocation in order to disable the mmu and to clear the dcache after the relocation. Additionally it makes the initial ram address and size configurable and fix the various CONFIG_SYS_INIT_SP_ADDR definitions in the pxa board config files.

Quoted 6 lines
Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Prakash Kumar <[email protected]>
CC Robert Schwebel <[email protected]>
CC Cliff Brake <[email protected]>
CC Stefano Babic <[email protected]>

I see that nobody picked this is up so far, and I will not do it as well... It is posted as part of a series with USB patches, while this one is not related to USB.
So, repost it as an stand-alone patch?

Kind regards,

Remy

author
#16 lore raw

PATCH 5/5 pxa: fix relocation

Am 26.11.2011 23:27, schrieb Remy Bohmer:

Quoted 18 lines

2011/10/17 Stefan Herbrechtsmeier<[email protected]>:

Quoted 11 lines

The current relocation don't work correct, as it doesn't clear the initial ram (dcache) after relocation. This leads to missing bootargs during Linux boot. Additionally the current relocation use the sdram address for the initial ram which introduce a bug in the sdram initialization.

This patch extend the relocation in order to disable the mmu and to clear the dcache after the relocation. Additionally it makes the initial ram address and size configurable and fix the various CONFIG_SYS_INIT_SP_ADDR definitions in the pxa board config files.

Quoted 6 lines
Signed-off-by Stefan Herbrechtsmeier<[email protected]>
CC Marek Vasut<[email protected]>
CC Prakash Kumar<[email protected]>
CC Robert Schwebel<[email protected]>
CC Cliff Brake<[email protected]>
CC Stefano Babic<[email protected]>
Quoted 4 lines

I see that nobody picked this is up so far, and I will not do it as well... It is posted as part of a series with USB patches, while this one is not related to USB.
So, repost it as an stand-alone patch?

This patch was superseded by 'PXA: Rework start.S to be closer to other ARMs' from Marek.

#17 lore raw

PATCH 1/5 pxa: fix usb host register mismatch

In reply to Stefan Herbrechtsmeier

Hi

2011/10/17 Stefan Herbrechtsmeier <[email protected]>:

Quoted 7 lines
Signed-off-by Stefan Herbrechtsmeier <[email protected]>
CC Marek Vasut <[email protected]>
CC Remy Bohmer ?<[email protected]>

---
?arch/arm/cpu/pxa/usb.c ? ? ? ? ? ? ? ? ? | ? ?2 +- ?arch/arm/include/asm/arch-pxa/pxa-regs.h | ? ?2 ++ ?2 files changed, 3 insertions(+), 1 deletions(-)

Applied to u-boot-usb

Kind regards,

Remy