step towards removal of mach/system.h

index 1a347f481e..af395338db 100644
@@ -158,13 +158,11 @@ void cpu_idle_wait(void)
 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 
 /*
- * This is our default idle handler.  We need to disable
- * interrupts here to ensure we don't miss a wakeup call.
+ * This is our default idle handler.
  */
 static void default_idle(void)
 {
-	if (!need_resched())
-		arch_idle();
+	arch_idle();
 	local_irq_enable();
 }
 

@@ -191,23 +189,26 @@ void cpu_idle(void)
 				cpu_die();
 #endif
 
+			/*
+			 * We need to disable interrupts here
+			 * to ensure we don't miss a wakeup call.
+			 */
 			local_irq_disable();
 			if (hlt_counter) {
 				local_irq_enable();
 				cpu_relax();
-			} else {
+			} else if (!need_resched()) {
 				stop_critical_timings();
 				if (cpuidle_idle_call())
 					pm_idle();
 				start_critical_timings();
 				/*
-				 * This will eventually be removed - pm_idle
-				 * functions should always return with IRQs
-				 * enabled.
+				 * pm_idle functions should always
+				 * return with IRQs enabled.
 				 */
 				WARN_ON(irqs_disabled());
+			} else
 				local_irq_enable();
-			}
 		}
 		leds_event(led_idle_end);
 		tick_nohz_restart_sched_tick();

index 746d6fc6d3..079b5bdadb 100644
@@ -123,9 +123,7 @@ static struct map_desc exynos4_iodesc[] __initdata = {
 
 static void exynos4_idle(void)
 {
-	if (!need_resched())
-		cpu_do_idle();
-
+	cpu_do_idle();
 	local_irq_enable();
 }
 

index 495b3987d4..c25b6b06be 100644
@@ -108,13 +108,7 @@ void omap1_pm_idle(void)
 	__u32 use_idlect1 = arm_idlect1_mask;
 	int do_sleep = 0;
 
-	local_irq_disable();
 	local_fiq_disable();
-	if (need_resched()) {
-		local_fiq_enable();
-		local_irq_enable();
-		return;
-	}
 
 #ifdef CONFIG_OMAP_MPU_TIMER
 #warning Enable 32kHz OS timer in order to allow sleep states in idle

index bf089e743e..3ada66c167 100644
@@ -277,7 +277,6 @@ static int omap2_can_sleep(void)
 
 static void omap2_pm_idle(void)
 {
-	local_irq_disable();
 	local_fiq_disable();
 
 	if (!omap2_can_sleep()) {

index 7255d9bce8..16292e5124 100644
@@ -492,13 +492,12 @@ int omap3_can_sleep(void)
 
 static void omap3_pm_idle(void)
 {
-	local_irq_disable();
 	local_fiq_disable();
 
 	if (!omap3_can_sleep())
 		goto out;
 
-	if (omap_irq_pending() || need_resched())
+	if (omap_irq_pending())
 		goto out;
 
 	trace_power_start(POWER_CSTATE, 1, smp_processor_id());

index 8a938542c5..93e8b02f7a 100644
@@ -88,14 +88,13 @@ static void s5p64x0_idle(void)
 {
 	unsigned long val;
 
-	if (!need_resched()) {
-		val = __raw_readl(S5P64X0_PWR_CFG);
-		val &= ~(0x3 << 5);
-		val |= (0x1 << 5);
-		__raw_writel(val, S5P64X0_PWR_CFG);
-
-		cpu_do_idle();
-	}
+	val = __raw_readl(S5P64X0_PWR_CFG);
+	val &= ~(0x3 << 5);
+	val |= (0x1 << 5);
+	__raw_writel(val, S5P64X0_PWR_CFG);
+
+	cpu_do_idle();
+
 	local_irq_enable();
 }
 

index fd2708e7d8..a5d42be262 100644
@@ -94,9 +94,7 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
 
 static void s5pc100_idle(void)
 {
-	if (!need_resched())
-		cpu_do_idle();
-
+	cpu_do_idle();
 	local_irq_enable();
 }
 

index 9114572082..c02adca897 100644
@@ -101,9 +101,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
 
 static void s5pv210_idle(void)
 {
-	if (!need_resched())
-		cpu_do_idle();
-
+	cpu_do_idle();
 	local_irq_enable();
 }
 

index bfc684441e..cfacd93cb7 100644
@@ -311,6 +311,13 @@ static struct at91_gpio_bank at91cap9_gpio[] = {
 	}
 };
 
+static void at91cap9_idle(void)
+{
+	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+	cpu_do_idle();
+	local_irq_enable();
+}
+
 static void at91cap9_reset(void)
 {
 	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);

@@ -333,6 +340,7 @@ static void __init at91cap9_map_io(void)
 
 static void __init at91cap9_initialize(void)
 {
+	pm_idle = at91cap9_idle;
 	at91_arch_reset = at91cap9_reset;
 	pm_power_off = at91cap9_poweroff;
 	at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);

index f73302dbc6..3eff653d69 100644
@@ -286,6 +286,16 @@ static struct at91_gpio_bank at91rm9200_gpio[] = {
 	}
 };
 
+static void at91rm9200_idle(void)
+{
+	/*
+	 * Disable the processor clock.  The processor will be automatically
+	 * re-enabled by an interrupt or by a reset.
+	 */
+	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+	local_irq_enable();
+}
+
 static void at91rm9200_reset(void)
 {
 	/*

@@ -307,6 +317,7 @@ static void __init at91rm9200_map_io(void)
 
 static void __init at91rm9200_initialize(void)
 {
+	pm_idle = at91rm9200_idle;
 	at91_arch_reset = at91rm9200_reset;
 	at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
 			| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)

index cb397be144..42892a3080 100644
@@ -315,8 +315,16 @@ static void __init at91sam9260_map_io(void)
 	}
 }
 
+static void at91sam9260_idle(void)
+{
+	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+	cpu_do_idle();
+	local_irq_enable();
+}
+
 static void __init at91sam9260_initialize(void)
 {
+	pm_idle = at91sam9260_idle;
 	at91_arch_reset = at91sam9_alt_reset;
 	pm_power_off = at91sam9260_poweroff;
 	at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)

index 6c8e3b5f66..f8ced39969 100644
@@ -284,8 +284,16 @@ static void __init at91sam9261_map_io(void)
 		at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 }
 
+static void at91sam9261_idle(void)
+{
+	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+	cpu_do_idle();
+	local_irq_enable();
+}
+
 static void __init at91sam9261_initialize(void)
 {
+	pm_idle = at91sam9261_idle;
 	at91_arch_reset = at91sam9_alt_reset;
 	pm_power_off = at91sam9261_poweroff;
 	at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)

index 044f3c927e..acf3f1e488 100644
@@ -301,8 +301,16 @@ static void __init at91sam9263_map_io(void)
 	at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
 }
 
+static void at91sam9263_idle(void)
+{
+	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+	cpu_do_idle();
+	local_irq_enable();
+}
+
 static void __init at91sam9263_initialize(void)
 {
+	pm_idle = at91sam9263_idle;
 	at91_arch_reset = at91sam9_alt_reset;
 	pm_power_off = at91sam9263_poweroff;
 	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);

index 1532b508c8..bef812d1f1 100644
@@ -302,6 +302,13 @@ static struct at91_gpio_bank at91sam9g45_gpio[] = {
 	}
 };
 
+static void at91sam9g45_idle(void)
+{
+	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+	cpu_do_idle();
+	local_irq_enable();
+}
+
 static void at91sam9g45_reset(void)
 {
 	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);

@@ -325,6 +332,7 @@ static void __init at91sam9g45_map_io(void)
 
 static void __init at91sam9g45_initialize(void)
 {
+	pm_idle = at91sam9g45_idle;
 	at91_arch_reset = at91sam9g45_reset;
 	pm_power_off = at91sam9g45_poweroff;
 	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);

index a238105d2c..4952451c8e 100644
@@ -290,8 +290,16 @@ static void __init at91sam9rl_map_io(void)
 	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
 }
 
+static void at91sam9rl_idle(void)
+{
+	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+	cpu_do_idle();
+	local_irq_enable();
+}
+
 static void __init at91sam9rl_initialize(void)
 {
+	pm_idle = at91sam9rl_idle;
 	at91_arch_reset = at91sam9_alt_reset;
 	pm_power_off = at91sam9rl_poweroff;
 	at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);

index 56ba3bd035..d6a174e155 100644
@@ -37,8 +37,19 @@ unsigned long clk_get_rate(struct clk *clk)
 	return AT91X40_MASTER_CLOCK;
 }
 
+static void at91x40_idle(void)
+{
+	/*
+	 * Disable the processor clock.  The processor will be automatically
+	 * re-enabled by an interrupt or by a reset.
+	 */
+	at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
+	cpu_do_idle();
+}
+
 void __init at91x40_initialize(unsigned long main_clock)
 {
+	pm_idle = at91x40_idle;
 	at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
 			| (1 << AT91X40_ID_IRQ2);
 }

index 36af14bc13..ed2ec8e4bc 100644
@@ -28,23 +28,7 @@
 
 static inline void arch_idle(void)
 {
-	/*
-	 * Disable the processor clock.  The processor will be automatically
-	 * re-enabled by an interrupt or by a reset.
-	 */
-#ifdef AT91_PS
-	at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
-#else
-	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-#endif
-#ifndef CONFIG_CPU_ARM920T
-	/*
-	 * Set the processor (CP15) into 'Wait for Interrupt' mode.
-	 * Post-RM9200 processors need this in conjunction with the above
-	 * to save power when idle.
-	 */
 	cpu_do_idle();
-#endif
 }
 
 void (*at91_arch_reset)(void);

new file mode 100644
index 0000000000..573071ba65
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-clps711x/idle.c
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <asm/hardware/clps7111.h>
+
+static void clps711x_idle(void)
+{
+	clps_writel(1, HALT);
+	__asm__ __volatile__(
+	"mov    r0, r0\n\
+	mov     r0, r0");
+}
+
+static int __init clps711x_idle_init(void)
+{
+	pm_idle = clps711x_idle;
+	return 0;
+}
+
+arch_initcall(clps711x_idle_init);
+

index f916cd7a47..367edfcef3 100644
@@ -26,10 +26,7 @@
 
 static inline void arch_idle(void)
 {
-	clps_writel(1, HALT);
-	__asm__ __volatile__(
-	"mov	r0, r0\n\
-	mov	r0, r0");
+	cpu_do_idle();
 }
 
 static inline void arch_reset(char mode, const char *cmd)

index d0ce8abdd4..53c6f51015 100644
@@ -271,8 +271,36 @@ static struct platform_device *ebsa110_devices[] = {
 	&am79c961_device,
 };
 
+/*
+ * EBSA110 idling methodology:
+ *
+ * We can not execute the "wait for interrupt" instruction since that
+ * will stop our MCLK signal (which provides the clock for the glue
+ * logic, and therefore the timer interrupt).
+ *
+ * Instead, we spin, polling the IRQ_STAT register for the occurrence
+ * of any interrupt with core clock down to the memory clock.
+ */
+static void ebsa110_idle(void)
+{
+	const char *irq_stat = (char *)0xff000000;
+
+	/* disable clock switching */
+	asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
+
+	/* wait for an interrupt to occur */
+	while (!*irq_stat);
+
+	/* enable clock switching */
+	asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
+
+	/* return with IRQ enabled */
+	local_irq_enable();
+}
+
 static int __init ebsa110_init(void)
 {
+	pm_idle = ebsa110_idle;
 	return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
 }
 

index 9a26245bf1..ac7bd8a74e 100644
@@ -10,28 +10,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-/*
- * EBSA110 idling methodology:
- *
- * We can not execute the "wait for interrupt" instruction since that
- * will stop our MCLK signal (which provides the clock for the glue
- * logic, and therefore the timer interrupt).
- *
- * Instead, we spin, polling the IRQ_STAT register for the occurrence
- * of any interrupt with core clock down to the memory clock.
- */
 static inline void arch_idle(void)
 {
-	const char *irq_stat = (char *)0xff000000;
-
-	/* disable clock switching */
-	asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
-
-	/* wait for an interrupt to occur */
-	while (!*irq_stat);
-
-	/* enable clock switching */
-	asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
+	cpu_do_idle();
 }
 
 #define arch_reset(mode, cmd)	cpu_reset(0x80000000)

new file mode 100644
index 0000000000..0c528f3397
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-gemini/idle.c
+ */
+
+#include <linux/init.h>
+
+static void gemini_idle(void)
+{
+	/*
+	 * Because of broken hardware we have to enable interrupts or the CPU
+	 * will never wakeup... Acctualy it is not very good to enable
+	 * interrupts first since scheduler can miss a tick, but there is
+	 * no other way around this. Platforms that needs it for power saving
+	 * should call enable_hlt() in init code, since by default it is
+	 * disabled.
+	 */
+	local_irq_enable();
+	cpu_do_idle();
+}
+
+static int __init gemini_idle_init(void)
+{
+	pm_idle = gemini_idle;
+	return 0;
+}
+
+arch_initcall(gemini_idle_init);
+

index 4d9c1f8724..20c1738060 100644
@@ -16,16 +16,6 @@
 
 static inline void arch_idle(void)
 {
-	/*
-	 * Because of broken hardware we have to enable interrupts or the CPU
-	 * will never wakeup... Acctualy it is not very good to enable
-	 * interrupts here since scheduler can miss a tick, but there is
-	 * no other way around this. Platforms that needs it for power saving
-	 * should call enable_hlt() in init code, since by default it is
-	 * disabled.
-	 */
-	local_irq_enable();
-	cpu_do_idle();
 }
 
 static inline void arch_reset(char mode, const char *cmd)

index 51d4e44ab9..f3bf3572a3 100644
@@ -242,3 +242,23 @@ void __init h720x_map_io(void)
 {
 	iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
 }
+
+static void h720x__idle(void)
+{
+	CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
+	nop();
+	nop();
+	CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
+	nop();
+	nop();
+	local_irq_enable();
+}
+
+static int __init h720x__idle_init(void)
+{
+	pm_idle = h720x__idle;
+	return 0;
+}
+
+arch_initcall(h720x_idle_init);
+

index a708d24ee4..65032f5c24 100644
@@ -16,12 +16,6 @@
 
 static void arch_idle(void)
 {
-	CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
-	nop();
-	nop();
-	CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
-	nop();
-	nop();
 }
 
 

index a1bee33d18..3fd8da956b 100644
@@ -443,4 +443,7 @@ void __init ixp23xx_sys_init(void)
 {
 	*IXP23XX_EXP_UNIT_FUSE |= 0xf;
 	platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
+
+	/* by default, the idle code is disabled */
+	disable_hlt();
 }

index 8920ff2dff..0d239f2a1c 100644
@@ -13,10 +13,6 @@
 
 static inline void arch_idle(void)
 {
-#if 0
-	if (!hlt_counter)
-		cpu_do_idle();
-#endif
 }
 
 static inline void arch_reset(char mode, const char *cmd)

index 07772575d7..b787b81fd2 100644
@@ -256,6 +256,13 @@ void __init ixp4xx_init_irq(void)
 					 handle_level_irq);
 		set_irq_flags(i, IRQF_VALID);
 	}
+
+	/*
+	 * ixp4xx does not implement the XScale PWRMODE register
+	 * ixp4xx does not implement the XScale PWRMODE registerso it must not
+	 * call cpu_do_idle().
+	 */
+	disable_hlt();
 }
 
 

index 54c0af7fa2..ce7ff3941a 100644
@@ -13,12 +13,6 @@
 
 static inline void arch_idle(void)
 {
-	/* ixp4xx does not implement the XScale PWRMODE register,
-	 * so it must not call cpu_do_idle() here.
-	 */
-#if 0
-	cpu_do_idle();
-#endif
 }
 
 

index a8cbca6701..0c394dd671 100644
@@ -19,40 +19,10 @@
 
 #include <mach/regs-clock.h>
 
-void (*s3c24xx_idle)(void);
 void (*s3c24xx_reset_hook)(void);
 
-void s3c24xx_default_idle(void)
-{
-	unsigned long tmp;
-	int i;
-
-	/* idle the system by using the idle mode which will wait for an
-	 * interrupt to happen before restarting the system.
-	 */
-
-	/* Warning: going into idle state upsets jtag scanning */
-
-	__raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
-		     S3C2410_CLKCON);
-
-	/* the samsung port seems to do a loop and then unset idle.. */
-	for (i = 0; i < 50; i++) {
-		tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
-	}
-
-	/* this bit is not cleared on re-start... */
-
-	__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
-		     S3C2410_CLKCON);
-}
-
 static void arch_idle(void)
 {
-	if (s3c24xx_idle != NULL)
-		(s3c24xx_idle)();
-	else
-		s3c24xx_default_idle();
 }
 
 #include <mach/system-reset.h>

index ef0958d3e5..c9018fbf67 100644
@@ -33,7 +33,6 @@
 #include <asm/irq.h>
 
 #include <mach/reset.h>
-#include <mach/idle.h>
 
 #include <plat/cpu-freq.h>
 

@@ -129,6 +128,7 @@ static void s3c2412_idle(void)
 	__raw_writel(tmp, S3C2412_PWRCFG);
 
 	cpu_do_idle();
+	local_irq_enable();
 }
 
 static void s3c2412_hard_reset(void)

@@ -162,7 +162,7 @@ void __init s3c2412_map_io(void)
 
 	/* set our idle function */
 
-	s3c24xx_idle = s3c2412_idle;
+	pm_idle = s3c2412_idle;
 
 	/* set custom reset hook */
 

index 494ce913dc..5b0ab08d5a 100644
@@ -45,7 +45,6 @@
 #include <asm/irq.h>
 
 #include <mach/reset.h>
-#include <mach/idle.h>
 #include <mach/regs-s3c2443-clock.h>
 
 #include <plat/gpio-core.h>

@@ -85,7 +84,6 @@ int __init s3c2416_init(void)
 	printk(KERN_INFO "S3C2416: Initializing architecture\n");
 
 	s3c24xx_reset_hook = s3c2416_hard_reset;
-	/* s3c24xx_idle = s3c2416_idle;	*/
 
 	/* change WDT IRQ number */
 	s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;

index c1fc6c6fac..21ac7de906 100644
@@ -192,6 +192,35 @@ static unsigned long s3c24xx_read_idcode_v4(void)
 	return __raw_readl(S3C2410_GSTATUS1);
 }
 
+static void s3c24xx_default_idle(void)
+{
+	unsigned long tmp;
+	int i;
+
+	/* idle the system by using the idle mode which will wait for an
+	 * interrupt to happen before restarting the system.
+	 */
+
+	/* Warning: going into idle state upsets jtag scanning */
+
+	__raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
+		     S3C2410_CLKCON);
+
+	/* the samsung port seems to do a loop and then unset idle.. */
+	for (i = 0; i < 50; i++) {
+		tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
+	}
+
+	/* this bit is not cleared on re-start... */
+
+	__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
+		     S3C2410_CLKCON);
+
+	/* return with IRQs enabled */
+	local_irq_enable();
+}
+
+
 /* Hook for arm_pm_restart to ensure we execute the reset code
  * with the caches enabled. It seems@least the S3C2440 has a problem
  * resetting if there is bus activity interrupted by the reset.

@@ -227,6 +256,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 		idcode = s3c24xx_read_idcode_v4();
 	}
 
+	pm_idle = s3c24xx_default_idle;
 	arm_pm_restart = s3c24xx_pm_restart;
 
 	s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));

index feda3ca7fc..ee235625d7 100644
@@ -150,11 +150,17 @@ static struct sys_timer shark_timer = {
 	.init		= shark_timer_init,
 };
 
+static void shark_init_irq(void)
+{
+	disable_hlt();
+}
+
 MACHINE_START(SHARK, "Shark")
 	/* Maintainer: Alexander Schulz */
 	.atag_offset	= 0x3000,
 	.map_io		= shark_map_io,
 	.init_irq	= shark_init_irq,
+	.init_machine	= shark_init_machine,
 	.timer		= &shark_timer,
 	.dma_zone_size	= SZ_4M,
 MACHINE_END

index 7a1fa6adb7..34301545e3 100644
@@ -534,5 +534,6 @@ void __init nuc900_board_init(struct platform_device **device, int size)
 	platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev));
 	spi_register_board_info(nuc900_spi_board_info,
 					ARRAY_SIZE(nuc900_spi_board_info));
+	disable_hlt();
 }
 

new file mode 100644
index 0000000000..580b4075fd
@@ -0,0 +1,31 @@
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+void mx3_idle(void)
+{
+	/* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
+	unsigned long reg = 0;
+	__asm__ __volatile__(
+	/* disable I and D cache */
+	"mrc p15, 0, %0, c1, c0, 0\n"
+	"bic %0, %0, #0x00001000\n"
+	"bic %0, %0, #0x00000004\n"
+	"mcr p15, 0, %0, c1, c0, 0\n"
+	/* invalidate I cache */
+	"mov %0, #0\n"
+	"mcr p15, 0, %0, c7, c5, 0\n"
+	/* clear and invalidate D cache */
+	"mov %0, #0\n"
+	"mcr p15, 0, %0, c7, c14, 0\n"
+	/* WFI */
+	"mov %0, #0\n"
+	"mcr p15, 0, %0, c7, c0, 4\n"
+	"nop\n" "nop\n" "nop\n" "nop\n"
+	"nop\n" "nop\n" "nop\n"
+	/* enable I and D cache */
+	"mrc p15, 0, %0, c1, c0, 0\n"
+	"orr %0, %0, #0x00001000\n"
+	"orr %0, %0, #0x00000004\n"
+	"mcr p15, 0, %0, c1, c0, 0\n"
+	: "=r" (reg));
+}

index b7c55e7db0..4855e99b2c 100644
@@ -51,6 +51,7 @@ void __init imx31_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX31);
 	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+	pm_idle = mx3_idle;
 }
 
 void __init mx31_init_irq(void)

index f49bac7a1e..f20fed6954 100644
@@ -48,6 +48,7 @@ void __init imx35_init_early(void)
 	mxc_set_cpu_type(MXC_CPU_MX35);
 	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+	pm_idle = mx3_idle;
 }
 
 void __init mx35_init_irq(void)

index f7bf996f46..c57bd92764 100644
@@ -1529,6 +1529,11 @@ static void clk_tree_init(void)
 	__raw_writel(reg, MXC_CCM_CBCDR);
 }
 
+static void mx51_idle(void)
+{
+	mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+}
+
 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 			unsigned long ckih1, unsigned long ckih2)
 {

@@ -1569,6 +1574,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 	/* System timer */
 	mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
 		MX51_MXC_INT_GPT);
+
+	pm_idle = mx51_idle;
 	return 0;
 }
 

index 51f02a9d41..89d08c51ca 100644
@@ -20,40 +20,9 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 
-extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
-
 static inline void arch_idle(void)
 {
-	/* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
-	if (cpu_is_mx31() || cpu_is_mx35()) {
-		unsigned long reg = 0;
-		__asm__ __volatile__(
-			/* disable I and D cache */
-			"mrc p15, 0, %0, c1, c0, 0\n"
-			"bic %0, %0, #0x00001000\n"
-			"bic %0, %0, #0x00000004\n"
-			"mcr p15, 0, %0, c1, c0, 0\n"
-			/* invalidate I cache */
-			"mov %0, #0\n"
-			"mcr p15, 0, %0, c7, c5, 0\n"
-			/* clear and invalidate D cache */
-			"mov %0, #0\n"
-			"mcr p15, 0, %0, c7, c14, 0\n"
-			/* WFI */
-			"mov %0, #0\n"
-			"mcr p15, 0, %0, c7, c0, 4\n"
-			"nop\n" "nop\n" "nop\n" "nop\n"
-			"nop\n" "nop\n" "nop\n"
-			/* enable I and D cache */
-			"mrc p15, 0, %0, c1, c0, 0\n"
-			"orr %0, %0, #0x00001000\n"
-			"orr %0, %0, #0x00000004\n"
-			"mcr p15, 0, %0, c1, c0, 0\n"
-			: "=r" (reg));
-	} else if (cpu_is_mx51())
-		mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-	else
-		cpu_do_idle();
+	cpu_do_idle();
 }
 
 void arch_reset(char mode, const char *cmd);

index 580b407..ac0d655 100644
@@ -28,4 +28,6 @@ void mx3_idle(void)
 	"orr %0, %0, #0x00000004\n"
 	"mcr p15, 0, %0, c1, c0, 0\n"
 	: "=r" (reg));
+
+	local_irq_enable();
 }

index c57bd92..63dc037 100644
@@ -15,12 +15,14 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/clkdev.h>
+#include <linux/pm.h>
 
 #include <asm/div64.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/clock.h>
+#include <mach/system.h>
 
 #include "crm_regs.h"
 

@@ -1532,6 +1534,8 @@ static void clk_tree_init(void)
 static void mx51_idle(void)
 {
 	mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+
+	local_irq_enable();
 }
 
 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,

index 388a407..24e61e4 100644
@@ -203,6 +203,9 @@ static inline int mx35_revision(void)
 {
 	return mx35_cpu_rev;
 }
+
+void mx3_idle(void);
+
 #endif
 
 #endif /* ifndef __MACH_MX3x_H__ */

index 89d08c5..9875cc0 100644
@@ -20,6 +20,8 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 
+extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+
 static inline void arch_idle(void)
 {
 	cpu_do_idle();