i.mx: add the initial i.mx6q core/board support

In order to support the coming MX6 platform and to reducde the duplicated code, we had better move some common files to the imx-common folder for sharing.

Signed-off-by Jason Liu <[email protected]>

---

 Makefile                                       |    7 ++
 arch/arm/cpu/armv7/imx-common/Makefile         |   47 ++++++++++
 arch/arm/cpu/armv7/imx-common/cpu_info.c       |  108 ++++++++++++++++++++++++
 arch/arm/cpu/armv7/{mx5 => imx-common}/speed.c |    0
 arch/arm/cpu/armv7/{mx5 => imx-common}/timer.c |   17 ++--
 arch/arm/cpu/armv7/mx5/Makefile                |    2 +-
 arch/arm/cpu/armv7/mx5/soc.c                   |   77 -----------------
 7 files changed, 172 insertions(+), 86 deletions(-)

+++ b/arch/arm/cpu/armv7/imx-common/cpu_info.c

arch/arm/cpu/armv7/imx-common/cpu_info.c +15 -0

@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,

Quoted 6 lines · Jason Liu

In order to support the coming MX6 platform and to reducde the duplicated code, we had better move some common files to the imx-common folder for sharing.

Signed-off-by Jason Liu <[email protected]>

---

Hi jason,

Quoted 8 lines

?Makefile ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?7 ++
?arch/arm/cpu/armv7/imx-common/Makefile ? ? ? ? | ? 47 ++++++++++
?arch/arm/cpu/armv7/imx-common/cpu_info.c ? ? ? | ?108 ++++++++++++++++++++++++
?arch/arm/cpu/armv7/{mx5 => imx-common}/speed.c | ? ?0
?arch/arm/cpu/armv7/{mx5 => imx-common}/timer.c | ? 17 ++--
?arch/arm/cpu/armv7/mx5/Makefile ? ? ? ? ? ? ? ?| ? ?2 +-
?arch/arm/cpu/armv7/mx5/soc.c ? ? ? ? ? ? ? ? ? | ? 77 -----------------

?7 files changed, 172 insertions(+), 86 deletions(-)

I agree completely to add a common directory to share code between MX5 and MX6. However, your patch mixes new code with code moved from MX5. This is at least not coherent with the commit message, where you say you are only moving files. I understand what you did, I think it is enough to extend the commit message to better explain it.

arch/arm/cpu/armv7/imx-common/cpu_info.c

Quoted 4 lines

(quoted diff) +1 -0

+#########################################################################

arch/arm/cpu/armv7/imx-common/cpu_info.c +0 -0

The name of the file is quite confusing - I am expecting to see only function to retrieve information about the revision, but there are other common functions. It is better to use another name.

Quoted 18 lines

+++ b/arch/arm/cpu/armv7/imx-common/cpu_info.c

arch/arm/cpu/armv7/imx-common/cpu_info.c +15 -0

@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,

arch/arm/cpu/armv7/imx-common/cpu_info.c line 25

Quoted 10 lines

arch/arm/cpu/armv7/imx-common/cpu_info.c +10 -0

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+

Ok - all these functions are taken from the original soc.c.

arch/arm/cpu/armv7/imx-common/timer.c

Quoted 13 lines

arch/arm/cpu/armv7/imx-common/speed.c renamed from arch/arm/cpu/armv7/mx5/speed.c +0 -0

similarity index 100%
rename from arch/arm/cpu/armv7/mx5/speed.c
rename to arch/arm/cpu/armv7/imx-common/speed.c

arch/arm/cpu/armv7/imx-common/timer.c renamed from arch/arm/cpu/armv7/mx5/timer.c +0 -0

old mode 100644
new mode 100755
similarity index 84%
rename from arch/arm/cpu/armv7/mx5/timer.c
rename to arch/arm/cpu/armv7/imx-common/timer.c
index 2544b08..98e9f4a

You mix here two things - you move the files and you change it adding new features. Split into two patches.

Best regards,
Stefano Babic

--
=====================================================================
DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
=====================================================================

Yes, agree. what about cpu.c? if you dislike, could you do me a favor to name it. :)

Quoted 3 lines

You mix here two things - you move the files and you change it adding new features. Split into two patches.

In fact, I did not do any function change. I just do the followings two changes:

- fix the checkpatch warnings with the original timer.c file in mx5 folder.
- change the CONFIG_SYS_MX5_CLK32 to CLK_32KHZ

I can add the changes to the commit message. Do I still need split into two patches?

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

Signed-off-by Jason Liu <[email protected]>

---
 arch/arm/cpu/armv7/mx6/Makefile           |   48 +
 arch/arm/cpu/armv7/mx6/clock.c            |  388 +++++++
 arch/arm/cpu/armv7/mx6/iomux-v3.c         |   76 ++
 arch/arm/cpu/armv7/mx6/lowlevel_init.S    |   60 +
 arch/arm/cpu/armv7/mx6/soc.c              |   57 +
 arch/arm/include/asm/arch-mx6/ccm_regs.h  |  894 +++++++++++++++
 arch/arm/include/asm/arch-mx6/clock.h     |   50 +
 arch/arm/include/asm/arch-mx6/gpio.h      |   35 +
 arch/arm/include/asm/arch-mx6/imx-regs.h  |  233 ++++
 arch/arm/include/asm/arch-mx6/iomux-v3.h  |  104 ++
 arch/arm/include/asm/arch-mx6/mx6x_pins.h | 1683
+++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 
 38 +
 12 files changed, 3666 insertions(+), 0 deletions(-)

(quoted diff) +0 -0

b/arch/arm/cpu/armv7/mx6/lowlevel_init.S new file mode 100644 index 0000000..7a03f59

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +41 -0

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * Set all MPROTx to be non-bufferable,
+ * trusted for R/W, not forced to user-mode.
+ * The PACR default values are good.
+ */
+.macro init_aips
+	ldr r0, =AIPS1_ON_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+
+	ldr r0, =AIPS2_ON_BASE_ADDR

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +9 -0

+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+	init_aips
+
+	mov pc, lr

+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (2)

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +1 -0

+#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/clock.h new file mode 100644 index 0000000..636458f

arch/arm/include/asm/arch-mx6/clock.h new file +50 -0

@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_PER_CLK,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_AXI_CLK,
+	MXC_EMI_SLOW_CLK,
+	MXC_DDR_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_ESDHC4_CLK,
+	MXC_SATA_CLK,
+	MXC_NFC_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/gpio.h new file mode 100644 index 0000000..1dc34e9

arch/arm/include/asm/arch-mx6/gpio.h new file +24 -0

@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+

Quoted 20 lines

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

Signed-off-by Jason Liu <[email protected]>

---

?arch/arm/cpu/armv7/mx6/Makefile ? ? ? ? ? | ? 48 +
?arch/arm/cpu/armv7/mx6/clock.c ? ? ? ? ? ?| ?388 +++++++
?arch/arm/cpu/armv7/mx6/iomux-v3.c ? ? ? ? | ? 76 ++
?arch/arm/cpu/armv7/mx6/lowlevel_init.S ? ?| ? 60 +
?arch/arm/cpu/armv7/mx6/soc.c ? ? ? ? ? ? ?| ? 57 +
?arch/arm/include/asm/arch-mx6/ccm_regs.h ?| ?894 +++++++++++++++
?arch/arm/include/asm/arch-mx6/clock.h ? ? | ? 50 +
?arch/arm/include/asm/arch-mx6/gpio.h ? ? ?| ? 35 +
?arch/arm/include/asm/arch-mx6/imx-regs.h ?| ?233 ++++
?arch/arm/include/asm/arch-mx6/iomux-v3.h ?| ?104 ++
?arch/arm/include/asm/arch-mx6/mx6x_pins.h | 1683

+++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | ?38 +
?12 files changed, 3666 insertions(+), 0 deletions(-)

[...]

Quoted 51 lines

(quoted diff) +0 -0

b/arch/arm/cpu/armv7/mx6/lowlevel_init.S new file mode 100644 index 0000000..7a03f59

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +45 -0

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * Set all MPROTx to be non-bufferable,
+ * trusted for R/W, not forced to user-mode.
+ * The PACR default values are good.
+ */
+.macro init_aips
+ ? ? ldr r0, =AIPS1_ON_BASE_ADDR
+ ? ? ldr r1, =0x77777777
+ ? ? str r1, [r0, #0x0]
+ ? ? str r1, [r0, #0x4]
+ ? ? ldr r1, =0x0
+ ? ? str r1, [r0, #0x40]
+ ? ? str r1, [r0, #0x44]
+ ? ? str r1, [r0, #0x48]
+ ? ? str r1, [r0, #0x4C]
+ ? ? str r1, [r0, #0x50]
+
+ ? ? ldr r0, =AIPS2_ON_BASE_ADDR
+ ? ? ldr r1, =0x77777777
+ ? ? str r1, [r0, #0x0]
+ ? ? str r1, [r0, #0x4]
+ ? ? ldr r1, =0x0

arch/arm/cpu/armv7/mx6/lowlevel_init.S line 51

Quoted 6 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +6 -0

+ ? ? str r1, [r0, #0x40]
+ ? ? str r1, [r0, #0x44]
+ ? ? str r1, [r0, #0x48]
+ ? ? str r1, [r0, #0x4C]
+ ? ? str r1, [r0, #0x50]
+.endm /* init_aips */

Can't this be done in C code? Why the assembly ?

Quoted 10 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +9 -0

+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+ ? ? init_aips
+
+ ? ? mov pc, lr

[...]

Quoted 1 line

+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET ? ? ? ? ? ?(2)

Drop parenthesis around stuff similar to this.

Quoted 87 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +1 -0

+#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/clock.h new file mode 100644 index 0000000..636458f

arch/arm/include/asm/arch-mx6/clock.h new file +50 -0

@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+ ? ? MXC_ARM_CLK = 0,
+ ? ? MXC_PER_CLK,
+ ? ? MXC_AHB_CLK,
+ ? ? MXC_IPG_CLK,
+ ? ? MXC_IPG_PERCLK,
+ ? ? MXC_UART_CLK,
+ ? ? MXC_CSPI_CLK,
+ ? ? MXC_AXI_CLK,
+ ? ? MXC_EMI_SLOW_CLK,
+ ? ? MXC_DDR_CLK,
+ ? ? MXC_ESDHC_CLK,
+ ? ? MXC_ESDHC2_CLK,
+ ? ? MXC_ESDHC3_CLK,
+ ? ? MXC_ESDHC4_CLK,
+ ? ? MXC_SATA_CLK,
+ ? ? MXC_NFC_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/gpio.h new file mode 100644 index 0000000..1dc34e9

arch/arm/include/asm/arch-mx6/gpio.h new file +23 -0

@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+

arch/arm/include/asm/arch-mx6/gpio.h line 34

Quoted 7 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +7 -0

+/* GPIO registers */
+struct gpio_regs {
+ ? ? u32 ? ? gpio_dr;
+ ? ? u32 ? ? gpio_dir;
+ ? ? u32 ? ? gpio_psr;
+};
+

You'll have GPIO driver, so why expose this structure ?

arch/arm/include/asm/arch-mx6/gpio.h line 31

Quoted 2 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +1 -0

+#endif

M

Quoted 73 lines

Quoted 19 lines

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

Signed-off-by Jason Liu <[email protected]>

---
 arch/arm/cpu/armv7/mx6/Makefile           |   48 +
 arch/arm/cpu/armv7/mx6/clock.c            |  388 +++++++
 arch/arm/cpu/armv7/mx6/iomux-v3.c         |   76 ++
 arch/arm/cpu/armv7/mx6/lowlevel_init.S    |   60 +
 arch/arm/cpu/armv7/mx6/soc.c              |   57 +
 arch/arm/include/asm/arch-mx6/ccm_regs.h  |  894 +++++++++++++++
 arch/arm/include/asm/arch-mx6/clock.h     |   50 +
 arch/arm/include/asm/arch-mx6/gpio.h      |   35 +
 arch/arm/include/asm/arch-mx6/imx-regs.h  |  233 ++++
 arch/arm/include/asm/arch-mx6/iomux-v3.h  |  104 ++
 arch/arm/include/asm/arch-mx6/mx6x_pins.h | 1683
+++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h
| 38 +
 12 files changed, 3666 insertions(+), 0 deletions(-)

[...]

Quoted 51 lines

(quoted diff) +0 -0

b/arch/arm/cpu/armv7/mx6/lowlevel_init.S new file mode 100644 index 0000000..7a03f59

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +45 -0

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * Set all MPROTx to be non-bufferable,
+ * trusted for R/W, not forced to user-mode.
+ * The PACR default values are good.
+ */
+.macro init_aips
+     ldr r0, =AIPS1_ON_BASE_ADDR
+     ldr r1, =0x77777777
+     str r1, [r0, #0x0]
+     str r1, [r0, #0x4]
+     ldr r1, =0x0
+     str r1, [r0, #0x40]
+     str r1, [r0, #0x44]
+     str r1, [r0, #0x48]
+     str r1, [r0, #0x4C]
+     str r1, [r0, #0x50]
+
+     ldr r0, =AIPS2_ON_BASE_ADDR
+     ldr r1, =0x77777777
+     str r1, [r0, #0x0]
+     str r1, [r0, #0x4]
+     ldr r1, =0x0

Quoted 8 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S line 51

Quoted 6 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +6 -0

+     str r1, [r0, #0x40]
+     str r1, [r0, #0x44]
+     str r1, [r0, #0x48]
+     str r1, [r0, #0x4C]
+     str r1, [r0, #0x50]
+.endm /* init_aips */

Can't this be done in C code? Why the assembly ?

I think this should be initialized as early as possible, so I put it here.

Quoted 13 lines

Quoted 10 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +9 -0

+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+     init_aips
+
+     mov pc, lr

[...]

Quoted 3 lines

Quoted 1 line

+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (2)

Drop parenthesis around stuff similar to this.

Yes, thanks.

Quoted 87 lines

Quoted 87 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +1 -0

+#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/clock.h new file mode 100644 index 0000000..636458f

arch/arm/include/asm/arch-mx6/clock.h new file +50 -0

@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+     MXC_ARM_CLK = 0,
+     MXC_PER_CLK,
+     MXC_AHB_CLK,
+     MXC_IPG_CLK,
+     MXC_IPG_PERCLK,
+     MXC_UART_CLK,
+     MXC_CSPI_CLK,
+     MXC_AXI_CLK,
+     MXC_EMI_SLOW_CLK,
+     MXC_DDR_CLK,
+     MXC_ESDHC_CLK,
+     MXC_ESDHC2_CLK,
+     MXC_ESDHC3_CLK,
+     MXC_ESDHC4_CLK,
+     MXC_SATA_CLK,
+     MXC_NFC_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/gpio.h new file mode 100644 index 0000000..1dc34e9

arch/arm/include/asm/arch-mx6/gpio.h new file +23 -0

@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+

Quoted 9 lines

arch/arm/include/asm/arch-mx6/gpio.h line 34

Quoted 7 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +7 -0

+/* GPIO registers */
+struct gpio_regs {
+     u32     gpio_dr;
+     u32     gpio_dir;
+     u32     gpio_psr;
+};
+

You'll have GPIO driver, so why expose this structure ?

yes, we already had drivers/gpio/mxc_gpio.c driver. In this driver, we will use this structure. And it's the same as i.mx5 before.

Jason Liu

Quoted 3 lines

arch/arm/include/asm/arch-mx6/gpio.h line 31

Quoted 1 line

arch/arm/include/asm/arch-mx6/gpio.h new file +1 -0

+#endif

M

Quoted 83 lines · Marek Vasut

Quoted 81 lines

Quoted 19 lines

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

Signed-off-by Jason Liu <[email protected]>

---

?arch/arm/cpu/armv7/mx6/Makefile ? ? ? ? ? | ? 48 +
?arch/arm/cpu/armv7/mx6/clock.c ? ? ? ? ? ?| ?388 +++++++
?arch/arm/cpu/armv7/mx6/iomux-v3.c ? ? ? ? | ? 76 ++
?arch/arm/cpu/armv7/mx6/lowlevel_init.S ? ?| ? 60 +
?arch/arm/cpu/armv7/mx6/soc.c ? ? ? ? ? ? ?| ? 57 +
?arch/arm/include/asm/arch-mx6/ccm_regs.h ?| ?894 +++++++++++++++
?arch/arm/include/asm/arch-mx6/clock.h ? ? | ? 50 +
?arch/arm/include/asm/arch-mx6/gpio.h ? ? ?| ? 35 +
?arch/arm/include/asm/arch-mx6/imx-regs.h ?| ?233 ++++
?arch/arm/include/asm/arch-mx6/iomux-v3.h ?| ?104 ++
?arch/arm/include/asm/arch-mx6/mx6x_pins.h | 1683

+++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 38 +
?12 files changed, 3666 insertions(+), 0 deletions(-)

[...]

Quoted 47 lines

(quoted diff) +0 -0

b/arch/arm/cpu/armv7/mx6/lowlevel_init.S new file mode 100644 index 0000000..7a03f59

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +41 -0

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * Set all MPROTx to be non-bufferable,
+ * trusted for R/W, not forced to user-mode.
+ * The PACR default values are good.
+ */
+.macro init_aips
+ ? ? ldr r0, =AIPS1_ON_BASE_ADDR
+ ? ? ldr r1, =0x77777777
+ ? ? str r1, [r0, #0x0]
+ ? ? str r1, [r0, #0x4]
+ ? ? ldr r1, =0x0
+ ? ? str r1, [r0, #0x40]
+ ? ? str r1, [r0, #0x44]
+ ? ? str r1, [r0, #0x48]
+ ? ? str r1, [r0, #0x4C]
+ ? ? str r1, [r0, #0x50]
+
+ ? ? ldr r0, =AIPS2_ON_BASE_ADDR

arch/arm/cpu/armv7/mx6/lowlevel_init.S line 51

Quoted 10 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +10 -0

+ ? ? ldr r1, =0x77777777
+ ? ? str r1, [r0, #0x0]
+ ? ? str r1, [r0, #0x4]
+ ? ? ldr r1, =0x0
+ ? ? str r1, [r0, #0x40]
+ ? ? str r1, [r0, #0x44]
+ ? ? str r1, [r0, #0x48]
+ ? ? str r1, [r0, #0x4C]
+ ? ? str r1, [r0, #0x50]
+.endm /* init_aips */

Can't this be done in C code? Why the assembly ?

Quoted 1 line

I think this should be initialized as early as possible, so I put it here.

As early as arch_cpu_init is late (see arch/arm/lib/board.c)?

Quoted 116 lines

Quoted 13 lines

Quoted 10 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +9 -0

+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+ ? ? init_aips
+
+ ? ? mov pc, lr

[...]

Quoted 3 lines

Quoted 1 line

+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET ? ? ? ? ? ?(2)

Drop parenthesis around stuff similar to this.

Yes, thanks.

Quoted 96 lines

Quoted 84 lines

arch/arm/cpu/armv7/mx6/lowlevel_init.S new file +1 -0

+#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/clock.h new file mode 100644 index 0000000..636458f

arch/arm/include/asm/arch-mx6/clock.h new file +50 -0

@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+ ? ? MXC_ARM_CLK = 0,
+ ? ? MXC_PER_CLK,
+ ? ? MXC_AHB_CLK,
+ ? ? MXC_IPG_CLK,
+ ? ? MXC_IPG_PERCLK,
+ ? ? MXC_UART_CLK,
+ ? ? MXC_CSPI_CLK,
+ ? ? MXC_AXI_CLK,
+ ? ? MXC_EMI_SLOW_CLK,
+ ? ? MXC_DDR_CLK,
+ ? ? MXC_ESDHC_CLK,
+ ? ? MXC_ESDHC2_CLK,
+ ? ? MXC_ESDHC3_CLK,
+ ? ? MXC_ESDHC4_CLK,
+ ? ? MXC_SATA_CLK,
+ ? ? MXC_NFC_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-mx6/gpio.h new file mode 100644 index 0000000..1dc34e9

arch/arm/include/asm/arch-mx6/gpio.h new file +21 -0

@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA

arch/arm/include/asm/arch-mx6/gpio.h line 34

Quoted 10 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +9 -0

+ */
+
 
+/* GPIO registers */
+struct gpio_regs {
+ ? ? u32 ? ? gpio_dr;
+ ? ? u32 ? ? gpio_dir;
+ ? ? u32 ? ? gpio_psr;
+};
+

You'll have GPIO driver, so why expose this structure ?

Quoted 2 lines

yes, we already had drivers/gpio/mxc_gpio.c driver. In this driver, we will use this structure. And it's the same as i.mx5 before.

So why do you need to expose the structure, isn't it internal to the driver?

Quoted 7 lines

Jason Liu

Quoted 3 lines

Quoted 1 line

+#endif

M

Quoted 4 lines

Quoted 2 lines

yes, we already had drivers/gpio/mxc_gpio.c driver. In this driver, we will use this structure. And it's the same as i.mx5 before.

So why do you need to expose the structure, isn't it internal to the driver?

Yes, it's internal to the gpio driver, but, all the soc does not have the same gpio_regs layout,
so we put it here in order to have multiple #ifdef. Stefano, any comments for this?

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

Signed-off-by Jason Liu <[email protected]>

---
 arch/arm/cpu/armv7/mx6/Makefile           |   48 +
 arch/arm/cpu/armv7/mx6/clock.c            |  388 +++++++
 arch/arm/cpu/armv7/mx6/iomux-v3.c         |   76 ++
 arch/arm/cpu/armv7/mx6/lowlevel_init.S    |   60 +
 arch/arm/cpu/armv7/mx6/soc.c              |   57 +
 arch/arm/include/asm/arch-mx6/ccm_regs.h  |  894 +++++++++++++++
 arch/arm/include/asm/arch-mx6/clock.h     |   50 +
 arch/arm/include/asm/arch-mx6/gpio.h      |   35 +
 arch/arm/include/asm/arch-mx6/imx-regs.h  |  233 ++++
 arch/arm/include/asm/arch-mx6/iomux-v3.h  |  104 ++
 arch/arm/include/asm/arch-mx6/mx6x_pins.h | 1683 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/sys_proto.h |   38 +
 12 files changed, 3666 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/mx6/Makefile new file +48 -0

new file mode 100644
index 0000000..b0da028
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	= soc.o clock.o iomux-v3.o
+SOBJS   = lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/armv7/mx6/clock.c new file +293 -0

new file mode 100644
index 0000000..e0d9c6f
@@ -0,0 +1,388 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/clock.h>
+
+enum pll_clocks {
+	PLL_SYS,	/* System PLL */
+	PLL_BUS,	/* System Bus PLL*/
+	PLL_USBOTG,	/* OTG USB PLL */
+	PLL_ENET,	/* ENET PLL */
+};
+
+struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
+
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+	u32 div;
+
+	switch (pll) {
+	case PLL_SYS:
+		div = __raw_readl(&imx_ccm->analog_pll_sys);
+		div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
+
+		return infreq * (div >> 1);
+	case PLL_BUS:
+		div = __raw_readl(&imx_ccm->analog_pll_528);
+		div &= BM_ANADIG_PLL_528_DIV_SELECT;
+
+		return infreq * (20 + (div << 1));
+	case PLL_USBOTG:
+		div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
+                div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
+
+		return infreq * (20 + (div << 1));
+	case PLL_ENET:
+		div = __raw_readl(&imx_ccm->analog_pll_enet);
+		div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
+
+		return (div == 3 ? 125000000 : 25000000 * (div << 1));
+	default:
+		return 0;
+	}
+	/* NOTREACHED */
+}
+
+static u32 get_mcu_main_clk(void)
+{
+	u32 reg, freq;
+
+	reg = __raw_readl(&imx_ccm->cacrr);
+	reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
+	reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
+	freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+
+	return freq / (reg + 1);
+}
+
+static u32 get_periph_clk(void)
+{
+	u32 reg, freq = 0;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+		reg = __raw_readl(&imx_ccm->cbcmr);
+		reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
+		reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
+
+		switch (reg) {
+		case 0:
+			freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+			break;
+		case 1:
+		case 2:
+			freq = CONFIG_SYS_MX6_HCLK;
+			break;
+		default:
+			break;
+		}
+	} else {
+		reg = __raw_readl(&imx_ccm->cbcmr);
+		reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
+		reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
+
+		switch (reg) {
+		case 0:
+			freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+			break;
+		case 1:
+			freq = PLL2_PFD2_FREQ;
+			break;
+		case 2:
+			freq = PLL2_PFD0_FREQ;
+			break;
+		case 3:
+			freq = PLL2_PFD2_DIV_FREQ;
+			break;
+		default:
+			break;
+		}
+	}
+
+	return freq;
+}
+
+
+static u32 get_ahb_clk(void)
+{
+	u32 reg, ahb_podf;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+	return get_periph_clk() / (ahb_podf + 1);
+}
+
+static u32 get_ipg_clk(void)
+{
+	u32 reg, ipg_podf;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
+	ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+
+	return get_ahb_clk() / (ipg_podf + 1);
+}
+
+static u32 get_ipg_per_clk(void)
+{
+	u32 reg, perclk_podf;
+
+	reg = __raw_readl(&imx_ccm->cscmr1);
+	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
+
+	return get_ipg_clk() / (perclk_podf + 1);
+}
+
+static u32 get_uart_clk(void)
+{
+	u32 reg, uart_podf;
+
+	reg = __raw_readl(&imx_ccm->cscdr1);
+	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
+	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+
+	return PLL3_80M / (uart_podf + 1);
+}
+
+
+static u32 get_cspi_clk(void)
+{
+	u32 reg, cspi_podf;
+
+	reg = __raw_readl(&imx_ccm->cscdr2);
+	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
+	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+	return	PLL3_60M / (cspi_podf + 1);
+}
+
+static u32 get_axi_clk(void)
+{
+	u32 root_freq, axi_podf;
+	u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
+
+	axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
+	axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
+
+	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
+		if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
+			root_freq = PLL2_PFD2_FREQ;
+		else
+			root_freq = PLL3_PFD1_FREQ;;
+	} else
+		root_freq = get_periph_clk();
+
+	return  root_freq / (axi_podf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+	u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
+
+	cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
+	emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
+	emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
+	emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
+	emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
+
+	switch (emi_clk_sel) {
+	case 0:
+		root_freq = get_axi_clk();
+		break;
+	case 1:
+		root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+		break;
+	case 2:
+		root_freq = PLL2_PFD2_FREQ;
+		break;
+	case 3:
+		root_freq = PLL2_PFD0_FREQ;
+		break;
+	}
+
+	return root_freq / (emi_slow_pof + 1);
+}
+
+static u32 get_mmdc_ch0_clk(void)
+{
+	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+
+	return get_periph_clk() / (mmdc_ch0_podf + 1);
+}
+
+static u32 get_usdhc1_clk(void)
+{
+	u32 root_freq = 0;
+	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+	u32 usdhc1_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
+				MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
+
+	if (cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL)
+		root_freq = PLL2_PFD0_FREQ;
+	else
+		root_freq = PLL2_PFD2_FREQ;
+
+	return root_freq / (usdhc1_podf + 1);
+}
+
+static u32 get_usdhc2_clk(void)
+{
+	u32 root_freq = 0;
+	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+	u32 usdhc2_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
+				MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
+
+	if (cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL)
+		root_freq = PLL2_PFD0_FREQ;
+	else
+		root_freq = PLL2_PFD2_FREQ;
+
+	return root_freq / (usdhc2_podf + 1);
+}
+
+static u32 get_usdhc3_clk(void)
+{
+	u32 root_freq = 0;
+	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+	u32 usdhc3_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
+				MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
+
+	if (cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL)
+		root_freq = PLL2_PFD0_FREQ;
+	else
+		root_freq = PLL2_PFD2_FREQ;
+
+	return root_freq / (usdhc3_podf + 1);
+}
+
+static u32 get_usdhc4_clk(void)
+{
+	u32 root_freq = 0;
+	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);

arch/arm/cpu/armv7/mx6/iomux-v3.c new file +83 -0

new file mode 100644
index 0000000..ff934ea
@@ -0,0 +1,76 @@
+/*
+ * Based on the iomux-v3.c from Linux kernel:
+ * Copyright (C) 2008 by Sascha Hauer <[email protected]>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                       <[email protected]>
+ *
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/arch/iomux-v3.h>
+
+static void *base;
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+{
+	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+	u32 sel_input_ofs =
+		(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+	u32 sel_input =
+		(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+	u32 pad_ctrl_ofs =
+		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+	if (mux_ctrl_ofs)
+		__raw_writel(mux_mode, base + mux_ctrl_ofs);
+
+	if (sel_input_ofs)
+		__raw_writel(sel_input, base + sel_input_ofs);
+
+	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+
+	return 0;
+}
+
+int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+{
+	iomux_v3_cfg_t *p = pad_list;
+	int i;
+	int ret;
+
+	for (i = 0; i < count; i++) {
+		ret = imx_iomux_v3_setup_pad(*p);
+		if (ret)
+			return ret;
+		p++;
+	}
+	return 0;
+}
+
+void imx_iomux_v3_init(void *iomux_v3_base)
+{
+	base = iomux_v3_base;
+}
 
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(unsigned char *mac)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[4];
+	struct fuse_bank4_regs *fuse =
+			(struct fuse_bank4_regs *)bank->fuse_regs;

arch/arm/cpu/armv7/mx6/iomux-v3.c new file +1 -0

+#endif

arch/arm/include/asm/arch-mx6/ccm_regs.h new file +49 -0

new file mode 100644
index 0000000..e8f0a93
@@ -0,0 +1,894 @@
+/*
+ * Freescale ANADIG Register Definitions
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+
+struct imx_ccm_reg {
+	u32 ccr;	/* 0x0000 */
+	u32 ccdr;
+	u32 csr;
+	u32 ccsr;
+	u32 cacrr;	/* 0x0010*/
+	u32 cbcdr;
+	u32 cbcmr;
+	u32 cscmr1;
+	u32 cscmr2;	/* 0x0020 */
+	u32 cscdr1;
+	u32 cs1cdr;
+	u32 cs2cdr;
+	u32 cdcdr;	/* 0x0030 */
+	u32 chscdr;
+	u32 cscdr2;
+	u32 cscdr3;
+	u32 cscdr4;	/* 0x0040 */
+	u32 resv0;
+	u32 cdhipr;
+	u32 cdcr;
+	u32 ctor;	/* 0x0050 */
+	u32 clpcr;
+	u32 cisr;
+	u32 cimr;

arch/arm/include/asm/arch-mx6/gpio.h new file +25 -0

new file mode 100644
index 0000000..1dc34e9
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_MX5_GPIO_H

Quoted 378 lines · Jason Liu

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

Signed-off-by Jason Liu <[email protected]>

---

?arch/arm/cpu/armv7/mx6/Makefile ? ? ? ? ? | ? 48 +
?arch/arm/cpu/armv7/mx6/clock.c ? ? ? ? ? ?| ?388 +++++++
?arch/arm/cpu/armv7/mx6/iomux-v3.c ? ? ? ? | ? 76 ++
?arch/arm/cpu/armv7/mx6/lowlevel_init.S ? ?| ? 60 +
?arch/arm/cpu/armv7/mx6/soc.c ? ? ? ? ? ? ?| ? 57 +
?arch/arm/include/asm/arch-mx6/ccm_regs.h ?| ?894 +++++++++++++++
?arch/arm/include/asm/arch-mx6/clock.h ? ? | ? 50 +
?arch/arm/include/asm/arch-mx6/gpio.h ? ? ?| ? 35 +
?arch/arm/include/asm/arch-mx6/imx-regs.h ?| ?233 ++++
?arch/arm/include/asm/arch-mx6/iomux-v3.h ?| ?104 ++
?arch/arm/include/asm/arch-mx6/mx6x_pins.h | 1683 +++++++++++++++++++++++++++++
?arch/arm/include/asm/arch-mx6/sys_proto.h | ? 38 +

?12 files changed, 3666 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/mx6/Makefile new file +48 -0

new file mode 100644
index 0000000..b0da028
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB ?= $(obj)lib$(SOC).o
+
+COBJS ? ? ? ?= soc.o clock.o iomux-v3.o
+SOBJS ? = lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): ? ? ?$(OBJS)
+ ? ? $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/armv7/mx6/clock.c new file +299 -0

new file mode 100644
index 0000000..e0d9c6f
@@ -0,0 +1,388 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/clock.h>
+
+enum pll_clocks {
+ ? ? PLL_SYS, ? ? ? ?/* System PLL */
+ ? ? PLL_BUS, ? ? ? ?/* System Bus PLL*/
+ ? ? PLL_USBOTG, ? ? /* OTG USB PLL */
+ ? ? PLL_ENET, ? ? ? /* ENET PLL */
+};
+
+struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
+
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+ ? ? u32 div;
+
+ ? ? switch (pll) {
+ ? ? case PLL_SYS:
+ ? ? ? ? ? ? div = __raw_readl(&imx_ccm->analog_pll_sys);
+ ? ? ? ? ? ? div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
+
+ ? ? ? ? ? ? return infreq * (div >> 1);
+ ? ? case PLL_BUS:
+ ? ? ? ? ? ? div = __raw_readl(&imx_ccm->analog_pll_528);
+ ? ? ? ? ? ? div &= BM_ANADIG_PLL_528_DIV_SELECT;
+
+ ? ? ? ? ? ? return infreq * (20 + (div << 1));
+ ? ? case PLL_USBOTG:
+ ? ? ? ? ? ? div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
+ ? ? ? ? ? ? ? ?div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
+
+ ? ? ? ? ? ? return infreq * (20 + (div << 1));
+ ? ? case PLL_ENET:
+ ? ? ? ? ? ? div = __raw_readl(&imx_ccm->analog_pll_enet);
+ ? ? ? ? ? ? div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
+
+ ? ? ? ? ? ? return (div == 3 ? 125000000 : 25000000 * (div << 1));
+ ? ? default:
+ ? ? ? ? ? ? return 0;
+ ? ? }
+ ? ? /* NOTREACHED */
+}
+
+static u32 get_mcu_main_clk(void)
+{
+ ? ? u32 reg, freq;
+
+ ? ? reg = __raw_readl(&imx_ccm->cacrr);
+ ? ? reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
+ ? ? reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
+ ? ? freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+
+ ? ? return freq / (reg + 1);
+}
+
+static u32 get_periph_clk(void)
+{
+ ? ? u32 reg, freq = 0;
+
+ ? ? reg = __raw_readl(&imx_ccm->cbcdr);
+ ? ? if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ ? ? ? ? ? ? reg = __raw_readl(&imx_ccm->cbcmr);
+ ? ? ? ? ? ? reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
+ ? ? ? ? ? ? reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
+
+ ? ? ? ? ? ? switch (reg) {
+ ? ? ? ? ? ? case 0:
+ ? ? ? ? ? ? ? ? ? ? freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? case 1:
+ ? ? ? ? ? ? case 2:
+ ? ? ? ? ? ? ? ? ? ? freq = CONFIG_SYS_MX6_HCLK;
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? default:
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? }
+ ? ? } else {
+ ? ? ? ? ? ? reg = __raw_readl(&imx_ccm->cbcmr);
+ ? ? ? ? ? ? reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
+ ? ? ? ? ? ? reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
+
+ ? ? ? ? ? ? switch (reg) {
+ ? ? ? ? ? ? case 0:
+ ? ? ? ? ? ? ? ? ? ? freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? case 1:
+ ? ? ? ? ? ? ? ? ? ? freq = PLL2_PFD2_FREQ;
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? case 2:
+ ? ? ? ? ? ? ? ? ? ? freq = PLL2_PFD0_FREQ;
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? case 3:
+ ? ? ? ? ? ? ? ? ? ? freq = PLL2_PFD2_DIV_FREQ;
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? default:
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? }
+ ? ? }
+
+ ? ? return freq;
+}
+
+
+static u32 get_ahb_clk(void)
+{
+ ? ? u32 reg, ahb_podf;
+
+ ? ? reg = __raw_readl(&imx_ccm->cbcdr);
+ ? ? reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+ ? ? ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+ ? ? return get_periph_clk() / (ahb_podf + 1);
+}
+
+static u32 get_ipg_clk(void)
+{
+ ? ? u32 reg, ipg_podf;
+
+ ? ? reg = __raw_readl(&imx_ccm->cbcdr);
+ ? ? reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
+ ? ? ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+
+ ? ? return get_ahb_clk() / (ipg_podf + 1);
+}
+
+static u32 get_ipg_per_clk(void)
+{
+ ? ? u32 reg, perclk_podf;
+
+ ? ? reg = __raw_readl(&imx_ccm->cscmr1);
+ ? ? perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
+
+ ? ? return get_ipg_clk() / (perclk_podf + 1);
+}
+
+static u32 get_uart_clk(void)
+{
+ ? ? u32 reg, uart_podf;
+
+ ? ? reg = __raw_readl(&imx_ccm->cscdr1);
+ ? ? reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
+ ? ? uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+
+ ? ? return PLL3_80M / (uart_podf + 1);
+}
+
+
+static u32 get_cspi_clk(void)
+{
+ ? ? u32 reg, cspi_podf;
+
+ ? ? reg = __raw_readl(&imx_ccm->cscdr2);
+ ? ? reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
+ ? ? cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+ ? ? return ?PLL3_60M / (cspi_podf + 1);
+}
+
+static u32 get_axi_clk(void)
+{
+ ? ? u32 root_freq, axi_podf;
+ ? ? u32 cbcdr = ?__raw_readl(&imx_ccm->cbcdr);
+
+ ? ? axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
+ ? ? axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
+
+ ? ? if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
+ ? ? ? ? ? ? if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
+ ? ? ? ? ? ? ? ? ? ? root_freq = PLL2_PFD2_FREQ;
+ ? ? ? ? ? ? else
+ ? ? ? ? ? ? ? ? ? ? root_freq = PLL3_PFD1_FREQ;;
+ ? ? } else
+ ? ? ? ? ? ? root_freq = get_periph_clk();
+
+ ? ? return ?root_freq / (axi_podf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+ ? ? u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
+
+ ? ? cscmr1 = ?__raw_readl(&imx_ccm->cscmr1);
+ ? ? emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
+ ? ? emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
+ ? ? emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
+ ? ? emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
+
+ ? ? switch (emi_clk_sel) {
+ ? ? case 0:
+ ? ? ? ? ? ? root_freq = get_axi_clk();
+ ? ? ? ? ? ? break;
+ ? ? case 1:
+ ? ? ? ? ? ? root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+ ? ? ? ? ? ? break;
+ ? ? case 2:
+ ? ? ? ? ? ? root_freq = PLL2_PFD2_FREQ;
+ ? ? ? ? ? ? break;
+ ? ? case 3:
+ ? ? ? ? ? ? root_freq = PLL2_PFD0_FREQ;
+ ? ? ? ? ? ? break;
+ ? ? }
+
+ ? ? return root_freq / (emi_slow_pof + 1);
+}
+
+static u32 get_mmdc_ch0_clk(void)
+{
+ ? ? u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+ ? ? u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+
+ ? ? return get_periph_clk() / (mmdc_ch0_podf + 1);
+}
+
+static u32 get_usdhc1_clk(void)
+{
+ ? ? u32 root_freq = 0;
+ ? ? u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+ ? ? u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+ ? ? u32 usdhc1_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
+
+ ? ? if (cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL)
+ ? ? ? ? ? ? root_freq = PLL2_PFD0_FREQ;
+ ? ? else
+ ? ? ? ? ? ? root_freq = PLL2_PFD2_FREQ;
+
+ ? ? return root_freq / (usdhc1_podf + 1);
+}
+
+static u32 get_usdhc2_clk(void)
+{
+ ? ? u32 root_freq = 0;
+ ? ? u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+ ? ? u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+ ? ? u32 usdhc2_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
+
+ ? ? if (cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL)
+ ? ? ? ? ? ? root_freq = PLL2_PFD0_FREQ;
+ ? ? else
+ ? ? ? ? ? ? root_freq = PLL2_PFD2_FREQ;
+
+ ? ? return root_freq / (usdhc2_podf + 1);
+}
+
+static u32 get_usdhc3_clk(void)
+{
+ ? ? u32 root_freq = 0;
+ ? ? u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+ ? ? u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+ ? ? u32 usdhc3_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
+
+ ? ? if (cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL)
+ ? ? ? ? ? ? root_freq = PLL2_PFD0_FREQ;
+ ? ? else
+ ? ? ? ? ? ? root_freq = PLL2_PFD2_FREQ;
+
+ ? ? return root_freq / (usdhc3_podf + 1);
+}
+
+static u32 get_usdhc4_clk(void)
+{
+ ? ? u32 root_freq = 0;
+ ? ? u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+ ? ? u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+ ? ? u32 usdhc4_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
+
+ ? ? if (cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL)
+ ? ? ? ? ? ? root_freq = PLL2_PFD0_FREQ;
+ ? ? else

arch/arm/cpu/armv7/mx6/clock.c line 66

Quoted 4 lines

arch/arm/cpu/armv7/mx6/clock.c new file +4 -0

+ ? ? ? ? ? ? root_freq = PLL2_PFD2_FREQ;
+
+ ? ? return root_freq / (usdhc4_podf + 1);
+}

All get_usdhcX function are identical, except for two masks (MXC_CCM_CSCDR1_USDHCx_PODF_MASK and MXC_CCM_CSCMR1_USDHCx_CLK_SEL). Merge them in a get_usdhc_clk(usdhc_number)

Quoted 98 lines

arch/arm/cpu/armv7/mx6/iomux-v3.c new file +89 -0

new file mode 100644
index 0000000..ff934ea
@@ -0,0 +1,76 @@
+/*
+ * Based on the iomux-v3.c from Linux kernel:
+ * Copyright (C) 2008 by Sascha Hauer <[email protected]>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ * ? ? ? ? ? ? ? ? ? ? ? <[email protected]>
+ *
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/arch/iomux-v3.h>
+
+static void *base;
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+{
+ ? ? u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ ? ? u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ ? ? u32 sel_input_ofs =
+ ? ? ? ? ? ? (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ ? ? u32 sel_input =
+ ? ? ? ? ? ? (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+ ? ? u32 pad_ctrl_ofs =
+ ? ? ? ? ? ? (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+ ? ? u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+ ? ? if (mux_ctrl_ofs)
+ ? ? ? ? ? ? __raw_writel(mux_mode, base + mux_ctrl_ofs);
+
+ ? ? if (sel_input_ofs)
+ ? ? ? ? ? ? __raw_writel(sel_input, base + sel_input_ofs);
+
+ ? ? if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+ ? ? ? ? ? ? __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+
+ ? ? return 0;
+}
+
+int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+{
+ ? ? iomux_v3_cfg_t *p = pad_list;
+ ? ? int i;
+ ? ? int ret;
+
+ ? ? for (i = 0; i < count; i++) {
+ ? ? ? ? ? ? ret = imx_iomux_v3_setup_pad(*p);
+ ? ? ? ? ? ? if (ret)
+ ? ? ? ? ? ? ? ? ? ? return ret;
+ ? ? ? ? ? ? p++;
+ ? ? }
+ ? ? return 0;
+}
+
+void imx_iomux_v3_init(void *iomux_v3_base)
+{
+ ? ? base = iomux_v3_base;
+}
 
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(unsigned char *mac)
+{
+ ? ? struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ ? ? struct fuse_bank *bank = &iim->bank[4];
+ ? ? struct fuse_bank4_regs *fuse =
+ ? ? ? ? ? ? ? ? ? ? (struct fuse_bank4_regs *)bank->fuse_regs;
+
+ ? ? u32 mac_lo = readl(&fuse->mac_addr_low);
+ ? ? u32 mac_hi = readl(&fuse->mac_addr_high);
+
+ ? ? *(u32 *)mac = mac_lo;
+

arch/arm/cpu/armv7/mx6/iomux-v3.c

Quoted 4 lines

+ ? ? mac[4] = mac_hi & 0xff;
+ ? ? mac[5] = (mac_hi >> 8) & 0xff;

arch/arm/cpu/armv7/mx6/iomux-v3.c new file +2 -0

+
+}

Even if the implementation is slightly different, this function (except for the bank number) does the same things for MX5 and MX6 - you can als put it into imx-common.

Quoted 62 lines

arch/arm/cpu/armv7/mx6/iomux-v3.c new file +1 -0

+#endif

arch/arm/include/asm/arch-mx6/ccm_regs.h new file +54 -0

new file mode 100644
index 0000000..e8f0a93
@@ -0,0 +1,894 @@
+/*
+ * Freescale ANADIG Register Definitions
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ?02111-1307 USA
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+
+struct imx_ccm_reg {
+ ? ? u32 ccr; ? ? ? ?/* 0x0000 */
+ ? ? u32 ccdr;
+ ? ? u32 csr;
+ ? ? u32 ccsr;
+ ? ? u32 cacrr; ? ? ?/* 0x0010*/
+ ? ? u32 cbcdr;
+ ? ? u32 cbcmr;
+ ? ? u32 cscmr1;
+ ? ? u32 cscmr2; ? ? /* 0x0020 */
+ ? ? u32 cscdr1;
+ ? ? u32 cs1cdr;
+ ? ? u32 cs2cdr;
+ ? ? u32 cdcdr; ? ? ?/* 0x0030 */
+ ? ? u32 chscdr;
+ ? ? u32 cscdr2;
+ ? ? u32 cscdr3;
+ ? ? u32 cscdr4; ? ? /* 0x0040 */
+ ? ? u32 resv0;
+ ? ? u32 cdhipr;
+ ? ? u32 cdcr;
+ ? ? u32 ctor; ? ? ? /* 0x0050 */
+ ? ? u32 clpcr;
+ ? ? u32 cisr;
+ ? ? u32 cimr;
+ ? ? u32 ccosr; ? ? ?/* 0x0060 */
+ ? ? u32 cgpr;
+ ? ? u32 CCGR0;
+ ? ? u32 CCGR1;
+ ? ? u32 CCGR2; ? ? ?/* 0x0070 */

arch/arm/include/asm/arch-mx6/ccm_regs.h line 59

Quoted 5 lines

arch/arm/include/asm/arch-mx6/ccm_regs.h new file +5 -0

+ ? ? u32 CCGR3;
+ ? ? u32 CCGR4;
+ ? ? u32 CCGR5;
+ ? ? u32 CCGR6; ? ? ?/* 0x0080 */
+ ? ? u32 CCGR7

Checking this there something confusing in actual code. There is struct mxc_ccm_reg in crm_regs.h and struct clkctl in imx-regs.h. The two

structure are identical. I am asking myself why...it seems to me that someting went wrong.
If there is no evident reason, we should even clean up this point.

And it is better you use one of the already supplied names (mxc_ccm_reg or clkctl), without adding a new one.

Quoted 36 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +28 -0

new file mode 100644
index 0000000..1dc34e9
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+
+/* GPIO registers */
+struct gpio_regs {
+ ? ? u32 ? ? gpio_dr;

arch/arm/include/asm/arch-mx6/gpio.h line 35

Quoted 5 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +5 -0

+ ? ? u32 ? ? gpio_dir;
+ ? ? u32 ? ? gpio_psr;
+};
+
+#endif

Maybe do we find a way to add a common include directory ? This file is duplicated. We can use include/asm/arch/imx-common

Best regards,
Stefano Babic

--
=====================================================================
DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
=====================================================================

Quoted 4 lines

All get_usdhcX function are identical, except for two masks (MXC_CCM_CSCDR1_USDHCx_PODF_MASK and MXC_CCM_CSCMR1_USDHCx_CLK_SEL). Merge them in a get_usdhc_clk(usdhc_number)

Yes, I also notice this when writing the code. At that time, I just think to make clear about the code.
Now, I think your comments is also reasonable. I will change it later.

Quoted 13 lines

Quoted 13 lines

arch/arm/cpu/armv7/mx6/soc.c new file +13 -0

+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(unsigned char *mac)
+{
+     struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+     struct fuse_bank *bank = &iim->bank[4];
+     struct fuse_bank4_regs *fuse =
+                     (struct fuse_bank4_regs *)bank->fuse_regs;
+
+     u32 mac_lo = readl(&fuse->mac_addr_low);
+     u32 mac_hi = readl(&fuse->mac_addr_high);
+
+     *(u32 *)mac = mac_lo;
+

Quoted 8 lines

arch/arm/cpu/armv7/mx6/soc.c line 56

Quoted 4 lines

arch/arm/cpu/armv7/mx6/soc.c new file +4 -0

+     mac[4] = mac_hi & 0xff;
+     mac[5] = (mac_hi >> 8) & 0xff;
+
+}

Even if the implementation is slightly different, this function (except for the bank number) does the same things for MX5 and MX6 - you can als put it into imx-common.

Stefano, there is big difference for the memory layout. On i.mx5, the layout is:

32-bit 32-bit 32-bit 32-bit 32-bit 32-bit
mac0 mac1 mac2 mac3 mac4 mac5

but on i.mx6:

32bit 32bit [low 16bit]
mac[0-3] mac[4-5]

It's due to i.mx6q use OCOTP fuse-controller other than the fuse-box on the i.mx5.

Thus, I think, I will keep the code as it is.

Quoted 3 lines

Checking this there something confusing in actual code. There is struct mxc_ccm_reg in crm_regs.h and struct clkctl in imx-regs.h. The two

I did not searched the clkctl in the patch-set by using:
grep -nR clkctl *

Quoted 6 lines

structure are identical. I am asking myself why...it seems to me that someting went wrong.
If there is no evident reason, we should even clean up this point.

And it is better you use one of the already supplied names (mxc_ccm_reg or clkctl), without adding a new one.

Yes, I'm using mxc_ccm_reg.

Quoted 2 lines

Maybe do we find a way to add a common include directory ? This file is duplicated. We can use include/asm/arch/imx-common

I don't find one good way to add a common include directory. If I try to find one,
I will put this head file to imx-common.

Quoted 6 lines · Jason Hui

Quoted 4 lines

All get_usdhcX function are identical, except for two masks (MXC_CCM_CSCDR1_USDHCx_PODF_MASK and MXC_CCM_CSCMR1_USDHCx_CLK_SEL). Merge them in a get_usdhc_clk(usdhc_number)

Quoted 1 line

Yes, I'm using mxc_ccm_reg.

Ok - this structure is also used in most drivers - if I am not wrong (and I will better check), the struct clkctl is used only to generate the offsets in asm-offsets.h. If it is so, it could be drop in a future clean up patch...

Quoted 7 lines

Quoted 3 lines

Maybe do we find a way to add a common include directory ? This file is duplicated. We can use include/asm/arch/imx-common

I don't find one good way to add a common include directory. If I try to find one,
I will put this head file to imx-common.

The easy way is to add include/asm/arch-imx-common, and then the header are explicitely included as #include <asm/arch-imx-common/..>. I have seen only another example in U-Boot for armv7:

arch/arm/cpu/armv7/highbank/timer.c:#include <asm/arch-armv7/systimer.h>

I am opened to other solutions, too, but I think that introducing a common repository for IMX include files (as Linux with plat_imx does) is the way to do.

Best regards,
Stefano Babic

--
=====================================================================
DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
=====================================================================

Signed-off-by Jason Liu <[email protected]>

---
 drivers/gpio/mxc_gpio.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

drivers/gpio/mxc_gpio.c +0 -0

index a7f36b2..908808d 100644
@@ -40,10 +40,10 @@ static unsigned long gpio_ports[] = {
 	[0] = GPIO1_BASE_ADDR,
 	[1] = GPIO2_BASE_ADDR,

The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller.

The usdhc controller is almost compatible with esdhc except it adds one misc control register from user using experience.

Signed-off-by Jason Liu <[email protected]>

---
 drivers/mmc/fsl_esdhc.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

drivers/mmc/fsl_esdhc.c +0 -0

index ec953f0..cd17ef2 100644

drivers/mmc/fsl_esdhc.c +0 -0

 	regs = (struct fsl_esdhc *)cfg->esdhc_base;
 

/* First reset the eSDHC controller */

Quoted 16 lines

The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller.

The usdhc controller is almost compatible with esdhc except it adds one misc control register from user using experience.

Signed-off-by Jason Liu <[email protected]>

---
?drivers/mmc/fsl_esdhc.c | ? 14 +++++++++++++- ?1 files changed, 13 insertions(+), 1 deletions(-)

drivers/mmc/fsl_esdhc.c +0 -0

index ec953f0..cd17ef2 100644

drivers/mmc/fsl_esdhc.c struct fsl_esdhc { · line 66

Quoted 10 lines

drivers/mmc/fsl_esdhc.c +6 -1

@@ -58,7 +58,12 @@ struct fsl_esdhc {
 ? ? ? uint ? ?autoc12err;
 ? ? ? uint ? ?hostcapblt;
 ? ? ? uint ? ?wml;
- ? ? char ? ?reserved1[8];
+#if defined(CONFIG_FSL_USDHC)
+ ? ? uint ? ?mixctrl;
+ ? ? char ? ?reserved1[4];
+#else
+ ? ? char ? ?reserved1[8];
+#endif

Hi Jason,

can't we just drop this ifdef ?

Quoted 12 lines

drivers/mmc/fsl_esdhc.c +0 -0

 ? ? ? uint ? ?fevt;
 ? ? ? char ? ?reserved2[168];
 ? ? ? uint ? ?hostver;

@@ -298,6 +303,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 struct mmc_data *data)
 

? ? ? /* Send the command */
? ? ? esdhc_write32(&regs->cmdarg, cmd->cmdarg);

drivers/mmc/fsl_esdhc.c +3 -0

+#if defined(CONFIG_FSL_USDHC)
+ ? ? esdhc_write32(&regs->mixctrl, xfertyp & 0xFFFF);
+#endif

Quoted 1 line

? ? ? esdhc_write32(&regs->xfertyp, xfertyp);

Why is this duplicated? This seems like a huge user-experience nonsense to me :)

If you write to xfertyp register, you still have to write the same thing to mixctrl? Or if you do it vice versa, won't it work ? Why did you add the register?

Quoted 8 lines

? ? ? /* Wait for the command to complete */

drivers/mmc/fsl_esdhc.c +0 -0

@@ -482,7 +490,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct
 fsl_esdhc_cfg *cfg)
 
 ? ? ? mmc = malloc(sizeof(struct mmc));
 

drivers/mmc/fsl_esdhc.c struct fsl_esdhc { · line 66

Quoted 5 lines

drivers/mmc/fsl_esdhc.c +4 -0

+#if defined(CONFIG_FSL_USDHC)
+ ? ? sprintf(mmc->name, "FSL_USDHC");
+#else
 ? ? ? sprintf(mmc->name, "FSL_ESDHC");
+#endif

Why not just rename it to FSL_SDHC and be done with it ?

Quoted 4 lines

drivers/mmc/fsl_esdhc.c +0 -0

 ? ? ? regs = (struct fsl_esdhc *)cfg->esdhc_base;
 

? ? ? /* First reset the eSDHC controller */

Quoted 29 lines

Quoted 16 lines

The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller.

The usdhc controller is almost compatible with esdhc except it adds one misc control register from user using experience.

Signed-off-by Jason Liu <[email protected]>

---
 drivers/mmc/fsl_esdhc.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

drivers/mmc/fsl_esdhc.c +0 -0

index ec953f0..cd17ef2 100644

drivers/mmc/fsl_esdhc.c struct fsl_esdhc { · line 66

Quoted 10 lines

drivers/mmc/fsl_esdhc.c +6 -1

@@ -58,7 +58,12 @@ struct fsl_esdhc {
      uint    autoc12err;
      uint    hostcapblt;
      uint    wml;
-     char    reserved1[8];
+#if defined(CONFIG_FSL_USDHC)
+     uint    mixctrl;
+     char    reserved1[4];
+#else
+     char    reserved1[8];
+#endif

Hi Jason,

Quoted 1 line

can't we just drop this ifdef ?

Yes, I think we can. I will drop it later.

Quoted 17 lines

drivers/mmc/fsl_esdhc.c esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, · line 310

Quoted 13 lines

drivers/mmc/fsl_esdhc.c +3 -0

      uint    fevt;
      char    reserved2[168];
      uint    hostver;

@@ -298,6 +303,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 struct mmc_data *data)
 
      /* Send the command */
      esdhc_write32(&regs->cmdarg, cmd->cmdarg);
+#if defined(CONFIG_FSL_USDHC)
+     esdhc_write32(&regs->mixctrl, xfertyp & 0xFFFF);
+#endif
      esdhc_write32(&regs->xfertyp, xfertyp);

Why is this duplicated? This seems like a huge user-experience nonsense to me :)

Quoted 3 lines

If you write to xfertyp register, you still have to write the same thing to mixctrl? Or if you do it vice versa, won't it work ? Why did you add the register?

This is due to that on i.mx6q usdhc, it adds one extra mixctrl(offset 0x48) register to accommodate the
low 16-bits of tranfertype and the high 16-bits of tranfertype will still go via the xfertyp register.
On the i.mx6q usdhc, the xfertyp(offset 0xc) register, the low 16-bits is not used and only
high 16-bits have been used. I can make the above code clear as the followings,

#if defined(CONFIG_FSL_USDHC) esdhc_write32(&regs->mixctrl, xfertyp & 0x0000FFFF); esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000); #else
esdhc_write32(&regs->xfertyp, xfertyp); #endif

Quoted 7 lines

Quoted 7 lines

drivers/mmc/fsl_esdhc.c +0 -0

      /* Wait for the command to complete */

@@ -482,7 +490,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct
 fsl_esdhc_cfg *cfg)
 
      mmc = malloc(sizeof(struct mmc));
 

Quoted 7 lines

drivers/mmc/fsl_esdhc.c int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) · line 497

Quoted 5 lines

drivers/mmc/fsl_esdhc.c +4 -0

+#if defined(CONFIG_FSL_USDHC)
+     sprintf(mmc->name, "FSL_USDHC");
+#else
      sprintf(mmc->name, "FSL_ESDHC");
+#endif

Why not just rename it to FSL_SDHC and be done with it ?

OK, I will do it.

Quoted 3 lines

Quoted 3 lines

drivers/mmc/fsl_esdhc.c +0 -0

      regs = (struct fsl_esdhc *)cfg->esdhc_base;
 

      /* First reset the eSDHC controller */

Jason Liu

Quoted 30 lines · Marek Vasut

Quoted 29 lines

Quoted 16 lines

The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller.

The usdhc controller is almost compatible with esdhc except it adds one misc control register from user using experience.

Signed-off-by Jason Liu <[email protected]>

---
?drivers/mmc/fsl_esdhc.c | ? 14 +++++++++++++- ?1 files changed, 13 insertions(+), 1 deletions(-)

drivers/mmc/fsl_esdhc.c +0 -0

index ec953f0..cd17ef2 100644

drivers/mmc/fsl_esdhc.c struct fsl_esdhc { · line 66

Quoted 10 lines

drivers/mmc/fsl_esdhc.c +6 -1

@@ -58,7 +58,12 @@ struct fsl_esdhc {
 ? ? ? uint ? ?autoc12err;
 ? ? ? uint ? ?hostcapblt;
 ? ? ? uint ? ?wml;
- ? ? char ? ?reserved1[8];
+#if defined(CONFIG_FSL_USDHC)
+ ? ? uint ? ?mixctrl;
+ ? ? char ? ?reserved1[4];
+#else
+ ? ? char ? ?reserved1[8];
+#endif

Hi Jason,

Quoted 3 lines

Quoted 1 line

can't we just drop this ifdef ?

Yes, I think we can. I will drop it later.

Please drop now so it's not forgotten ;-)

Quoted 30 lines

Quoted 17 lines

Quoted 12 lines

drivers/mmc/fsl_esdhc.c +0 -0

 ? ? ? uint ? ?fevt;
 ? ? ? char ? ?reserved2[168];
 ? ? ? uint ? ?hostver;

@@ -298,6 +303,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 struct mmc_data *data)
 

? ? ? /* Send the command */
? ? ? esdhc_write32(&regs->cmdarg, cmd->cmdarg);

drivers/mmc/fsl_esdhc.c +3 -0

+#if defined(CONFIG_FSL_USDHC)
+ ? ? esdhc_write32(&regs->mixctrl, xfertyp & 0xFFFF);
+#endif

Quoted 1 line

? ? ? esdhc_write32(&regs->xfertyp, xfertyp);

Why is this duplicated? This seems like a huge user-experience nonsense to me :)

Quoted 3 lines

If you write to xfertyp register, you still have to write the same thing to mixctrl? Or if you do it vice versa, won't it work ? Why did you add the register?

This is due to that on i.mx6q usdhc, it adds one extra mixctrl(offset 0x48) register to accommodate the
low 16-bits of tranfertype and the high 16-bits of tranfertype will still go via the xfertyp register.
On the i.mx6q usdhc, the xfertyp(offset 0xc) register, the low 16-bits is not used and only
high 16-bits have been used. I can make the above code clear as the followings,

Quoted 6 lines

#if defined(CONFIG_FSL_USDHC) esdhc_write32(&regs->mixctrl, xfertyp & 0x0000FFFF); esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000); #else
esdhc_write32(&regs->xfertyp, xfertyp); #endif

Well this is insane, is the datasheet for mx6q available already so I can check for myself?

Quoted 23 lines

Quoted 8 lines

Quoted 8 lines

? ? ? /* Wait for the command to complete */

drivers/mmc/fsl_esdhc.c +0 -0

@@ -482,7 +490,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct
 fsl_esdhc_cfg *cfg)
 
 ? ? ? mmc = malloc(sizeof(struct mmc));
 

Quoted 7 lines

drivers/mmc/fsl_esdhc.c struct fsl_esdhc { · line 66

Quoted 5 lines

drivers/mmc/fsl_esdhc.c +4 -0

+#if defined(CONFIG_FSL_USDHC)
+ ? ? sprintf(mmc->name, "FSL_USDHC");
+#else
 ? ? ? sprintf(mmc->name, "FSL_ESDHC");
+#endif

Why not just rename it to FSL_SDHC and be done with it ?

OK, I will do it.

Quoted 3 lines

Quoted 3 lines

drivers/mmc/fsl_esdhc.c +0 -0

 ? ? ? regs = (struct fsl_esdhc *)cfg->esdhc_base;
 

? ? ? /* First reset the eSDHC controller */

Jason Liu

Quoted 2 lines

Well this is insane, is the datasheet for mx6q available already so I can check for myself?

This is mx6q usdhc design and datasheet is not public now. Without this, the mmc driver does not work.

Quoted 5 lines · Jason Hui

Quoted 2 lines

Well this is insane, is the datasheet for mx6q available already so I can check for myself?

This is mx6q usdhc design and datasheet is not public now. Without this, the mmc driver does not work.

Can you at least add a useful comment explaining why it is required, maybe copying only the few lines from the manual where it is described, or adding the errata number if this is due to a bug ?

Best regards,
Stefano

--
=====================================================================
DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
=====================================================================

Quoted 4 lines · Jason Hui

Quoted 3 lines

Quoted 2 lines

Well this is insane, is the datasheet for mx6q available already so I can check for myself?

Quoted 6 lines

Quoted 2 lines

This is mx6q usdhc design and datasheet is not public now. Without this, the mmc driver does not work.

Can you at least add a useful comment explaining why it is required, maybe copying only the few lines from the manual where it is described, or adding the errata number if this is due to a bug ?

It's not the bug but the design.

I will extend the commit message.

Quoted 10 lines

Best regards,
Stefano

--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================

The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller.

The usdhc controller is almost compatible with esdhc except it adds one misc control register from user using experience.

Signed-off-by Jason Liu <[email protected]>

---

 drivers/mmc/fsl_esdhc.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

drivers/mmc/fsl_esdhc.c +9 -1

index ec953f0..cd17ef2 100644
@@ -58,7 +58,12 @@ struct fsl_esdhc {
 	uint	autoc12err;
 	uint	hostcapblt;
 	uint	wml;
-	char	reserved1[8];
+#if defined(CONFIG_FSL_USDHC)
+	uint    mixctrl;
+	char    reserved1[4];
+#else
+	char    reserved1[8];
+#endif
 	uint	fevt;
 	char	reserved2[168];
 	uint	hostver;

@@ -298,6 +303,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 	/* Send the command */
 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
+#if defined(CONFIG_FSL_USDHC)
+	esdhc_write32(&regs->mixctrl, xfertyp & 0xFFFF);
+#endif
 	esdhc_write32(&regs->xfertyp, xfertyp);
 
 	/* Wait for the command to complete */

Hi Jason,

board/freescale/mx6qarm2/mx6qarm2.c

Quoted 4 lines · Jason Liu

board/freescale/mx6qarm2/mx6qarm2.c new file +4 -0

+int board_init(void)
+{
+ ? ? ? /* board id for linux */
+ ? ? ? gd->bd->bi_arch_number = MACH_TYPE_MX61_ARD;

Please remove this line and define the mach type in the board header file.

Regards,

Fabio Estevam

board/freescale/mx6qarm2/mx6qarm2.c

Quoted 6 lines · Jason Liu

board/freescale/mx6qarm2/mx6qarm2.c new file +6 -0

+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ ? ? ? struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ ? ? ? if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ ? ? ? ? ? ? ? *cd = gpio_get_value(107); /*GPIO6_11*/

GPIO6_11 number is 5*32 + 11 = 171 , not 107.

Also, in order to use gpio_get_value you need to configure the pin as GPIO first.

...

Review

Quoted 3 lines

(quoted diff) +3 -0

+#define CONFIG_SYS_SDRAM_BASE ? ? ? ? ?(PHYS_SDRAM)
+#define CONFIG_SYS_INIT_RAM_ADDR ? ? ? (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE ? ? ? (IRAM_SIZE)

Unneeded parentheses.

Regards,

Fabio Estevam

Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.

Signed-off-by Jason Liu <[email protected]>

---
 MAINTAINERS                           |    1 +
 board/freescale/mx6qarm2/Makefile     |   48 ++++++++++
 board/freescale/mx6qarm2/imximage.cfg |  167 +++++++++++++++++++++++++++++++++
 board/freescale/mx6qarm2/mx6qarm2.c   |  163 ++++++++++++++++++++++++++++++++
 boards.cfg                            |    1 +
 include/configs/mx6qarm2.h            |  163 ++++++++++++++++++++++++++++++++
 6 files changed, 543 insertions(+), 0 deletions(-)

board/freescale/mx6qarm2/Makefile new file +0 -0

new file mode 100644
index 0000000..5ca7ec1
@@ -0,0 +1,48 @@

board/freescale/mx6qarm2/mx6qarm2.c new file +0 -0

new file mode 100644
index 0000000..63322a9
@@ -0,0 +1,163 @@

board/freescale/mx6qarm2/mx6qarm2.c new file +9 -0

+int board_mmc_init(bd_t *bis)
+{
+	s32 status = 0;
+	u32 index = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(

board/freescale/mx6qarm2/mx6qarm2.c new file +8 -0

+			return status;
+		}
+
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	}
+
+	return status;
+}

Hi Jason,

Two neats in addition to Fabio's comments below:

Quoted 12 lines · Jason Liu

Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.

Signed-off-by Jason Liu <[email protected]>

---

?MAINTAINERS ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?1 +
?board/freescale/mx6qarm2/Makefile ? ? | ? 48 ++++++++++
?board/freescale/mx6qarm2/imximage.cfg | ?167 +++++++++++++++++++++++++++++++++
?board/freescale/mx6qarm2/mx6qarm2.c ? | ?163 ++++++++++++++++++++++++++++++++
?boards.cfg ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
?include/configs/mx6qarm2.h ? ? ? ? ? ?| ?163 ++++++++++++++++++++++++++++++++

?6 files changed, 543 insertions(+), 0 deletions(-)

[...]

Quoted 6 lines

board/freescale/mx6qarm2/Makefile new file +0 -0

new file mode 100644
index 0000000..5ca7ec1
@@ -0,0 +1,48 @@

[...]

board/freescale/mx6qarm2/Makefile

Quoted 5 lines

board/freescale/mx6qarm2/Makefile new file +5 -0

+clean:
+ ? ? rm -f $(SOBJS) $(OBJS)
+
+distclean: ? clean
+ ? ? rm -f $(LIB) core *.bak .depend

Please, remove clean and distclean targets - they have no use and are being removed from board directory level Makefiles.

[...]

Quoted 6 lines

board/freescale/mx6qarm2/mx6qarm2.c new file +0 -0

new file mode 100644
index 0000000..63322a9
@@ -0,0 +1,163 @@

[...]

Quoted 13 lines

board/freescale/mx6qarm2/mx6qarm2.c new file +13 -0

+int board_mmc_init(bd_t *bis)
+{
+ ? ? s32 status = 0;
+ ? ? u32 index = 0;
+
+ ? ? for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ ? ? ? ? ? ? switch (index) {
+ ? ? ? ? ? ? case 0:
+ ? ? ? ? ? ? ? ? ? ? imx_iomux_v3_setup_multiple_pads(
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? case 1:
+ ? ? ? ? ? ? ? ? ? ? imx_iomux_v3_setup_multiple_pads(

Quoted 6 lines

+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? default:
+ ? ? ? ? ? ? ? ? ? ? printf("Warning: you configured more USDHC controllers"
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? "(%d) then supported by the board (%d)\n",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? index+1, CONFIG_SYS_FSL_USDHC_NUM);

Is it possible to put spaces around the '+' sign?

board/freescale/mx6qarm2/mx6qarm2.c line 48

Quoted 9 lines

+ ? ? ? ? ? ? ? ? ? ? return status;
+ ? ? ? ? ? ? }

board/freescale/mx6qarm2/mx6qarm2.c new file +6 -0

+
+ ? ? ? ? ? ? status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ ? ? }
+
+ ? ? return status;
+}

[...]

--
Regards,
Igor.

Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.

Signed-off-by Jason Liu <[email protected]>

board/freescale/mx6qarm2/mx6qarm2.c new file +4 -0

+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR, 1},
+	{USDHC4_BASE_ADDR, 1},

Quoted 4 lines · Jason Liu

Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.

Signed-off-by Jason Liu <[email protected]>

Hi Jason,

is mx6qarm2 the official Freescale name ?

Quoted 11 lines

board/freescale/mx6qarm2/mx6qarm2.c new file +10 -0

+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ ? ? {USDHC3_BASE_ADDR, 1},
+ ? ? {USDHC4_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ ? ? struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+

Quoted 4 lines

+ ? ? if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ ? ? ? ? ? ? *cd = gpio_get_value(107); /*GPIO6_11*/
+ ? ? else /* Don't have the CD GPIO pin on board */
+ ? ? ? ? ? ? *cd = 0;

Is it the logic inverted ? If you return always zero, there is no Card in the slot for the MMC framework and there is no attempt to read it. It is working on USDHC4 ?

board/freescale/mx6qarm2/mx6qarm2.c

Quoted 13 lines

board/freescale/mx6qarm2/mx6qarm2.c new file +12 -0

+int board_early_init_f(void)
+{
+ ? ? imx_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
+ ? ? setup_iomux_uart();
+
+ ? ? return 0;
+}
+
+int board_init(void)
+{
+ ? ? /* board id for linux */
+ ? ? gd->bd->bi_arch_number = MACH_TYPE_MX61_ARD;

You should only set CONFIG_MACH_TYPE mx6qarm2.h and drop this line. The set is done in common code.

Quoted 9 lines

+ ? ? /* address of boot parameters */
+ ? ? gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +
+ ? ? /*
+ ? ? ?* Need re-initialization again since base is in BSS
+ ? ? ?* After relocation, base will be clear to zero.
+ ? ? ?*/
+ ? ? imx_iomux_v3_init((void *)IOMUXC_BASE_ADDR);

However, this is a trick. As general rule, we must not use BSS before relocation. Is there no other way to do this ?

include/configs/mx6qarm2.h

Quoted 9 lines

include/configs/mx6qarm2.h new file +8 -0

+
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY ? ? ? ? ? ? 3
+
+#define CONFIG_PRIME ? ? ? ? ? ? ? ? "FEC0"

Ethernet is not yet working, right ? How many Ethernet has this board ?

Best regards,
Stefano Babic

--
=====================================================================
DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
=====================================================================

Quoted 4 lines · Stefano Babic

Quoted 3 lines · Jason Liu

Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.

Quoted 5 lines

Quoted 1 line

Signed-off-by Jason Liu <[email protected]>

Hi Jason,

is mx6qarm2 the official Freescale name ?

Yes, this is the official name.

Quoted 12 lines

Quoted 12 lines

board/freescale/mx6qarm2/mx6qarm2.c new file +10 -0

+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+     {USDHC3_BASE_ADDR, 1},
+     {USDHC4_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+     struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+

Quoted 8 lines

board/freescale/mx6qarm2/mx6qarm2.c line 99

Quoted 4 lines

board/freescale/mx6qarm2/mx6qarm2.c new file +4 -0

+     if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+             *cd = gpio_get_value(107); /*GPIO6_11*/
+     else /* Don't have the CD GPIO pin on board */
+             *cd = 0;

Is it the logic inverted ? If you return always zero, there is no Card in the slot for the MMC framework and there is no attempt to read it. It is working on USDHC4 ?

The framework flow is as the following. The logic is ok.

As the comments before for Fabio, I will drop the MACH_TYPE setting since i.mx6q linux kernel will go device tree and there is no-need for machine type now.

Quoted 11 lines

Quoted 10 lines

board/freescale/mx6qarm2/mx6qarm2.c new file +8 -0

+     /* address of boot parameters */
+     gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+     /*
+      * Need re-initialization again since base is in BSS
+      * After relocation, base will be clear to zero.
+      */
+     imx_iomux_v3_init((void *)IOMUXC_BASE_ADDR);

Quoted 2 lines

However, this is a trick. As general rule, we must not use BSS before relocation. Is there no other way to do this ?

There is no other way for it since we need uart early before the relocation. If you have other way, I really appreciate it.

Quoted 2 lines

Ethernet is not yet working, right ? How many Ethernet has this board ?

yes,I will remove the last line. Only the 1Gbit ENET support on this board.

Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.

include/configs/mx6qarm2.h new file +0 -0

new file mode 100644
index 0000000..a4c7b31

include/configs/mx6qarm2.h new file +26 -0

+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "script=boot.scr\0" \
+       "uimage=uImage\0" \
+       "mmcdev=0\0" \
+       "mmcpart=2\0" \
+       "mmcroot=/dev/mmcblk0p3 rw\0" \
+       "mmcrootfstype=ext3 rootwait\0" \
+       "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+               "root=${mmcroot} " \
+               "rootfstype=${mmcrootfstype}\0" \
+       "loadbootscript=" \
+               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source\0" \
+       "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "bootm\0" \
+       "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+               "root=/dev/nfs " \
+               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+       "netboot=echo Booting from net ...; " \
+               "run netargs; " \
+               "dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \